Introduction to Digital Circuits.

Types of Electronic Signals

• There are two types of electronic signals
– Analog signals. They have continuous values (Fig. 1), generally
between two limits.
– Digital signals. They can take a finite number of levels. In Digital
Electronics, they have only two levels, called LOW and HIGH (Fig. 2)

HIGH Level

LOW Level
 Digital Signals
• In Digital Electronics, a number is assigned to each level1:
LOW level = 0
HIGH level = 1
• The signal transition from a level to other is called an edge.
– Positive or rising edge is the transition from “0” to “1”
– Negative or falling edge is the transition from “1” to “0”

HIGH Level

Negative Edge
Positive Edge

LOW Level 1
Using Positive Logic
 Codes
• One digital signal is called a bit (binary digit) and can take only
two values {0,1}
• A groups of bits (combinations of “0”s and “1”s), called codes, are
used to represent numbers, letters, symbols, and anything else
required in a given application.

• With n bits, nbits, there are 2nbits values, from 0 to 2nbits -1

with n=8 there are 28 = 256 values or combinations, from 0 to
255.
• The number of bits nbits, required to code N combinations can be
found using this formula:
nbits = [log2 N] = [log10 N/ log10 2]

1
Positive Logic
Logic gates. Boolean Algebra
 Gates. Boolean Algebra
• Gates or logic gates are the simplest digital circuits. They are the
building block, from which we can build the rest of the digital circuits.

• There is a mathematical tool that allows describing, analizing and

optimizing (mimimizing) digital circuits: Boolean Algebra.
• This way any digital circuit could be associated to a function in
Boolean Algebra and vice versa.

• A logic function describes the circuit outputs as a function of its inputs

x1 Digital Logic function

x2 y y  f ( x1, x2 , x3 )
Circuit
x3
 Gates. Truth tables
• Another way to describe logical functions is by means of truth
tables, which describe the output value for each input
combination.
• Therefore, in these tables the output should be defined for all
input combinations: n inputs => 2n combinations

Example: y=f(x1, x2 , x3) x1 x2 x3 y

n=3 => 23=8 possible combinations 0 0 0 1
0 0 1 1
0 1 0 0
0 1 1 0
x1 Digital 1 0 0 0
x2 y 1 0 1 1
Circuit
x3
1 1 0 1
1 1 1 0
 AND Gates

AND GATE: It implements a logical function of n inputs that

produce a “1” at the ouput, if and only if the value of all inputs is
“1”

x1 x2 x3 y
Logic symbol of a AND Gate
0 0 0 0
0 0 1 0 x1
0 1 0 0 y
0 1 1 0 xn
1 0 0 0
1 0 1 0 Boolean Operator • : y= x1 • x2 • x3
1 1 0 0 Represents intersection or
1 1 1 1 coincidence

Output is1, If and only if all inputs are 1

 OR Gates
OR Gates: It implements a logical function of n inputs that produce
a “0” at the ouput, if and only if the value of all inputs is “0”

x1 x2 x3 y
Logic symbol of a OR Gate
0 0 0 0
0 0 1 1 x1
0 1 0 1 y
0 1 1 1 xn
1 0 0 1
1 0 1 1 Boolean Operator + : y = x1 + x2 + x3
1 1 0 1 Represents union or existence
1 1 1 1

Output is 1, if any input is 1

 NOT Gates or Inverters
NOT Gates: It implements a logical function of one input that
perform the complementation or inversion. The output is “0” if the
input is “1” and viceversa.

X y Logic symbol of an inverter

0 1
1 0
“bubble” indicates
inversion inversion

Operator  : y = x
Represents inversion or complementation
 NAND y NOR Gates

NAND y NOR Gates: Similar to AND and OR gates, but the output
is inverted.

NAND y= x1 • x2 • x3 NOR y = x1 + x2 + x3
x1 x2 x3 y x1 x2 x3 y
0 0 0 1 0 0 0 1
0 0 1 1 0 0 1 0
0 1 0 1 0 1 0 0
0 1 1 1 0 1 1 0
1 0 0 1 1 0 0 0
1 0 1 1 1 0 1 0
1 1 0 1 1 1 0 0
1 1 1 0 1 1 1 0
Output is 0, if all inputs are 1 Output is 0, if any input is 1
 XOR y XNOR Gates

XOR y XNOR Gates: Two inputs gates, usually used for comparing
and summing. Their truth tables, symbols and operator are:

XOR y= x1  x2 XNOR y= x1  x2

x1 x2 y
x1 x2 y
0 0 1
0 0 0
0 1 0
0 1 1
1 0 0
1 0 1
1 1 1
1 1 0

Output is1, if inputs are

Output is1, if inputs are
equal
different
 Gates. Exercise 1
1.- Write the truth tables and boolean expressions corresponding to
these circuits:

x1
y
x2

x3
 Gates. Exercise 2
2.- Obtain the boolean expression and the equivalent logic circuit that
implements a basic flight protection circuit with an output FLIGHTOK,
using these variables:
a) BAMAX– it is “1” if the bank angle of the plane θ, is greater than its
maximum defined value, “0” otherwise.
b) BAMIN – it is “1” if bank angle of the plane θ, is less than its
minimum defined value, “0” otherwise.
c) AOAMAX – it is “1” if angle of attack of the plane α, is greater than
its minimum defined value, “0” otherwise.
d) AOAMIN– it is “1” if angle of attack of the plane α, is less than its
maximum defined value, “0” otherwise.
 Gates. Exercise 3
3.- Check A-330 emergency generator operation description shown
below:
 Tristate buffer
• Tristate buffer: It is a basic logic circuit used to interconnect other circuits.
Basically, it behaves as a switch. If input EN (enable) is active the switch is
ON connecting input and output and producing a “1” or a “0”,otherwise the
switch is OFF, the output is disconnected or in high impedance “Z”.

EN A B EN
EN 0 0 Z
0 1 Z
1 0 0 A B
A B 1 1 1
 Gates. Reading schematics
• Signals can be active at “1” or “0”
• AND with different active levels

Physically is:
AND NAND NOR OR
• OR with different active levels

Physically is:
OR NOR NAND AND
• NOT with different active levels

Physically is:
NOT NOT
Physical logic gates
 Physical logic gates. Integrated circuits
• Gates are generally fabricated within an integrated circuit. An integrated circuit (IC or
chip) is a set of electronic devices connected on a small piece of silicon (chip or wafer) of
semiconductor material.

• This way of manufacturing saves on energy consumption during operation, obtains

higher processing speeds (internal connections are faster and as technology advances,
transistors are increasingly faster and smaller), save space and therefore obtain a larger
scale integration (increase the number or density of electronic components in each
circuit).
• In this way, the electronic industry classifies integrated circuits according to their scale of
integration.

Table from: Integrated circuit. (2023, February 4).

In Wikipedia. https://en.wikipedia.org/wiki/Integrated_circuit
 Physical logic gates. General technologies
• Another way of classifying gates and digital circuits in general is based on the technology
of their transistors, bipolar or MOS (Metal Oxide Semiconductor).
• Among bipolar technologies we can find TTL circuits (Transistor-Transistor Logic) and
ECL circuits (Emitter-Coupled Logic).
• MOS technology is the most widely used today (computers, mobiles, etc.). Modern
integrated circuits use a variant called CMOS (Complementary MOS) that combines the
use of N-MOS and P-MOS transistors.
• Externally, we can find the integrated circuits in many different packages (see figure)
that have been standardized by the electronic industry.

DIP – Dual-In-Line Package

De Personaamigable - Trabajo propio, CC BY-SA 4.0,

https://commons.wikimedia.org/w/index.php?curid=11 Other types of packages.
3039958 More info: https://learn.sparkfun.com/tutorials/integrated-circuits/all
 Physical logic gates. Logic families
• Finally, integrated circuits are classified into families or sets of circuits that have a
common way of operating and power supplies.
• In the case of logic gates, there are multiple families, both bipolar and MOS. One of the
classic families (which was enormously important in the 1960s and 1970s) and which are
very useful didactically is the TTL family of the 74 series (also called 74x to include its
variants: 74, 74S , 74LS, 74AS, etc.).
• In the figure you can see a photo of an integrated 74LS86 that contains four XOR gates
(SSI scale) inside. As can be seen in the image to the right, there are several integrated
circuits that physically implement different logic gates in different configurations, in this
case depending on the number of inputs.
 Logic families
Logic family – a set of circuits with a common
operation and power supply characteristics.

Classical Texas Instruments – TTL families.

Tables from: List of 7400-series integrated circuits. (2023, January 20).

In Wikipedia. https://en.wikipedia.org/wiki/List_of_7400-series_integrated_circuits
 Physical logic gates. Logic families
• The electrical parameters of the logic gates can be divided into two groups: the strictly
electrical ones (currents, voltages, powers) and those related to their operating speed.
• In order to know these parameters, each manufacturer characterizes the circuits that it
produces and publishes circuits data in the so-called datasheets.
• Next we are going to proceed to carry out an activity in which we will familiarize ourselves
with a data sheet and learn the fundamental electrical parameters of a logic gate. We
must emphasize that this type of parameters are also common to more complex digital
circuits.

ALLDATSHEET.COM. Electronic Components Datasheet Search.

<https://pdf1.alldatasheet.com/datasheet-pdf/view/46213/SLS/74LS86.html>
 Task 1. Basic Parameters of Logic Circuits
1.- From the datasheet of the integrated circuit (IC) DM74LS00, IC
containing four NAND gates:

a. Determine logic levels at the input and outputs of the gate

b. Determine noise margins
c. How many inputs or gates can be connected to an output of this gate?
Which state, LOW or HIGH, is limiting its fan-out?
d. Could it be connected to this circuit a load demanding 10 mA at LOW?
e. What does DC supply voltage need this circuit?
f. What is the average power that consumes this circuit?
g. When does this circuit demands the maximum current from the power
supply?
h. Determine the maximum propagation delay. Which case is the worst?
 Logic Levels
1.- DC Supply voltage. All digital circuits have to be connected to a DC
power supply, VCC or VDD. This connection is realized through pins called
VCC or VDD and ground pins, GND or VSS.
 Logic Levels
2.- Logic levels. The range of voltage used to represent “0”s and “1”s are
called logic levels.
Typical logic level values for CMOS and TTL families with a DC supply
voltage of 5 V are shown below:

5,0V 5,0V Logic 1

HIGH Level Logic 1
(HIGH) (HIGH)
3,5V VIH
2,0V VIH
Undefined
Undefined
1,5V VIL
0,8V VIL Logic 0
Logic 0 (LOW) (LOW)
0V 0V
LOW Level
TTL CMOS
 Basic Parameters of Logic Circuits
• There are four specifications for logic levels:
1. VIL(max), maximum low-level input voltage, defines the minimum voltage for a valid
“0” at the input.
2. VIH(min), minimum high-level input voltage, defines the minimum voltage for a valid
“1” at the input.
3. VOH(min), minimum high-level output voltage, defines the minimum voltage for a
valid “1” at the output of a circuit
4. VOL(max), maximum low-level output voltage, defines the maximum voltage that a
valid “0” at the output of circuit.
• The noise margin is a measure of noise immunity (the ability to
tolerate noise) of circuits. Calculation of noise margins:
– High-level noise margin:
VNH  VOH (min)  VIH (min)
– Low-level noise margin:
VNL  VIL (max)  VOL (max)
Noise
VOLmax VILmax

VOHmin VIHmin
 Basic Parameters of Logic Circuits
4.- Input and output currents
IIH, high-level input current – defines the current flowing through an input
at HIGH
IIL, low-level input current – defines the current flowing through an input
at LOW
IOL, low-level output current – defines the current flowing through an
output at LOW
IOH, high-level output current – defines the current flowing through an
output at HIGH

• To exceed the maximum specified current values can cause

the failure or malfunction of the circuit
 Basic Parameters of Logic Circuits
4.- Input and output currents. FAN-OUT

The “fan-out” defines the maximum number of inputs (gates) of

the same family that can be connected to a given output
It depends on current parameters and can be determined using
this formula:

𝐹𝐴𝑁 − 𝑂𝑈𝑇 =𝑚𝑖𝑛𝑖𝑚𝑢𝑚

{| ||
𝐼 𝑂𝐻 ( max ) 𝐼 𝑂𝐿 ( max )
𝐼 𝐼𝐻 ( max )
,
𝐼 𝐼𝐿 ( max ) |}
HIGH LOW
 Basic Parameters of Logic Circuits
4.- Input and output currents. FAN-OUT

The “fan-out” defines the maximum number of inputs (gates) of

the same family that can be connected to a given output
It depends on current parameters and can be determined using
this formula:
𝐹𝐴𝑁 − 𝑂𝑈𝑇 =𝑚𝑖𝑛𝑖𝑚𝑢𝑚 { 𝑛 𝐻 ,𝑛 𝐿 }

HIGH LOW

𝑛𝐻=
|
𝐼 𝑂𝐻 ( max )
𝐼 𝐼𝐻 ( max )| |
𝑛𝐿=
𝐼 𝑂𝐿 ( max )
𝐼 𝐼𝐿 ( max ) |
 Basic Parameters of Logic Circuits.
5.- Power consumption. Power consumption depends on ICC y VCC
(VDD):
ICCH, supply current when all the outputs are HIGH.
ICCL, supply current when all the outputs are LOW.

Average supply current:

ICC(avg)= (ICCH + ICCL)/2

Average power consumption:

PD(avg) = ICC(avg) x VCC
 Propagation delay. Speed
6- Propagation Delay Time tP. It is the time delay between change at the
input and the corresponding change at the output of the circuit. Two
measurements of tP are specified:
– tpHL: time between a specified reference point on the input signal
and a point on the output, when it is changing from HIGH to LOW
– tpLH: time between a specified reference point on the input signal
and a point on the output, when it is changing from LOW to HIGH
 Basic memories.
Flip-flops and latches
 SEQUENTIAL AND COMBINATIONAL LOGIC
CIRCUITS. CONCEPT.
• In a combinational circuit, the outputs is only a function of the
combinations of input levels. It always produces the same output for the
same combination of inputs values.
• Gates are combinational circuits.
z (t  1)  f ( x(t )) where : z - circuit output and x - circuit inputs

• In a sequential circuit, the outputs is a function of the combination of input

variables in the current instant of time and also of the history or sequence
that they had before.
• A sequential circuit needs to memorize the effect of previous input values
into internal states to define its behavior in the next instant of time.

z (t  1)  f ( x(t ), y (t ))
where :
z - circuit output
x - circuit inputs
y - circuit states
 Flip-flops and Latches. Concepts
• Flip-flop and latches are the simplest sequential circuits. They are
just devices able to memorize a bit
• Flip-flops are synchronized by a special signal called clock.
• Latches don’t use clock, they are asynchronous or use an enable
signal.
• There are four type of flip-flops and latches:
– SR latch and flip-flop
– JK flip-flop
– T flip-flop
– D latch and flip-flop
S-R Latches
 S-R Latch.
• This latch has two inputs called S(Set) and R(Reset) and two outputs (Q
and not Q(Q). S and R can be considered as commands:
– S: (SET) Set Q to “1” and Q to “0”
– R: (RESET) Set Q to “0” and Q to “1”

Symbol Truth Table

S Q

R Q

Implementation
Forbidden
 S-R Latch. Active Low Inputs
• The inputs S and R can be active low. Commands are effective
when they are “0”
R S Qt 1 Qt 1
1 1 Qt Qt
S S Q 1 0 1 0
0 1 0 1
R R Q 0 0 X X

Forbidden
 S-R Latch. Exercise 1
• Exercise 1: Determine the value of the outputs of a S-R latch with
active high inputs S and R, to which the following waveforms are
applied:

t
R
t

Q
t
 BIESTABLES. Set-Reset (SR). Ejercicio
• Exercise 2: Determine the value of the outputs of a S-R latch with
active low inputs S and R, to which the following waveforms are
applied:

t
R

t
Q

t
S-R flip-flops
 The Edge-Triggered S-R flip-flop
Edge-triggered flip-flop operates synchronously, only in the instant that the
clock signal transits from “1” to “0” or vice versa.

Symbols and truth-table of the edge-triggered S-R flip-flops are:

The Edge-Triggered S-R flip-flop. Waveforms

Waveforms of a edge-triggered S-R flip-flop

The forbidden combination is no problem in this time

instant
 The Edge-Triggered S-R flip-flop. Exercise
• Exercise 3: Determine the output waveforms of the flip-flop, if to
its inputs the following waveforms are applied. Assume that Q is
initially “0”.
SET
S Q
CLK
t CLK
S
t R CLR Q
R

t
Q

t
 The Edge-Triggered S-R flip-flop. Exercise
• Exercise 4: Determine the output waveforms of the flip-flop, if to
its inputs the following waveforms are applied. Assume that Q is
initially “0”.
SET
S Q
CLK
t CLK
S
t R CLR Q
R

t
Q

t
J-K and T flip-flops
 The Edge-Triggered JK flip-flop.
These flip-flops behave very similar to S-R. The only difference is that
when boths inputs are “1” it toggles the outputs. If the output was “0” it
becomes “1” and viceversa.
The symbol and truth-table of the (positive) edge-triggered flip-flop are:

J=SET
K=RESET
 The Edge-Triggered JK flip-flop.
Ejercicio 5: Determine the output waveforms of the flip-flop, if to its inputs the
following waveforms are applied. Assume that Q is initially “0”.

t
Q

t
 The Edge-Triggered T flip-flop
If the input T=0 then outputs do not change, if T=1 outputs toggle.

T CLK Q(t+1)
T
0 ↑ Q(t) No change

1 ↑ Q(t) Toggle

Converting a JK flip-flop into a type T flip-flop:

SET
T J Q
CLK

K CLR Q
D flip-flops and latches
 D flip-flops and latches
D latch is level synchronized by input EN (enable).

D Q
E Q(t+1)
0 Q(t) No change
E Q
1 D Transparent

Positive edge-triggered flip-flop:

D Q
D CLK Q(t+1)
0 0 Each positive
CLK Q edge samples
1 1 the value of the
D input.
Flip-flops asynchronous and
synchronous signals
 Aysnchronous and synchronous signals
Flip-flops signals can be classified as synchronous, those which are
synchronized by the clock signal and therefore its operation depends on the
clock.

And, asynchronous, those which are clock-independent. Asynchronous

signals have higher priority than synchronous signal. When they are active
the clock and asynchronous signals are ignored.
 Aysnchronous and synchronous signals
The waveforms shown below correspond to the signals applied to a JK flip-
flop with two asynchronous signals PR (preset) and CLR (clear) active at
‘0’, which is connected as shown below.

Please, draw the waveforms that should correspond to the output Qout.
Timing of the flip-flops and latches
 Flip-flop and latches timing
To avoid malfunctioning, flip-flops and latches have special timing requirements:
1) Clock, SET and RESET pulses should meet or exceed the minimum width
2) Synchronous signals have to keep a set-up and hold time with respect to clock
signals
3) Clock signals can not exceed a maximum frequency

Example: The propagation delays and minimum widths for asynchronous inputs

Metastabilty!
 Flip-flop and latches timing
Set-up time. Synchronous inputs should be stable before the clock active edge
Hold time. Synchronous inputs should be stable after the clock active edge
Propagation delay from clock activation

Example: Waveforms for a positive-edge triggered D-type flip-flop

Metastabilty!
 Flip-flop and latches timing
Set-up time. Synchronous inputs should be stable before the clock active edge
Hold time. Synchronous inputs should be stable after the clock active edge
Propagation delay from clock activation

Example: Waveforms for a positive-edge triggered D-type flip-flop

Metastabilty!

An unstable point
of equilibrium
 Flip-flop and latches timing
Clock signal parameters:
tw(H) – width of the pulse at HIGH
tw(L) – width of the pulse at LOW
T – clock period
fmax – maximum frequency
Flip-flop and latches timing
 Vocabulary. Spanish-English
• Flip-flop. Biestables
• Latches. Cerrojos
• Gates. Puertas
• Edge. Flanco
• Triggered. Disparado o Activado
Where are we?
 Levels of Abstraction of Computer Systems.
Programming in
C, C++, Java, Basic,
Pascal…
(high level)

Assembler or
Machine language
(low level)

Interpret instructions

Digital Electronics

ALU, FSM, RG

FPGA are here

 Abstraction in Computers
• A computer is a very complex system; with billions of
elementary electronic components. So, how to obtain a clear
description, analysis and design? How to cope with complexity?
• Computers as many complex systems are hierarchical and can
be analyzed using abstraction

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