Computer Organization and Architectures
CoSc2021
Chapter Two:- Data representation
Required Reading
Stallings Chapter 9
Sivarama Dandamudi, Sixth Edition, Chapter 2
February 15, 2023
CoSc2021- Computer Organization and
Architectures
Arithmetic & Logic Unit
The ALU is the part of the computer that actually performs
arithmetic and logical operations on data.
All of the other elements of the computer system—control
unit, registers, memory, I/O—are there mainly to bring data
into the ALU for it to process and then to take the results
back out.
Handles integers
May handle floating point (real) numbers
May be separate FPU (maths co-processor)
May be on chip separate FPU (486DX +)
February 15, 2023 2
CoSc2021- Computer Organization
and Architectures
ALU Inputs and Outputs
The below figure indicates , how the ALU is interconnected with the rest of the
processor.
Data are presented to the ALU in registers, and the results of an operation are stored
in registers.
The ALU may also set flags as the result of an operation. For example, an overflow
flag is set to 1 if the result of a computation exceeds the length of the register into
which it is to be stored. The flag values are also stored in registers within the
processor.
The control unit provides signals that control the operation of the ALU and the
movement of the data into and out of the ALU.
February 15, 2023 3
CoSc2021- Computer Organization
and Architectures
Why Don’t Computers Use Base 10?
Base 10 Number Representation
That’s why fingers are known as “digits”
Natural representation for financial transactions
Even carries through in scientific notation
o 1.5213 X 104
Implementing Electronically
Hard to store
o ENIAC (First electronic computer) used 10 vacuum tubes /
digit
Hard to transmit
o Need high precision to encode 10 signal levels on single wire
Messy to implement digital logic functions
o Addition, multiplication, etc.
February 15, 2023 4
CoSc2021- Computer Organization
and Architectures
Binary Representations
Information is represented with 0 or 1 which is called bit (binary digit): It
represents a logical truth.
Base 2 Number Representation
Represent 1521310 as 111011011011012
Represent 1.2010 as 1.0011001100110011[0011]…2
Represent 1.5213 X 104 as 1.11011011011012 X 213
Electronic Implementation
Easy to store with bitable elements
Reliably transmitted on noisy and inaccurate wires
Straightforward implementation of arithmetic and logic functions
0 1 0
3.3V
2.8V
0.5V
0.0V
February 15, 2023 5
Integer Representation
Computer arithmetic is commonly performed on two very different types of
numbers:
integer Representation
floating point Representation
Integer Representation:
Only have 0 & 1 to represent everything
Positive numbers stored in binary
e.g. 41=00101001
No minus sign
No period or radix point
It can be represented in
Sign-Magnitude
Two’s compliment
February 15, 2023 6
CoSc2021- Computer Organization
and Architectures
Sign-Magnitude
Leftmost bit is sign bit: 0 for positive, 1 for negative
Remaining bits are magnitude
Example:
+18 = 00010010
-18 = 10010010
Problems
Need to consider both sign and magnitude in arithmetic. Addition
and subtraction must consider both the signs and relative
magnitudes -- more complex
Two representations of zero (+0 and -0) , Testing for zero must
consider two possible zero representations
+ 010 = 00000000
-010 = 10000000 (sign magnitude)
February 15, 2023 7
CoSc2021- Computer Organization
and Architectures
Two’s Compliment
Leftmost bit still indicates sign
Positive numbers exactly same as sign-magnitude
Zero is only all zeroes (positive)
Negative numbers found by taking 2’s complement
Take complement of positive version
Add 1 to Least Significant Bit (LSB)
Example:
+3 = 00000011
+2 = 00000010
+1 = 00000001
+0 = 00000000
-1 = 11111111
-2 = 11111110
-3February
= 11111101
15, 2023 8
CoSc2021- Computer Organization
and Architectures
Benefits
One representation of zero
Arithmetic works easily
Negating is fairly easy
3 = 00000011
Boolean complement gives 11111100
Add 1 to LSB 11111101
February 15, 2023 9
CoSc2021- Computer Organization
and Architectures
Geometric Depiction of Two’s Complement Integers
February 15, 2023 10
CoSc2021- Computer Organization and
Architectures
Negation Special
Case 1
0 = 00000000 ->Bitwise not 11111111 ->then Add 1 to LSB +1
Result 1 00000000
Overflow is ignored, so: - 0 = 0
Case 2:
-128 = 10000000 -> bitwise not 01111111 -> then Add 1 to LSB +1
Result 10000000
So: -(-128) = -128 X
Monitor MSB (sign bit)
It should change during negation
February 15, 2023 11
CoSc2021- Computer Organization
and Architectures
Range of Numbers
8 bit 2s compliment
+127 = 01111111 = 27 -1
-128 = 10000000 = -27
16 bit 2s compliment
+32767 = 011111111 11111111 = 215 - 1
-32768 = 100000000 00000000 = -215
Conversion Between Lengths
Positive number pack with leading zeros
+18 = 00010010
+18 = 00000000 00010010
Negative numbers pack with leading ones
-18 = 10010010
-18 = 11111111 10010010
i.e. pack with MSB (sign bit)
February 15, 2023 12
CoSc2021- Computer Organization
and Architectures
Addition and Subtraction
Normal binary addition
Monitor sign bit for overflow
Take twos compliment of substahend and add to minuend
i.e. a - b = a + (-b)
So we only need addition and complement circuits
2’s complement examples (with 8 bit numbers)
Getting -55 -> Start with +55: 0110111 -> Complement that: 1001000
-> Add 1: +0000001 -> Total is -55: 1001001
Negating -55 -> Complement -55: 0110110 -> Add 1: +0000001
-> Total is 55 = 0110111
Adding -55 + 58
Start with -55: 1001001 -> Add 58: +0111010 ->Result is 3: 0000011
Overflow into and out-of sign bit is ignored
Overflow Rule - if two numbers are added, and they are both positive or both
negative, then overflow occurs if and only if the result has the opposite sign
February 15, 2023 13
CoSc2021- Computer Organization
and Architectures
Hardware for Addition and Subtraction
It only shows the data paths.
Control signals are needed to control whether or not the
complementer is used, depending on whether the operation
is addition or subtraction
The result may be stored in one of these registers or in a
third.
The overflow indication is stored in a 1-bit overflow flag (
overflow; ).
For subtraction, the subtrahend (
B register) is passed through a twos complementer so that
its twos complement is presented to the adder.
binary adder is presented two numbers for addition and
produces a sum and an overflow indication.
The binary adder treats the two numbers as unsigned
integers.
February 15, 2023 14
CoSc2021- Computer Organization
and Architectures
Multiplication
Compared with addition and subtraction, multiplication is a complex
operation, whether performed in hardware or software.
Work out partial product for each digit
Take care with place value (column)
Add partial products
Multiplication Example:
1011 Multiplicand (11 decimal)
x 1101 Multiplier (13 decimal)
1011 Partial products
0000 Note: if multiplier bit is 1 copy
1011 multiplicand (place value)
1011 otherwise zero
10001111 Product (143 dec)
Note: need double length result
February 15, 2023 15
CoSc2021- Computer Organization
and Architectures
Unsigned Binary Multiplication
Compared with the pencil-and-paper approach, there are several things we can do to make
computerized multiplication more efficient.
First, we can perform a running addition on the partial products rather than waiting until
the end. This eliminates the need for storage of all the partial products; fewer registers are
needed.
Second, we can save some time on the generation of partial products. For each 1 on the
multiplier, an add and a shift operation are required; but for each 0, only a shift is required.
February 15, 2023 16
CoSc2021- Computer Organization
and Architectures
Unsigned Binary Multiplication(cont…)
The multiplier and Multiplicand are loaded into two registers (Q and
M respectively).
A third register, the A register, is also needed and is initially set to 0.
There is also a 1-bit C register, initialized to 0, which holds a potential
carry bit resulting from addition.
The operation of the multiplier is as follows.
Control logic reads the bits of the multiplier one at a time.
If Q0 is 1, then the multiplicand is added to the A register and the
result is stored in the A register, with the C bit used for overflow. Then
all of the bits of the C, A, and Q registers are shifted to the right one
bit, so that the C bit goes into A n-1, A0 goes into Q n-1 and Q0 is lost.
If Q0 is 0, then no addition is performed, just the shift. This process is
repeated for each bit of the original multiplier.
The resulting bit product is contained in the A and Q registers.
February 15, 2023 17
CoSc2021- Computer Organization
and Architectures
Execution of Example
The Execution of Multiplicand (11) – 1011 and Multiplier (13) -
_1101 step by step: the result is become (140) - 10001111
February 15, 2023 18
CoSc2021- Computer Organization
and Architectures
Flowchart for Unsigned Binary Multiplication
February 15, 2023 19
CoSc2021- Computer Organization
and Architectures
Multiplying Negative Numbers
This does not work!
Solution 1
Convert to positive if required
Multiply as above
If signs were different, negate answer
Solution 2
Booth’s algorithm: can be described as follows
control logic scans the bits of the multiplier one at a time.
Now, as each bit is examined, the bit to its right is also examined.
If the two bits are the same (1–1 or 0–0), then all of the bits of the A,
Q and Q-1 registers are shifted to the right 1 bit.
February 15, 2023 20
CoSc2021- Computer Organization
and Architectures
Cont’d…
If the two bits differ, then the multiplicand is added to
or subtracted from the A register, depending on whether
the two bits are 0–1 or 1–0.
Following the addition or subtraction, the right shift
occurs. In either case, the right shift is such that the
leftmost bit of A, namely An-1 not only is shifted into An-
2 , but also remains in An-1 . This is required to preserve
the sign of the number in A and Q. It is known as an
arithmetic shift, because it preserves the sign bit.
February 15, 2023 21
CoSc2021- Computer Organization
and Architectures
Booth’s Algorithm
February 15, 2023 22
CoSc2021- Computer Organization
and Architectures
Example of Booth’s Algorithm
The multiplier and multiplicand are placed in the Q and M registers, respectively.
There is also a 1-bit register placed logically to the right of the least significant bit
(Q0) of the Q register and designated Q-1 ;
The results of the multiplication will appear in the A and Q registers.
A and Q-1 are initialized to 0.
Shows the sequence of events in Booth’s algorithm for the multiplication of 7 by 3.
February 15, 2023 23
CoSc2021- Computer Organization
and Architectures
Division
More complex than multiplication
Negative numbers are really bad!
Based on long division
February 15, 2023 24
CoSc2021- Computer Organization
and Architectures
Division of Unsigned Binary Integers
00001101 Quotient
Divisor 1011 10010011 Dividend
1011
Partial 001110
1011
Remainders
001111
1011
Remainder
100
February 15, 2023 25
CoSc2021- Computer Organization
and Architectures
Flowchart for Unsigned Binary Division
February 15, 2023 26
CoSc2021- Computer Organization
and Architectures
Real Numbers
Numbers with fractions
Could be done in pure binary
1001.1010 = 23 + 20 +2-1 + 2-3 =9.625
Where is the binary point?
Fixed?
Very limited
Moving?
How do you show where it is?
February 15, 2023 27
CoSc2021- Computer Organization
and Architectures
Floating Point
+/- .significand x 2exponent
Misnomer
Point is actually fixed between sign bit and body of
mantissa
Exponent indicates place value (point position)
February 15, 2023 28
CoSc2021- Computer Organization
and Architectures
Floating Point Examples
February 15, 2023 29
CoSc2021- Computer Organization
and Architectures
Signs for Floating Point
Mantissa is stored in 2s compliment
Exponent is in excess or biased notation
e.g. Excess (bias) 128 means
8 bit exponent field
Pure value range 0-255
Subtract 128 to get correct value
Range -128 to +127
February 15, 2023 30
CoSc2021- Computer Organization
and Architectures
Normalization
FP numbers are usually normalized
i.e. exponent is adjusted so that leading bit (MSB) of
mantissa is 1
Since it is always 1 there is no need to store it
(c.f. Scientific notation where numbers are normalized
to give a single digit before the decimal point
e.g. 3.123 x 103)
February 15, 2023 31
CoSc2021- Computer Organization
and Architectures
FP Ranges
For a 32 bit number
8 bit exponent
+/- 2256 1.5 x 1077
Accuracy
The effect of changing lsb of mantissa
23 bit mantissa 2-23 1.2 x 10-7
About 6 decimal places
February 15, 2023 32
CoSc2021- Computer Organization
and Architectures
Expressible Numbers
February 15, 2023 33
CoSc2021- Computer Organization
and Architectures
Reading Assignment
Real Numbers representation
Floating Point(FP)
IEEE 754 on IEEE Web site
FP Arithmetic x/
February 15, 2023 34
CoSc2021- Computer Organization
and Architectures
