Unit III

Memory Organization
 Contents
• Basic concept and hierarchy
• semiconductor RAM memories and types,
ROM memories and types.
• Cache memories: concept and design issues
( performance, address mapping and
replacement)
• Virtual memory: concept implementation
 Memory
• The memory unit is an essential component in any digital computer since
it is needed for storing programs and data.
• Not all accumulated information is needed by the processor at the same
time.
• So it is more economical to use low cost storage devices as a backup for
storing the information which is not currently used by the CPU.
• The execution speed of programs is highly dependant on the speed with
which instruction and data can be transferred between the processor and
memory.
• There are 3 basic parameters of memory:--
• Capacity
• Speed
• Cost per bit
 Capacity
• Memory can be viewed as a storage unit
containing m number of locations (addresses),
each of which stores n number of bits..
• Each word is addressed uniquely by log2m
number of bits.
• The total capacity of a memory is expressed as
mXn bit or m word memory.
• Ex. A 16 bit computer that generates 16-bit
address is capable of addressing up to 216=64K
memory locations.
 MEMORY
The data and Instructions that are entered into the computer by the
input devices needs to be stored in the computer’s memory before
the actual processing.

And the results after processing and the intermediate results also
need to be stored in the computer’s memory.

It basically provides the space for storing of the data and instructions
before processing, during processing and after processing.

So, Memory is an essential component of a digital computer. It is

required for storage and subsequent retrieval of the instructions and
data.
 Speed
• A useful parameter of the memory is its speed of operation
which is the time that elapses between the initiation of an
operation and the completion of that operation.
• This is measured in terms of two parameter: access time
tA
cycle time tC
Access time is the time taken by the memory to complete a
read operation.
Cycle time is the min time delay required between the
initiations of two successive memory operation.
 Memory Hierarchy
• The total memory capacity of a computer can
be visualized as being a hierarchy of
components.
• The memory hierarchy system consists of all
storage devices employed in a computer
system.
 Memory Hierarchy

CPU
Register

Cache

Access time
Cost per bit

capacity
Primary or Main Memory

(RAM /ROM )
Flash Memory
Secondary
Hard disk
CD and DVD or
Magnetic tape Auxiliary
memory
 Types of Memory

Memory

Register Cache Primary Secondary

Magnetic tape
RAM ROM

PROM Magnetic Disk

SRAM
EPROM
CD ROM
DRAM
EEPROM
 PRIMARY MEMORY
Primary memory is mainly used by CPU, so it is termed as primary memory. It is also called main
memory.

Primary memory is a type of memory that is available in the form of silicon chips. These chips are
created by IC by using very large scale integration techniques.

It store the currently executing program.

It stores data and instructions that are necessary to perform an operation. It holds both the
intermediate and final results of the computer during processing as the program proceeds.

Primary memory is typically high speed memory and very costly.

There are two types of primary Memory:

(a) Random Access Memory (RAM)
(b) Read Only Memory (ROM)
 RAM (Random Access Memory)
In RAM, it is possible both to read data from the memory and to write data into the memory.

In random access memory, any memory location can be accessed in a random way without
going through any other location. The access time is same for each and every memory
location.

RAM is also called read-write memory. RAM is used in computers for temporary storage of
data.

This is volatile in nature, it means contents stored in it are not permanent.

The major drawback of RAM is that it is volatile i.e. it stores information as long as the power
is supplied to it. Its contents are lost when power supply is switched off or interrupted.

Different types of RAM:

Static RAM
Dynamic RAM
 RAM (Random Access Memory)
• The most familiar form of system memory, Random
Access Memory (RAM) derives its name from the fact
that any of its memory cells can be accessed directly if
you are aware of the row and column that intersect at
that cell.
• The columns are referred to as bit lines while the rows
are referred to as word lines.
• The intersection of a word line and bit line is the
address of the memory cell
onto a silicon wafer.
 Basic RAM Architecture
Word Lines

Bit Cell

Bit Lines
High
Sense Amplifier
Low

Address Data
 Static RAM
• SRAM is made from an array of filp-flops , where each flip flop maintains
a single bit of data within a single memory location
• SRAM uses multiple transistors for each memory cell.

• It does not have a capacitor in each cell.

• Each bit of memory is held by a flip-flop memory which takes four to six
transistors besides some wiring.

• SRAM is not required to be refreshed which makes it significantly fast.

• The word “Static” indicates that the memory retains its content as long as
power remains applied.

• As compared to DRAM, SRAM has more parts and therefore it consumes

a lot more space on a chip. With less memory available per chip, the
SRAM becomes costlier.
 Static RAM (SRAM)

Word
Read: Drive word line, sense
Line value on bit lines

Write: Drive word line, drive

new value (strongly) on bit lines

Bit
!Bit
 Dynamic RAM
Dynamic random-access memory (DRAM) is a type of random access memory that
stores each bit of data in a separate capacitor within an integrated circuit. The
capacitor can be either charged or discharged; these two states are taken to represent
the two values of a bit, conventionally called 0 and 1.

Since capacitors leak charge, the information eventually fades unless the capacitor
charge is refreshed periodically. Because of this refresh requirement

Due to the way in which the cells are constructed, the reading action itself refreshes
the contents of the memory. If this is not done regularly, then the DRAM will lose its
contents, even if it continues to have power supplied to it. This refreshing action is why
the memory is called dynamic.

The advantage of DRAM is its structural simplicity: only one transistor and a capacitor

are required per bit, compared to four or six transistors in SRAM. This allows DRAM to
reach very high densities. 

DRAMs are smaller and less expensive than SRAMs  because SRAMs are made from
four to six transistors (or more) per bit, DRAMs use only one, plus a capacitor. 
 Refreshing Circuit

• Dynamic Random Access Memory needs to be refreshed consistently so

its required a refreshing circuit and contains memory cells with a paired
transistor. In order to activate the transistor at each bit in the column,
• DRAM sends a charge through the appropriate column (CAS).
The level of charge is determined by the sense-amplifier while reading. If
the level of charge exceeds fifty percent, it is read as a 1 whereas if the
charge is below fifty percent it is read as a 0. For dynamic memory to
work, Either the CPU or the memory controller recharges all the capacitors
before they are discharged to zero.
• To ensure this the memory is read and written back which if referred to as
refresh operation. DRAM is required to be refreshed dynamically all the
time otherwise it will lose the information. This refreshing operation
consumes a lot of time and causes the memory to slow down.
• Memory cells have a support infrastructure of other specialized circuits so
that information can be put in and retrieved from them. These circuits
identify each and column, keep track of the refresh sequence, read and
restore the signal from a cell and tell a cell whether it should take a charge
or not)
 DRAM must be recharged constantly

Like Capacitor
A Refereshing Circuit is required to recharge or reload the data.
 Dynamic RAM (DRAM)
Word Line

Read: Drive word line, sense value

on bit line (destroys saved value)

Write: Drive word line, drive new

value on bit line.

Bit Line
 Random-Access Memory (RAM)
• Static RAM (SRAM)
– Each cell stores bit with a six-transistor circuit.
– Retains value indefinitely, as long as it is kept powered.
– Relatively insensitive to disturbances such as electrical noise.
– Faster (8-16 times faster) and more expensive (8-16 times more expensice as
well) than DRAM.

• Dynamic RAM (DRAM)

– Each cell stores bit with a capacitor and transistor.
– Value must be refreshed every 10-100 ms.
– Sensitive to disturbances.
– Slower and cheaper than SRAM.
 ROM
• Read Only Memory (ROM) is an integrated circuit programmed with
data that holds instructions for starting up the computer. Data stored in
ROM is non volatile and is not lost when powered off. These data
cannot be changed or a special operation is needed to be performed to
change it.

ROM chips also comprise of columns and rows but it is different from
RAM in terms of intersection of these. These chips use diodes instead
of transistors to connect the lines if the value is 1 whereas if the value is
0 the lines are not connected.
A ROM chip cannot be reprogrammed or rewritten therefore when the
chip is created it requires the programming of perfect and complete
information. ROM chips are cost effective and use very little power.
 ROM (Read Only Memory)
ROM is a memory that performs only read operation.

A ROM is a non-volatile memory. It stores

information permanently. Its contents are not lost
when its power supply is switched off.

 It is not accessible to user, and hence user cannot

write anything into it. ROM is used to store
permanent (fixed) programs.
 Bootstrap loader
• The bootstrap loader is a program whose function is
to start the computer software operating when
power is turned on.
• When power is turned on the hardware of computer
sets the program counter to the first address of
bootstrap loader.
• The bootstrap program loads a portion of the
operating system from disk to main memory and
control is then transferred to the operating system,
which prepares the computer for general use.
 PROM
Programmable read only memory (PROM) is a type of ROM. These chips are non
volatile and cannot be used to store something else once it has been used. Blank
PROM chips can be coded with the help of a tool known as a programmer.

PROM chips  have a grid of columns and rows just as ordinary ROMs do. The
difference is that every intersection of a column and row in a PROM chip has a
fuse connecting them.

A charge sent through a column will pass through the fuse in a cell to a
grounded row indicating a value of 1. Since all the cells have a fuse, the initial
(blank) state of a PROM chip is all 1s.

To change the value of a cell to 0, you use a programmer to send a specific

amount of current to the cell. The higher voltage breaks the connection between
the column and row by burning out the fuse. This process is known as burning
the PROM
 EPROM
• Erasable Programmable Read Only Memory can be
erased with the help of ultraviolet light and rewritten
many times. These chips are configured by the EPROM
programmer, providing the voltage at the specified
levels
•  This procedure can be carried out many times;
however, the constant erasing and rewriting will
eventually render the chip useless.
• EPROM eraser is not selective, it will erase the entire
EPROM. The EPROM must be removed from the
device it is in and placed under the UV light of the
EPROM eraser for several minutes.
 EEPROM
• Electrically Erasable Programmable Read Only Memory chips are not
required to removed to be erased or rewritten. These chips do not require
to be erased altogether and specific portion of it can be easily altered.

• Additional dedicated equipment are also not required to change the

content the EEPROM chips . i.e. there is no need to physically removed
from the system.

• These chips are erased and rewritten with the help of electric charge.

In EEPROMs:
• The chip does not have to removed to be rewritten.
• The entire chip does not have to be completely erased to change a specific
portion of it.
• Changing the contents does not require additional dedicated equipment.
RAM and ROM chips
 RAM
• The block diagram of a RAM chip has been shown.
• The capacity of memory is 128 words of 8 bits
each.
• This require a 7 bit address and an 8 bit
bidirectional data bus.
• The read write inputs specify the memory
operation and the two chip select CS control
inputs are for enabling the chip only when it is
selected by the microprocessor.
 RAM
• The unit is in operation only when CS1=1 and CS2 =0.
• If the chip select inputs are not enabled or if they are enabled
but the read write inputs are not enabled the memory is
inhibited and its data bus is in high impedance state.
• When CS1=1 and CS2=0 the memory can be read or write
mode.
• When WR input is enabled the memory stores a byte from
the data bus into a location specified by the address input line
• When RD input is enabled the content of selected bytes are
placed into the bus.
 ROM Chip
ROM can only read, the data bus can only be in an output mode.

For the same size chip, it is possible to have more bits of ROM
than of RAM, because the internal binary cells in ROM occupy
less space than in RAM.

For this reason, the diagram specifies a 512 byte ROM, while the
RAM has only 128 bytes.

The nine address lines in the ROM chip specify any one of the
512 bytes stored in it.
ROM chip
 Example 1
• Assume that a computer system needs
512 bytes of RAM and 512 bytes of ROM.

And available chip

• RAM chip is of 128 X 8
• And ROM chip is of 512 X 8
 Ex 1Calculation of no. of chips.
•
Size=512 bytes

= 512 X 8

• Size of RAM chip=128 X 8

• No. of chips needed= 512 X 8 = 22=4 RAM chip

• 128 X 8
 Example 1

128 X 8 RAM 1

128 X 8 RAM 2

512 X 8 RAM
128 X 8 RAM 3

128 X 8 RAM 4
 Memory connection to CPU
• RAM and ROM chips are connected to a CPU through the data and address
buses.

• The low order lines in the address bus select the byte within the chips and other
lines select the particular chip.

• In the previous example each RAM chip receives 7 low order bits of address bus
to select one of 128 possible bytes.

• The particular RAM chip selected is determined from lines 8 and 9. This is done
through a 2 X 4 decoder. Whose outputs are connected to the CS1 input in each
RAM chip.

• The selection between the RAM and ROM is achieved by line 10.
 Memory address map
• The designer of a system must calculate the amount
of memory required for the particular application
and assign it to either RAM or ROM.

• The addressing of the memory can be established

by means of a table that specifies the memory
address assigned to each chip.

• The table called a memory address map is a

pictorial representation of assigned address space
for each chip in the system.
 Memory Address Map
A memory address map, is a pictorial representation of assigned address
space for each chip in the system.

Let us assume that a computer system needs 512 bytes of RAM and 512
bytes of ROM

The RAM chips have 128 bytes and need seven address lines. The ROM
chip has 512 bytes and needs 9 address lines.

The X’s are always assigned to the low order bus lines: lines 1 through 7
for the RAM and lines 1 through 9 for the ROM. It is now necessary to
distinguish between 4 RAM chips by assigning to each a different address.
• The hexadecimal address assigns a range of
hexadecimal equivalent address for each chip

• Line 8 and 9 represent four distinct binary

combination to specify which RAM we chose

• When line 10 is 0, CPU selects a RAM. And

when it’s 1, it selects the ROM
 Hexadecimal address range
16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
RAM 1 0 0 0 0 0 0 0 0 0 X X X X X X X
Lower 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0
upper 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1
0 0 7 F

RAM1 0000-007F
 Questions?
• How many 128 X 8 RAM chips are needed to
provide a memory capacity of 2048 bytes?
• How many lines of the address bus must be
used to access 2048 bytes of memory? How
many of these lines will be common to all
chips?
• How many lines must be decoded for chip
select? Specify the size of the decoder.
 Solution
• No. of chips= 2048 X 8 = 211/ 27=24=16 RAM chips
128 X 8

• As there are 2048 addresses

• So log2(2048)= 211
• So 11 bits for addressing
• Common lines will be 7 as RAM is of 128 bytes
• 4 lines for chip select.
• Size of decoder 4 X 16.
 RAM 11

RAM 12

RAM 13

RAM 14

RAM 15
RAM 7

RAM 8
RAM 5

RAM 9
RAM 1

RAM 2

RAM 3

RAM 4

RAM 6

RAM

RAM
10

16
CS1

CS1
CS 1
CS1

CS1

CS1

CS1

CS1

CS1

CS1

CS1

CS1

CS1

CS1

CS1
CS1
16 out put lines each will be
connected to CS 1of RAM chip
0 1 2 3 4 --------------16
Decoder
4 X 16 7 address lines to access 128
words.

11 10 9 8 7654321
 Question?
• A computer uses RAM chip of 1024 X 1 capacity.
• (a) How many chips are needed, and how
should their address lines be connected to
provide a memory capacity of 1024 bytes?
• (b) How many chips are needed to provide a
memory capacity of 16K bytes? Explain in words
how the chips are to be connected to the
address bus?
 Solution 2
• No. of chips= 1024 X 8 = 8 chips
1024 X 1
 Solution 2
8 bit data

1024 X 1 1024 X 1 1024 X 1 1024 X 1 1024 X 1

RAM 1 RAM 2 RAM 3 RAM 4 RAM 8

AD-10 AD-10 AD-10 AD-10 AD-10

CS RD WR CS RD WR CS RD WR CS RD WR CS RD WR

CS RD WR
 Solution 2
• If total memory capacity is 16K bytes then the no. of
chips required will be
• 16 X 1024 X 8 = 16 X 8
• 1024 X 1
• So 16 rows will be there. And in each row there will
be 8 RAM chips of size 1024 x1.
• Total address lines will be 16 K=24 X 210=214
• 4X 16 decoder will be used.
• All the 8 chips of a decoder will be activated at a time.
 Solution 2  16 K bytes
RAM 1 RAM2 RAM3 RAM4 RAM5 RAM6 RAM7 RAM8

RAM 1 RAM2 RAM3 RAM4 RAM5 RAM6 RAM7 RAM8

RAM 1 RAM2 RAM3 RAM4 RAM5 RAM6 RAM7 RAM8

1 RAM 1 RAM2 RAM3 RAM4 RAM5 RAM6 RAM7 RAM8
2 RAM 1 RAM2 RAM3 RAM4 RAM5 RAM6 RAM7 RAM8
3
RAM 1 RAM2 RAM3 RAM4 RAM5 RAM6 RAM7 RAM8
4
RAM 1 RAM2 RAM3 RAM4 RAM5 RAM6 RAM7 RAM8
5
4 X16 6 RAM 1 RAM2 RAM3 RAM4 RAM5 RAM6 RAM7 RAM8

Decoder 7 RAM 1 RAM2 RAM3 RAM4 RAM5 RAM6 RAM7 RAM8

8 RAM 1 RAM2 RAM3 RAM4 RAM5 RAM6 RAM7 RAM8
9 RAM 1 RAM2 RAM3 RAM4 RAM5 RAM6 RAM7 RAM8
10
RAM 1 RAM2 RAM3 RAM4 RAM5 RAM6 RAM7 RAM8
11
RAM 1 RAM2 RAM3 RAM4 RAM5 RAM6 RAM7 RAM8
12
13 RAM 1 RAM2 RAM3 RAM4 RAM5 RAM6 RAM7 RAM8

14 RAM 1 RAM2 RAM3 RAM4 RAM5 RAM6 RAM7 RAM8

15 RAM 1 RAM2 RAM3 RAM4 RAM5 RAM6 RAM7 RAM8
16
 Cache memory
• Principle of Locality:-
Programs access a small proportion of their address
space at any time
Temporal locality
– Items accessed recently are likely to be accessed again soon
– e.g., instructions in a loop, induction variables
Spatial locality
– - Items near those accessed recently are likely to be
accessed soon
– E.g., sequential instruction access, array data
 What is Cache Memory?
• If the active portion of the program and data
are placed in a fast memory, the average
access time can be reduced,
• thus reducing the total execution time of
program.
• Such a fast memory is referred to as a cache
memory.
 Cache Memory
• Cache memory is a small, high-speed RAM buffer
located between the CPU and main memory.

• Cache memory holds a copy of the instructions

(instruction cache) or data (operand or data cache)
currently being used by the CPU.

• The main purpose of a cache is to accelerate your

computer while keeping the price of the computer low.
Placement of Cache in computer
 Cache
• Small amount of fast memory
• Sits between normal main memory and CPU
• May be located on CPU chip or module
 Cache memories

Main
Processor Cache memory

• Processor issues a Read request, a block of words is transferred from the main
memory to the cache, one word at a time.
• Subsequent references to the data in this block of words are found in the cache.
• At any given time, only some blocks in the main memory are held in the cache.
Which blocks in the main memory are in the cache is determined by a “mapping
function”.
• When the cache is full, and a block of words needs to be transferred
from the main memory, some block of words in the cache must be
replaced. This is determined by a “replacement algorithm”.
 The working of cache
• When the cpu needs to access the memory,
the cache is examined. If the word is found in
the cache, it is read from there. If it is not
found in the cache, the main memory is
accessed to read the word. A block of word
containing the one just accessed is then
transferred from main memory to cache..
 Cache hit
• Existence of a cache is transparent to the processor. The processor issues
Read and Write requests in the same manner.

• If the data is in the cache it is called a Read or Write hit.

• Read hit:
 The data is obtained from the cache.

• Write hit:
 Cache has a replica of the contents of the main memory.
 Contents of the cache and the main memory may be updated simultaneously.
This is the write-through protocol.
 Update the contents of the cache, and mark it as updated by setting a bit known
as the dirty bit or modified bit. The contents of the main memory are updated
when this block is replaced. This is write-back or copy-back protocol.
 Cache miss
• If the data is not present in the cache, then a Read miss or Write miss occurs.

• Read miss:
 Block of words containing this requested word is transferred from the memory.
 After the block is transferred, the desired word is forwarded to the processor.
 The desired word may also be forwarded to the processor as soon as it is transferred
without waiting for the entire block to be transferred. This is called load-through or
early-restart.

• Write-miss:
 Write-through protocol is used, then the contents of the main memory are
updated directly.
 If write-back protocol is used, the block containing the
addressed word is first brought into the cache. The desired word
is overwritten with new information.
 Hit Ratio
• The performance of cache memory
• When the CPU refers to memory and finds the word in the cache its is
said to produce a hit.
• If the word is not found in cache it is in main memory and it counts as
miss.
Hit ratio=Total hits/ total CPU references to memory

• EX. In a computer assume

Cache access time= 100ns
Main memory access time =1000ns
Hit ratio=0.9
Then avg. access time= (0.9 x 100 ) + (0.1 X 1100)=200ns
Cache/Main Memory Structure
 Cache operation – overview
• CPU requests contents of memory location
• Check cache for this data
• If present, get from cache (fast)
• If not present, read required block from main
memory to cache
• Then deliver from cache to CPU
• Cache includes tags to identify which block of
main memory is in each cache slot
Cache Read Operation - Flowchart
 Cache Design
• Size
• Mapping Function
• Replacement Algorithm
• Write Policy
• Block Size
• Number of Caches
 Size does matter
• Cost
– More cache is expensive
• Speed
– More cache is faster (up to a point)
– Checking cache for data takes time
Typical Cache Organization
 The working of cache
• When the cpu needs to access the memory, the
cache is examined.
• If the word is found in the cache, it is read from
there. It is called as Cache Hit.
• If it is not found in the cache, the main memory
is accessed to read the word. It is referred as
Cache Miss.
• A block of word containing the one just accessed
is then transferred from main memory to cache..
 Hit Ratio
• The performance of cache memory
• When the CPU refers to memory and finds the word in the cache its is said to
produce a hit.
• If the word is not found in cache it is in main memory and it counts as miss.

Hit ratio= Total hits/ total CPU references to memory

Hit Ratio = Total Number of Hits / (Total Number of Hits + Total Number of Miss)

• EX. In a computer assume

• Cache access time= 100ns
• Main memory access time =1000ns
• Hit ratio=0.9
• Then avg. access time= (0.9 x 100 ) + (0.1 X 1100)=200ns
Replacement Algorithms of Cache Memory
Replacement algorithms are used when there are no available space in a cache in which
to place a data. Four of the most common cache replacement algorithms are described
below:
Least Recently Used (LRU):
The LRU algorithm selects for replacement the item that has been least recently used by the CPU.

First-In-First-Out (FIFO):
The FIFO algorithm selects for replacement the item that has been in the cache from the longest
time.

Least Frequently Used (LRU):

The LRU algorithm selects for replacement the item that has been least frequently used by the CPU.

Random:
The random algorithm selects for replacement the item randomly.
 Writing into Cache
• When the CPU finds a word in cache during a read operation,
main memory is not involved.

But when memory write operations are performed, CPU first

writes into the cache memory. These modifications made by CPU
during a write operations, on the data saved in cache, need to be
written back to main memory or to auxiliary memory.

These two popular cache write policies (schemes) are:

Write-Through
Write-Back
 Write-Through
In a write through cache, the main memory is updated
each time the CPU writes into cache.

The advantage of the write-through cache is that the main

memory always contains the same data as the cache
contains.

This characteristic is desirable in a system which uses direct

memory access scheme of data transfer. The I/O devices
communicating through DMA receive the most recent data.
 Write-Back
• In a write back scheme, only the cache memory is
updated during a write operation.

• The updated locations in the cache memory are

marked by a flag so that later on, when the word is
removed from the cache, it is copied into the main
memory.

• The words are removed from the cache time to time to

make room for a new block of words.
 Cache Mapping Technique
• The transformation of data from main
memory to cache memory is referred to as
mapping process. Three types of mappings
are under consideration:--
• (1) associative mapping
• (2) direct mapping
• (3) Set associative mapping
 Associative Mapping

CPU
Main Memory
32 K X 12 Cache
memory
512 X 12
 Associative mapping
• The associative memory stores the address and data of memory
word.
• Here the address is of 15 bits and data is of 12 bits.
• A cpu address of 15 bit is placed in argument register and the
associative memory is searched for the matching address.
• If the address is found the corresponding 12 bit data is read from
the memory.
• If no match occurs, main memory is accessed for the word.
• The address data pair is than transferred to the associative cache
memory.
• If the cache is full then a pair of address of data is replaced from the
memory.
Fully Associative Cache Organization
 Direct mapping
• Associated memories are expansive compared to RAM
because of the address logic associated with each cell.
• In direct mapping address is divided in two fields (1)
index (2) tag
• The number of bits in the index field is equal to the no.
of address bits required to access the cache memory.
• In general if there are 2K words in cache memory and 2n
words in main memory. The n bit memory address is
divided into two fields
• K bits for index and n-k bits for tag.
Direct mapping
Direct mapping
 Direct Mapping
• Each word in cache consist of the data word and its
associated tag. When a new word is first brought into
the cache the tag bits are stored alongside the data bits.
• The index field is used to access the cache.
• The tag field is compared.
• If the two tag match, there is a hit and desired data is in
cache.
• If there is a miss the required word is read from main
memory, and stored in the cache together with the new
tag replacing the previous value.
 Direct mapping

CPU address= 02777

777 is the index and 02 is
the tag bits.
As the two tag matches
there is a hit

CPU address= 01777

777 index
01 tag
Its a miss.
So a new word together
00 1220 with its tag will be brought
000
into the cache.

777 01 4560
Direct Mapping Cache Organization

Block
• The disadvantage of direct mapping is that the
hit ratio can drop if two or more words whose
address have the same index but different tags
are accessed repeatedly.
• Ex 01000, 02000, 03000
• This possibility is minimized by the fact that
they will be far apart in the address range.
 Direct mapping
• If the cache uses block size of 8 words. Then
the index is divided into two fields.
• (1) block (2) word
• 512/ 8 =64 blocks 6 bits for block
• 9-6=3 bits for word
•
Tag Block Word
6 6 3
 Question
• A digital computer has a memory unit of 64K X
16 and a cache memory of 1K words. The
cache can use direct mapping with a block size
of four words.
• (a) how many bits are there in the tag, index,
block and word fields of the address format?
• (b) how many block can the cache
accommodate?
 Solution
• Cache size 1K= 210
• So 10 bits are required to address the cache
memory. Index=10bits
• Total memory capacity=64K= 216
• Tag=16-10=6bits
• No. of blocks=1024/4=256=28
• 8 bits for block
• 2 bits for words
 Set-Associative mapping
• This organization shows an improvement over
the direct mapping technique.
• Each data word is store two or more words of
memory under the same index addresses.
• Each data word is stored together with its tag.
• The number of tag-data items in one word of
cache is said to form a set.
Set Associative Cache Organization
Set associative mapping
 Set associative mapping
• Here each index address refers to two data words and
their associated tags.
• Each tag require 6 bits and each data word is of 12 bits.
• So the word length is 2(6+12)=36 bits.
• An index address of 9 bits can accommodate 512 words.
• Thus the size of cache memory is 512X36 bits.
• It can store 1024 words of main memory.
• In general a set associative cache of set size k will
accommodate k words of main memory in each word of
cache.
 Set associative mapping
• When the cpu generates a memory request,
the index value of the address is used to
access the cache.
• The tag field of the address is then compared
with both tags in the cache to determine if a
match occurs.
• The comparison logic is done by an associative
search of the tags.
 Questions

• A two way set associative cache memory uses

blocks of four words. The cache can
accommodate a total of 2048 words from
main memory. The main memory size is
128K X 32.
(a) Formulate all the information required to
construct the cache memory.
(b) What is the size of cache memory?
 Solution
• Address generated by CPU= 128 K X 32
• 17 bits for address
• As it is 2-way set associative
• So if it can store 2048 total words then the total addresses will be 1024
• So 10 bits to address the cache. Tag index
• Tag= 17-10=7 7 10
• And the cache will be like
Tag Data Tag data
•
7 32 7 32

Total size of cache will be 1024 X2(7 +32)

 Question
• Consider a cache consisting of 256 blocks of
16 words each for a total of 4096 (4K)words
and assume that the main memory is
addressable by a 16 bit address and it consists
of 4K blocks. How many bits are there in each
of the TAG, BLOCK , and WORD fields for direct
mapping cache.
• Q.1The main memory consists of 16,384 blocks and each block
contains 256 eight bit words. A 4-way set associative cache
memory is used (1Kwords each set).
• How many bits will be needed to address the main memory?
14+8=22
• How many bits will be in TAG, index fields.
• Index=10 tag=12
• Direct mapping 1 k words and similar block size
• Index=10 tag=12
• 1024/256=4 word 8
• 12,2,8
 Magnetic Disks

Disk surface spins at

3600–7200 RPM read/write head

arm
The surface consists
of a set of concentric
magnetized rings called
tracks

The read/write
head floats over
the disk surface
and moves back
Each track is divided and forth on an
into sectors arm from track to
track.
 Disk Operation

• Operation
– Read or write complete sector
• Seek
– Position head over proper track
• Rotational Latency
– Wait until desired sector passes under head
• Read or Write Bits
– Transfer rate depends on # bits per track and
rotational speed
Logical vs. Physical Address Space
• The concept of a logical address space that is
bound to a separate physical address space is
central to proper memory management
– Logical address – generated by the CPU; also referred to
as virtual address
– Physical address – address seen by the memory unit
• Logical and physical addresses are the same in
compile-time and load-time address-binding
schemes; logical (virtual) and physical addresses
differ in execution-time address-binding scheme
 Base and Limit Registers

• A pair of base and limit registers define

the logical address space
Memory-Management Unit (MMU)
• Hardware device that maps virtual to physical
address

• In MMU scheme, the value in the relocation

register is added to every address generated by
a user process at the time it is sent to memory

• The user program deals with logical addresses;

it never sees the real physical addresses
 Logical vs. Physical Addresses
• Compile-Time + Load Time addresses same
• Run time addresses different

Logical Relocation Physical

Address Register Address
CPU 14000 Memory
346 14346
+

MMU

• User goes from 0 to max

• Physical goes from R+0 to R+max
 Relocatable Code Basics
• Allow logical addresses
• Protect other processes

Limit Reg Reloc Reg Memory

yes
CPU < +

no physical
MMU address

error

• Addresses must be contiguous!