Lecture - 07 - Embedded Systems Software Introduction
Lecture - 07 - Embedded Systems Software Introduction
1
Timing Guarantees
Hard real-time systems, often in safety-critical
applications abound
Aeronautics, automotive, train industries, manufacturing
control
polling
interrupt
Timer interfaces
CPU to sensor/
actuator
T1 T1 T3
T3 T1 T2 T3 t
T2 T2
P
t(0)
Properties:
later processes (T2, T3) have unpredictable starting times
no problem with communication between processes or use of
common resources, as there is a static ordering
T1 T3 T2 T2 T2
T1 T4 T2 T1 T1 t
0 2 4T 6 8 10 12 14 16 18 20
1
f P
T1 T3 T2 T1 T4 T1 T2 T 1 T2
t
0 2 4 6 T2 8 10 12 14T1 16 18 20
f P
Swiss Federal Computer Engineering
Institute of Technology 2 - 12 and Networks Laboratory
Generic Time-Triggered Scheduler
In an entirely time-triggered system, the temporal control structure
of all tasks is established a priori by off-line support-tools. This
temporal control structure is encoded in a Task-Descriptor List
(TDL) that contains the cyclic schedule for all activities of the node.
This schedule considers the required precedence and mutual
exclusion relationships among the tasks such that an explicit
coordination of the tasks by the operating system at run time is not
necessary. ..
The dispatcher is activated by the synchronized clock tick. It looks at
the TDL, and then performs the action that has been planned for
this instant [Kopetz].
Extensions:
allow interrupts (shared resources ? WCET ?) → be
careful!!
allow preemptable background processes
Swiss Federal Computer Engineering
Institute of Technology 2 - 15 and Networks Laboratory
Event Triggered Systems
The schedule of processes is determined by the
occurrence of external interrupts:
dynamic and adaptive: there are possible problems with
respect to timing, the use of shared resources and buffer over-
or underflow
guarantees can be given either off-line (if bounds on the
behavior of the environment are known) or during run-time
interrupt interrupt
Timer interfaces
CPU to sensor/
actuator
part 1 part 2
context
global memory
Swiss Federal Computer Engineering
Institute of Technology 2 - 18 and Networks Laboratory
Preemptive ET Scheduling – Stack Policy
Similar to non-preemptive case, but processes can be
preempted by others; this resolves partly the problem of
long tasks.
If the order of preemption is restricted, we can use the usual
stack-based context mechanism of function calls
(process = function).
context main memory
main(){
stack
…
task1(); task 1
…
registers
Context switch: thread 2
current CPU context
goes out ... CPU
Advantages:
predictable, where context switches can occur
less errors with use of shared resources
Problems:
programming errors can keep other threads out, thread never gives
up CPU
real-time behavior at risk if it takes too long before context
switch allowed
firing
timer
CPU