Lecture 18

 Logistics
 HW6 due today
 Midterm 2
 Wednesday Feb 25
 Review session Tuesday Feb 24, 4:30 in this room, EEB 037
 Will cover materials up to today’s lecture

 Last Lecture
 Counter Finite State Machine
 Timing

 Today
 General Finite State Machine (FSM) design

CSE370, Lecture 18 1
One more counter example:
A 5-state counter with D flip flops
 Counter repeats 5 states in sequence
 Sequence is 000, 010, 011, 101, 110, 000

Step 1: State diagram Step 2: State transition table

Assume D flip-flops

Present State Next State

000 110 C B A C+ B+ A+
0 0 0 0 1 0
0 0 1 X X X
010 101 0 1 0 0 1 1
0 1 1 1 0 1
1 0 0 X X X
011 1 0 1 1 1 0
1 1 0 0 0 0
1 1 1 X X X
CSE370, Lecture 18 2
5-state counter (con’t)

Step 3: Encode the next state functions

C+ C B+ C
A+ C

0 0 0 X 1 1 0 X 0 1 0 X
A X 1 X 1 A X 0 X 1 A X 1 X 0

B B B

C+ = A B+ = B' + A'C' A+ = BC'

CSE370, Lecture 18 3
5-state counter (con’t)

Step 4: Implement the design

A D Q C D Q B D Q A

CLK

A' B
C' C'
B'

Recall that a D flip flop also produces Q’ so A’, B’, and C’

would all be available without any extra inverters
CSE370, Lecture 18 4
5-state counter (con’t)

 Is our design robust?

 What if the counter starts in a 111 state?

Does our counter get

stuck in invalid states???

111
001
000 110
100

010 101

011

CSE370, Lecture 18 5
 5-state counter (con’t)

 Back-annotate our design to check it

Fill in state transition table Draw state diagram

Present State Next State 001

C B A C+ B+ A+ 000 110
0 0 0 0 1 0
0 0 1 1 1 0
0 1 0 0 1 1 010 101
0 1 1 1 0 1
1 0 0 0 1 0
1 0 1 1 1 0 011
100
1 1 0 0 0 0
A+ = BC' 1 1 1 1 0 0 111
B+ = B' + A'C'
The proper methodology is to design
C+ = A your counter to be self-starting
CSE370, Lecture 18 6
Self-starting counters

 Invalid states should always transition to valid states

 Assures startup
 Assures bit-error tolerance

 Design your counters to be self-starting

 Draw all states in the state diagram
 Fill in the entire state-transition table
 May limit your ability to exploit don't cares
 Choose startup transitions that minimize the logic

CSE370, Lecture 18 7
Finite state machines: more than counters

 FSM: A system that visits a finite number of logically

distinct states
 Counters are simple FSMs
 Outputs and states are identical
 Visit states in a fixed sequence without inputs

 FSMs are typically more complex than counters

 Outputs can depend on current state and on inputs
 State sequencing depends on current state and on inputs

CSE370, Lecture 18 8
FSM design

 Counter design procedure

1. State diagram
2. State-transition table
3. Next-state logic minimization
4. Implement the design

 FSM design procedure

1. State diagram
2. State-transition table
3. State minimization
4. State encoding
5. Next-state logic minimization
6. Implement the design

CSE370, Lecture 18 9
 Example: A vending machine
 15 cents for a cup of coffee (yeah, it’s subsidized)

 Doesn’t take pennies or quarters

 Doesn’t provide any change

 FSM-design procedure
1. State diagram

Reset
2. State-transition table
3. State minimization
4. State encoding
5. Next-state logic minimization
6. Implement the design

N
Vending Open
Coin Machine Release
Sensor FSM Mechanism
D

Clock

CSE370, Lecture 18 10
A vending machine:
(conceptual) state diagram
Reset (from all states)

S0
N D
Draw self-loops for
N’ D’ for S0 to S3
S1 S2 Also draw self-loops for
1 for S4 to S8
N D N D

S3 S4 S5 S6
[open] [open] [open]
N D

S7 S8
[open] [open]

CSE370, Lecture 18 11
A vending machine: State transition table

present inputs next output

state D N state open
S0 0 0 S0 0
0 1 S1 0
1 0 S2 0
1 1 X X
S1 0 0 S1 0
0 1 S3 0
1 0 S4 0
1 1 X X
S2 0 0 S2 0
0 1 S5 0
1 0 S6 0
1 1 X X
S3 0 0 S3 0
0 1 S7 0
1 0 S8 0
1 1 X X
S4 X X S4 1
S5 X X S5 1
S6 X X S6 1
S7 X X S7 1
S8 X X S8 1
CSE370, Lecture 18 12
A vending machine: State minimization

Reset present inputs next output

N’D’ state D N state open
0¢ 0 0 0¢ 0
0 1 5¢ 0
0¢ 1 0 10¢ 0
1 1 – –
N’D’ N 5¢ 0 0 5¢ 0
0 1 10¢ 0
D 1 0 15¢ 0
5¢
1 1 – –
N 10¢ 0 0 10¢
0 1 15¢ 0
D 10¢ 1 0 15¢ 0
1 1 – –
N+D 15¢ – – 15¢ 1

15¢ symbolic state table

[open] Reset

CSE370, Lecture 18 13
A vending machine: State encoding

present state inputs next state output

Q1 Q0 D N D1 D0 open
0 0 0 0 0 0 0
0 1 0 1 0
1 0 1 0 0
1 1 – – –
0 1 0 0 0 1 0
0 1 1 0 0
1 0 1 1 0
1 1 – – –
1 0 0 0 1 0 0
0 1 1 1 0
1 0 1 1 0
1 1 – – –
1 1 – – 1 1 1

CSE370, Lecture 18 14
 A vending machine: Logic minimization

Q1 Q1 Q1
D1 D0 Open
0 0 1 1 0 1 1 0 0 0 1 0
0 1 1 1 N 1 0 1 1 N N
0 0 1 0
D X X X X D X X X X D X X 1 X
1 1 1 1 0 1 1 1 0 0 1 0
Q0 Q0 Q0

D1 = Q1 + D + Q0 N

D0 = Q0’ N + Q0 N’ + Q1 N + Q1 D

OPEN = Q1 Q0

CSE370, Lecture 18 15
A vending machine: Implementation

CSE370, Lecture 18 16