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Vlsi Module-5

This document discusses semiconductor memories and testing and verification. It covers topics like logic verification principles, silicon debug, manufacturing tests, fault models, observability and controllability, design for test, boundary scan, and built-in self-test. Testing ensures chips perform their intended functions before production and can occur at the wafer, package, board, system, and field levels. Logic verification checks functional equivalence through simulation. Debugging prepares for issues found during initial tests. Manufacturing tests check for defects introduced during fabrication. Design for test focuses on improving observability and controllability to make testing easier.

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Phanindra Reddy
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346 views56 pages

Vlsi Module-5

This document discusses semiconductor memories and testing and verification. It covers topics like logic verification principles, silicon debug, manufacturing tests, fault models, observability and controllability, design for test, boundary scan, and built-in self-test. Testing ensures chips perform their intended functions before production and can occur at the wafer, package, board, system, and field levels. Logic verification checks functional equivalence through simulation. Debugging prepares for issues found during initial tests. Manufacturing tests check for defects introduced during fabrication. Design for test focuses on improving observability and controllability to make testing easier.

Uploaded by

Phanindra Reddy
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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MODULE-5

SEMICONDUCTOR MEMORIES
And
TESTING AND VERIFICATION
Introduction
• Semiconductor memory arrays capable of storing large
quantities of digital information are essential to all digital
systems.
• The amount of memory required in a particular system
depends on the type of application.
• The area efficiency of the memory array, i.e., the number of
stored data bits per unit area, is one of the key design criteria
that determine the overall storage capacity and, hence, the
memory cost per bit.
• Memory circuits are generally classified according to the type
of data storage and the type of data access.
TESTING AND VERIFICATION
CONTENTS
• Testing
• Logic verification principles
• Silicon debug
• Manufacturing Test
• Fault models
• Observability and controllability
• Design for Test
• Boundary scan
• Testing is one of the most expensive parts of chips.
• The first set of tests verifies that the chip performs its intended
function. These tests, called functionality tests or logic
verification, are run before tape out to verify the functionality
of the circuit.
• Testing a die (chip) can occur at the following levels:
 Wafer level
 Packaged chip level
 Board level
 System level
 Field level
LOGIC VERIFICATION
• You can check functional equivalence through
simulation at various levels of the design hierarchy.
• If the description is at the RTL level, the behavior at
a system level may be able to be fully verified.
• At each level, you can write small tests to verify the
equivalence between the new higher-level functional
model and the lower-level gate or functional level.
• At the top level, you can surround the filter functional
model with a software environment that models the
real-world use of the filter
• Verification at the top chip level using an FPGA
emulator offers several advantages over simulation.
DEBUGGING
• Many times, when a chip returns from fabrication, the first set
of tests are run in a lab environment, so you need to prepare
for this event.
You can begin by constructing a circuit board that provides the
following attributes:
• Power for the IC with ability to vary VDD and measure power
dissipation
• Real-world signal connections (i.e., analog and digital inputs
and outputs as required)
• Clock inputs as required (it is helpful to have a stable variable-
frequency clock generator)
• A digital interface to a PC.
MANUFACTURING TESTS
Whereas verification or functionality tests seek to
confirm the function of a chip as a whole,
manufacturing tests are used to verify that every gate
operates as expected.
• Layer-to-layer shorts (e.g., metal-to-metal)
• Discontinuous wires (e.g., metal thins when crossing
vertical topology jumps)
• Missing or damaged vias
• Shorts through the thin gate oxide to the substrate or
well.
Logic verification principles

• Figure 15.6(a) shows a combinational circuit with N inputs. To


test this circuit exhaustively, a sequence of 2N inputs (or test
vectors) must be applied and observed to fully exercise the
circuit.
• This combinational circuit is converted to a sequential circuit
with addition of M registers, as shown in Figure 15.6(b).
TEST VECTORS
• Test vectors are a set of patterns applied to inputs and
a set of expected outputs. Both logic verification and
manufacturing test require a good set of test vectors.
• Directed and random vectors are the most common
types.
• Directed vectors are selected by an engineer who is
knowledgeable about the system.
REGRESSION TESTING
High-level language scripts are frequently used when
running large test benches, especially for regression
testing.
Fault models
• To deal with the existence of good and bad parts, it is
necessary to propose a fault model.
• The most popular model is called the Stuck-At model.
• The Short Circuit/ Open Circuit model can be a closer fit to
reality, but is harder to incorporate into logic simulation tools.
Stuck-at Faults
• In the Stuck-At model, a faulty gate input is modeled as a
stuck at zero (Stuck-At-0, S-A0) or stuck at one (Stuck-At-l,
S-A-l). This model dates from board-level designs, where it
was determined to be adequate for modeling faults.
• Figure 15.11 illustrates how an S-A-0 or S-A-1 fault might
occur. These faults most frequently occur due to gate oxide
shorts.
Short circuit and open circuit
Other models include stuck-open or shorted
models.
Observability:
• The Observability of a particular circuit node is the degree to
which you can observe that node at the outputs of an
Integrated circuit(pins).
• Ideally you should be able to observe directly or with
moderate indirections.
Controllability:
• The Controllability of an integrated circuit within a chip is a
measure of the ease of testing the node to a 1 or 0 state.
• It is important when assessing the degree of difficulty of
testing a particular signal with in a circuit.
• An easily controllable node would be directly settable via an
input pad.
Repeatability
• The repeatability of system is the ability to produce the
same outputs given the same inputs.
• Combinational logic and synchronous sequential logic
is always repeatable when it is functioning correctly.
• However, certain asynchronous sequential circuits are
nondeterministic. For example, an arbiter may select
either input when both arrive at nearly the same time.
• Testing is much easier when the system is repeatable.
Some systems with asynchronous interfaces have a
lock-step mode to facilitate repeatable testing.
Survivability
• The survivability of a system is the ability to continue
function after a fault. For example, error-correcting
codes provide survivability in the event of soft errors.
• Adaptive techniques provide survivability in the
event of process variation. Some survivability
features are invoked automatically by the hardware,
while others are activated by blowing fuses after
manufacturing test.
Automatic Test pattern generation
• Automatic Test Pattern Generation (ATPG) methods
have been invented. The use of some form of ATPG is
standard for most digital designs.
.
Design for Testability
• The keys to designing circuits that are testable are
controllability and observability.
• controllability is the ability to set (to 1) and reset (to 0) every
node internal to the circuit.
• Observability is the ability to observe, either directly or
indirectly, the state of any node in the circuit.
• Good observability and controllability reduce the cost of
manufacturing testing because they allow high fault coverage
with relatively few test vector.
We will first cover three main approaches to what is commonly
called Design for Testability (DFT). These may be categorized as
follows:
• Ad hoc testing
• Scan-based approaches
• Built-in self-test (BIST).
Ad HOC testing:
Ad hoc test techniques, as their name suggests, are collections of
ideas aimed at reducing the combinational explosion of testing.
• Partitioning large sequential circuits
• Adding test points
• Adding multiplexers
• Providing for easy state reset
SCAN DESIGN
• The scan-design strategy for testing has evolved to provide
observability and controllability at each register.
• In designs with scan, the registers operate in one of two
modes. In normal mode, they behave as expected.
• In scan mode, they are connected to form a giant shift register
called a scan chain spanning the whole chip.
• By applying N clock pulses in scan mode, all N bits of state in
the system can be shifted out and new N bits of state can be
shifted in.
• Therefore, scan mode gives easy observability and
controllability of every register in the system.
Modern scan is based on the use of scan registers, as shown in
Figure 15.16.
Parallel scan
The basic idea is shown in Figure 15.17. The figure shows a two-
by-two register section.
Scannable register design
Built in self-test(BIST)
• These techniques add area to the chip for the test logic,
but reduce the test time required and thus can lower the
overall system cost.
• One method of testing a module is to use signature
analysis or cyclic redundancy checking.
• This involves using a pseudo-random sequence
generator (PRSG) to produce the input signals for a
section of combinational circuitry and a signature
analyzer to observe the output signal.
• A PRSG of length n is constructed from a linear
feedback shift register (LFSR), which in turn is made of
n flip-flops connected in a serial fashion.
A complete feedback shift register (CFSR), shown in
Figure 15.19(b), includes the zero state that may be
required in some test situations.
3-bit Register
Analog and Digital loop back
Analog/digital converter testing requires real-time access to the
digital output of the ADC.
If both ADCs and DACs are present, a loopback strategy can be
employed, as shown in Figure.

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