Features of 8086

- 8086 is a 16 bit microprocessor, It

can perform read & write operation
on both 8 or 16 bit data..
- 8086 has 16 bit data bus & 20 bit
address bus.

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 Features of 8086 ( continued)
- 20 bit address lines capable of
addressing 1MB memory location
- 16 bit data are stored in 2
consecutive memory locations
- 8086 can generate 16 bit I/O
address , 256 = 65536 I/O ports

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 Features of 8086 ( continued)
- 8086 has fourteen 16 bit registers
- 8086 has multiplexed address & data
bus
- 8086 operates in 2 modes ,
minimum( single processor ) &
maximum( multi processor) modes

- 8086 has 6 byte prefetch instruction

Queue

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 Registers Organisation
 16-Bit General Purpose Registers
– can access all 16-bits at once
– can access just high (H) byte, or
low (L) byte
only the General
Purpose registers
allow access as
8-bit High/Low
sub-registers

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 Registers Organisation (continued)
 Register Set
16-Bit Segment Addressing Registers
CS Code Segment
DS Data Segment
SS Stack Segment
ES Extra Segment

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 Registers Organisation (continued)
16-Bit Offset Addressing Registers
SP Stack Pointer
BP Base Pointer
SI Source Index
DI Destination Index

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 Registers Organisation (continued)
16-Bit Control/Status Registers
- IP Instruction Pointer (Program
Counter for execution control)
- FLAGS 16-bit register
• It is not a 16-bit value but it is a
collection of 9 bit-flags (six are unused)
• Flag is set when it is equal to 1
• Flag is clear when it is equal to 0

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 Architecture

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 Architecture (continued)
 The 8086 has two parts, the Bus
Interface Unit (BIU) and the Execution
Unit (EU).
 The BIU fetches instructions, reads and
writes data, and computes the 20-bit
address
 The EU decodes and executes the
instructions using the 16-bit ALU.

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 Architecture (continued)
 The BIU contains the following
registers
- IP - the Instruction Pointer
- CS - the Code Segment Register
- DS - the Data Segment Register
- SS - the Stack Segment Register
- ES - the Extra Segment Register

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 Architecture (continued)
 The BIU fetches instructions using
the CS and IP, written CS:IP, to
construct the 20-bit address. Data is
fetched using a segment register
(usually the DS) and an effective
address (EA) computed by the EU
depending on the addressing mode

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 Architecture (continued)
 The EU contains the following 16-bit general
purpose registers:
» AX - the Accumulator
» BX - the Base Register
» CX - the Count Register
» DX - the Data Register
» SP - the Stack Pointer \ defaults to
» BP - the Base Pointer / Stack segment
» SI - the Source Index Register
» DI - the Destination Register

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 Architecture (continued)

HIGH BYTE GP REGISTERS LOW BYTE

AH AX AL
BH BX BL
CH CX CL
DH DX DL
8 BIT 16 BIT 8 BIT

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 Architecture (continued)
ES Extra Segment
CS Code Segment
BIU registers SS Stack Segment
(20 bit adder) DS Data Segment
IP Instruction Pointer

AX AH AL Accumulator
BX BH BL Base Register
CX CH CL Count Register
DX DH DL Data Register
SP Stack Pointer
BP Base Pointer
SI Source Index Register
EU registers
DI Destination Index Register
16 bit arithmetic
FLAGS
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 General purpose Registers
 AX
 Accumulator Register
 Preferred register to use in arithmetic,
logic and data transfer instructions
because it generates the shortest Machine
Language Code
 Must be used in multiplication and division
operations
 Must also be used in I/O operations

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 General purpose Registers (conti..)
 BX
 Base Register
 Also serves as an address register
 Used in array operations
 Used in Table Lookup operations (XLAT )

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 General purpose Registers (conti..)
 CX
 Count register
 Used as a loop counter
 Used in shift and rotate operations
 DX
 Data register
 Used in multiplication and division
 Also used in I/O operations

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 Pointer & Index Registers
 Contain the offset addresses of
memory locations
 Can also be used in arithmetic and
other operations
 SP: Stack pointer
 Used with SS to access the stack segment

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 Pointer & Index Registers (continued)
 BP: Base Pointer
 Primarily used to access data on the stack
 Can be used to access data in other
segments
 SI: Source Index register
 is required for some string operations
 When string operations are performed, the
SI register points to memory locations in
the data segment which is addressed by
the DS register. Thus, SI is associated
with the DS in string operations.

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 Pointer & Index Registers (continued)
 DI: Destination Index register
 is also required for some string operations.
 When string operations are performed, the
DI register points to memory locations in
the data segment which is addressed by
the ES register. Thus, DI is associated with
the ES in string operations.
 The SI and the DI registers may also be used
to access data stored in arrays

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 Segment Registers
 Are Address registers
 Store the memory addresses of
instructions and data
 Memory Organization
 Each byte in memory has a 20 bit address
starting with 0 to 220-1 or 1 meg of
addressable memory

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 Segment Registers (continued)
 Addresses are expressed as 5 hex digits
from 00000 - FFFFF
 Problem: But 20 bit addresses are TOO BIG
to fit in 16 bit registers!
 Solution: Memory Segment
– Block of 64K (65,536) consecutive memory
bytes
– A segment number is a 16 bit number

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 Segment Registers (continued)
– Segment numbers range from 0000 to
FFFF
– Within a segment, a particular memory
location is specified with an offset
– An offset also ranges from 0000 to
FFFF

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 Segment Registers (continued)

Memory Model for 20-bit Address Space

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  to calculate physical memory address

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 Memory Address Generation
Offset Value (16 bits)

Segment Register (16 bits) 0000

Adder

Physical Address (20 Bits)

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 Flag Register

Overflow Carry flag

Direction Parity flag

Interrupt enable Auxiliary flag

Trap Zero

Sign
6 are status flags
3 are control flag

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 Pinout Diagram

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 Minimum mode operation

Ground Power Supply

5V  10%

Reset
Registers, seg regs, flags
CS: FFFFH, IP: 0000H
Clock If high for minimum 4 clks
Duty cycle: 33%

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 Minimum mode operation ( Conti..)

Address/Data Bus:
Contains address bits
A15-A0 when ALE is 1 &
data bits D15 – D0 when Address Latch Enable:
ALE is 0.
When high, multiplexed
address/data bus contains
address information.

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 Minimum mode operation ( Conti..)

INTERRUPT

Non-maskable interrupt

Interrupt acknowledge
Interrupt request

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 Minimum mode operation ( Conti..)
Direct Memory Access

Hold

Hold acknowledge

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 Minimum mode operation ( Conti..)
S6: Logic 0.

S5: Indicates
condition of IF flag
bits.
Address/Status Bus
Address bits A19 – A16 &
S4-S3: Indicate
Status bits S6 – S3
which segment is
accessed during
current bus cycle:

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 Minimum mode operation ( Conti..)

BHE#, A0: Bus High Enable/S7

Enables most significant
0, 0: Whole word
data bits D15 – D8 during
(16-bits)
read or write operation.
0,1: High byte S7: Always 1.
to/from odd address

1,0: Low byte

to/from even address

1,1: No selection

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 Minimum mode operation ( Conti..)
Min/Max mode
Minimum Mode: +5V
Maximum Mode: 0V

Min mode pins

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 Minimum mode operation ( Conti..)

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 Minimum mode operation ( Conti..)

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 Minimum mode operation ( Conti..)

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 Minimum mode operation ( Conti..)
Read Signal

Write Signal

Memory or I/0

Data Bus Enable

Used by external data bus buffers

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 Maximum mode operation

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 Maximum mode operation ( Conti..)

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 Maximum mode operation ( Conti..)
S2 S1 S0
000: INTA
001: read I/O port
010: write I/O port
011: halt
Status Signal
100: code access
Inputs to 8288 to
101: read memory
generate eliminated
110: write memory
signals due to max
111: none -passive
mode.

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 Maximum mode operation ( Conti..)

DMA
Request/Grant

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 Maximum mode operation ( Conti..)

Lock Output
Used to lock
peripherals off the Lock Output
system
Activated by using
the LOCK: prefix
on any instruction

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 Maximum mode operation ( Conti..)

QS1 QS0
00: Queue is idle
01: First byte of opcode
Queue Status
10: Queue is empty
Used by numeric
11: Subsequent byte of
opcode coprocessor (8087)

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 Minimum mode operation ( Conti..)

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 Minimum mode operation ( Conti..)

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 Memory Banking

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