TOP LEVEL VIEW OF

COMPUTER FUNCTION
ABEBE A. FEBRUARY, 2021
INTRODUCTION

Today we will focus on presenting a top-level view of computer

function.
• Main components of computer and their function?
• How are these components organized?
• How do these components communicate with each other?
INTRODUCTION

• At a top level, a computer consists of:

• Central Processing Unit;
• Memory;
• I/O components.

• The components are interconnected in order to execute programs.

COMPUTER COMPONENTS

Does anyone know who this person is?

 COMPUTER COMPONENTS

• Virtually all contemporary computer designs are based on concepts developed by John von Neumann:

• Von Neumann architecture is based on three concepts:

• Data and instructions are stored in a single read–write memory
• The contents of this memory are addressable by location, without regard to the type of data contained there
• Execution occurs in a sequential fashion (unless explicitly modified) from one instruction to the next.
• Ability to process inputs/outputs;
 • Consider the original method for
computation based on digital circuits:
• Employs a small set of logical gates:
• AND, OR, NOT, NAND, NOR, XOR,
XNOR
• Employ some type of memory:
COMPUTER • Flip-flop SR, JK, D
COMPONENTS
DISADVANTAGE WITH USING DIGITAL
CIRCUITS…
• Rigid design (hardwired program):
• Only works for a specific function...

• What if we need to calculate additional functions?

• Requires generating a new circuit...
• producing new truth tables;
• algebraic simplification;
• circuit design.
• Basically a lot of work...
 ALTERNATIVE…

• Suppose that instead of having such a hardwired circuit we have:

• We construct a general-purpose configuration of arithmetic and logic functions.

• A module capable of calculating :

• Logic functions:
• AND, OR, NOT, NAND, NOR, XOR, XNOR
• Arithmetic functions:
• addition, subtraction, multiplication, division, SHL, SHR,...
 SOLUTION…

• We also need a way to control such a module:

• In the original case of hardwired hardware, the system accepts data and produces result
• With general-purpose hardware
• The system accepts data and control signals and produces results.
• Thus, instead of rewiring the hardware for each new program, the programmer merely needs to
supply a new set of control signals

How shall the control signals be supplied?

 ANSWER…

• Program is a sequence of steps;

• At each step, an arithmetic/logical operation is performed on data;
• For each step, a new set of control signals is needed.
• Let us provide a unique code for each possible set of control signals, and
• let us add a segment that can accept a code and generate control signals
 SOFTWARE PROGRAMMING
• Programming is now much easier.
• Instead of rewiring the hardware for each new
program, all we need to do is provide a new sequence
of codes.
• Each code is, in effect, an instruction, and part of the
hardware interprets each instruction and generates
control signals.
• To distinguish this new method of programming, a
sequence of codes or instructions is called software
 COMPUTER COMPONENTS

• An instruction interpreter capable of generating

control signals;
• A general-purpose module for arithmetic/logic
functions.
• These two constitute the CPU
• Is this capability enough to have a functional
computer
 COMPUTER COMPONENTS

• Data and instructions must be provided to the system:

• Input module:
• contains basic components for accepting data and instructions
• Output module:
• contains the means of reporting results.

• Taken together, these are referred to as I/O components.

• Are these two components enough for a functional computer?
 COMPUTER COMPONENTS

• An input device will bring instructions and data in sequentially, but

• A program may not always be executed sequentially;
• it may jump around (e.g., the IAS jump instruction)
• Data operations may require access to more than one element:
• there must be a place to store both instructions and data.
• that module is called main memory
• to distinguish it from external storage
 COMPUTER COMPONENTS

• We have thus the main components of the von Neumann

architecture:
• Memory module
• I/O module
• CPU
We will be having a more detailed look at these components
COMPUTER
COMPONENTS

A top Level view of the

main computer
components (Source
Stallings)
 COMPUTER COMPONENTS -CPU

• CPU has a set of internal registers :

• Program Counter (PC):
• specifies the memory address of the next instruction to be
executed.
• Instruction Register (IR):
• holds the instruction currently being executed or decoded.
 COMPUTER COMPONENTS -CPU

• memory address register (MAR):

• specifies memory address to be read/written;
• memory buffer register (MBR):
• contains the data to be written into memory or...
• receives the data read from memory;
 COMPUTER COMPONENTS - CPU

• I/O address register (I/OAR):

• specifies a particular I/O device;
• I/O buffer (I/OBR) register:
• used for the exchange of data between an I/O module and the CPU;
 COMPUTER COMPONENTS -MEMORY

• Memory module consists of:

• Set of sequentially numbered addresses;
• Each location contains binary information (word);
• Data;
• Or instructions.
 COMPUTER COMPONENTS – I/O

• I/O module responsible for:

• Transfers data from external devices to CPU and memory;
• and vice versa
• Containing internal buffers for temporarily holding data
how do these components function together to execute
programs?
COMPUTER FUNCTION

• Basic function performed by a computer is execution of a

program:
• Consisting of a set of instructions stored in memory;
• Processor does the actual work by executing the specified
instructions;
• This gives us a hint of how to perform instruction processing...
BASIC INSTRUCTION CYCLE

• In its simplest form, instruction processing consists of two steps:

• Fetch stage:
• processor reads instructions from memory one at a time
• Execution stage:
• processor executes the instruction
BASIC INSTRUCTION CYCLE

• Program execution consists of a loop:

• 1 Fetch instruction stage;
• 2 Execute instruction stage
BASIC INSTRUCTION CYCLE

• At the beginning of each instruction cycle:

• Program counter holds the address of the instruction to be fetched;
• Processor fetches an instruction from memory;
• After each instruction fetch the PC is incremented.
• In order to fetch the memory address of next instruction
 EXAMPLE

• Consider a computer where each instruction occupies 16-bits in memory.

• Assume that the PC is set to memory location 300;
• Each location address contains a 16-bit word;
• The processor will next fetch the instruction at location 300.
• On succeeding instruction cycles, it will fetch instructions from locations:
• 301;
• 302;
• 303 and so on.

• This sequence may be altered.

 BASIC INSTRUCTION CYCLE

• The fetched instruction is loaded into a register in the

processor
• Known as the instruction register (IR);
• Instruction specifies control signals for the processor;
• Processor interprets the instruction and performs the required
action.
• What types of actions are usually performed?
BASIC INSTRUCTION CYCLE

• In general, these actions fall into four categories:

• Processor ↔ memory data transfers;
• Processor ↔ I/O peripherals data transfers;
• Data processing: arithmetic or logic operations on data;
• Control: E.g. alter the PC because of conditional jumps (IF’s)
• Let’s see those in an example
EXAMPLE

• Consider a processor:
• Containing a single data register, called an accumulator
(AC).
• Both instructions and data are 16 bits long;
• Convenient to organize memory using 16-bit words;
EXAMPLE

• Instruction format is the following:

• Opcode: code of the operation to be executed (+,-,×, ÷,etc...);

• How many bits are reserved for the opcode? Total combinations?
• Addressing memory,
• How many bits are reserved for the addressing memory? Total combinations?
EXAMPLE

• Opcode: code of the operation to be executed (+,-,×, ÷,etc...);

• 4 bits are reserved, i.e there can be different opcodes;
• Addressing memory,
• 12 bits are reserved, i.e. memory words can be addressed.
EXAMPLE

• Consider that we have the following opcodes:

• Also, each data requires 16 bits and has the following representation:1
bit for sign and 15 bits for magnitude
EXAMPLE

• Now lets try to execute the following instructions (assume PC=300):

• Add (sum) memory contents at address 940 to the contents at address
941;
• Store the result in the latter location.
EXAMPLE
EXAMPLE
EXAMPLE
EXAMPLE
EXAMPLE
EXAMPLE
EXAMPLE

• In textual form:
• The PC contains value 300, the address of the first instruction.
• This instruction (the value 1940 in hexadecimal) is loaded into the instruction register IR, and the PC is
incremented;
• The first 4 bits (first hexadecimal digit) in the IR indicate that the AC is to be loaded.
• The remaining 12 bits (three hexadecimal digits) specify the address (940) from which data are to
be loaded.
• The next instruction (5941) is fetched from location 301, and the PC is incremented.
• The old contents of the AC and the contents of location 941 are added, and the result is stored in the AC.
• The next instruction (2941) is fetched from location 302, and the PC is incremented.
• The contents of the AC are stored in location 941.
CLASS WORK

• Now lets try to execute the following instructions (assume PC=300):

• Add memory contents at address 940 to the contents at address 941;
• Add memory contents at address 941 to the contents at address 942;
• Store the result in the latter location -942.
?
BASIC INSTRUCTION CYCLE

• Some important notes:

• Last example was very simplified;
• But the overall control structure and information flow is
present;
• However, there are a lot of details missing;
• Lets look into a more detailed instruction cycle...
DETAILED INSTRUCTION CYCLE
DETAILED INSTRUCTION CYCLE

• The states can be described as follows:

• Instruction address calculation (IAC):
• Determine address of next instruction to be executed;

• Instruction fetch (IF):

• Read instruction from memory into the processor;

• Instruction operation decoding (IOD):

• Determine type of operation to be performed and operand(s) to be used.
DETAILED INSTRUCTION CYCLE

• Operand address calculation (OAC):

• Determine the address of the operand.
• Operand fetch (OF):
• Fetch the operand from memory or read it in from I/O.

• Data operation (DO):

• Perform the operation indicated in the instruction.
• Operand store (OS):
• Write the result into memory or to I/O.
DETAILED INSTRUCTION CYCLE

• Do you think those steps are enough? Should we add

other states? Is there something missing?
DETAILED INSTRUCTION CYCLE

• There exists some situations where we may want to interrupt the CPU:
• Program: arithmetic overflow, division by zero, segfault, etc..
• Timer: execute something periodically;
• I/O: exchange communication between I/O devices and the processor;
• Hardware: generated by a hardware failure
• e.g.: power, memory parity error, etc;
INTERRUPTS

• Because of these reasons (and some others):

• Computers provide a mechanism to interrupt the
processing;
• Virtually all computers provide a mechanism to
interrupt the normal processing of the processor.
• How does that work?
 INTERRUPTS

1. An interrupt request signal is sent to the processor.

2. The processor responds by suspending current program execution;
3. The processor executes a routine capable of dealing with the interrupt;
• A.k.a. interrupt handler.

4. After the handler finishes, the program returns to the original execution.
INTERRUPTS

There is some overhead involved in this process:

• Extra instructions must be executed:
• to determine the nature of the interrupt;
• decide the appropriate action.
• But what if multiple interruptions being generated at the same time?
• Example:
• A key is pressed;
• A segfault is generated;
MULTIPLE INTERRUPTS

• Suppose that multiple interrupts can occur, e.g.: a program may

be
• receiving data from a communications line:
• an interruption is generated every time a unit of data arrives.
• printing:
• an interruption is generated every time a print operation is completed;
• How should the system deal with such cases? (2 possibilities)
FIRST POSSIBILITY

• Disable interrupts while an interrupt is being processed:

• The processor will ignore interrupt request signals;
• Emphasis on the ‘‘ignore’’, interrupt signals can still be
generated.
• After the interrupt handler routine completes:
• Interrupts are enabled;
• the processor checks to see if any interrupts have occurred.
 ISSUES OF THE FIRST ONE

• Can you see any problem with this approach of disabling

interrupts while processing an interruption?
• Ignoring interruptions may have serious implications
SECOND POSSIBILITY

• Don’t ignore and allow each interruption to have a

priority:
• Higher priority interruptions can interrupt lower-
priority interruptions.
• This strategy is referred to as nested interrupt
processing
EXAMPLE
EXAMPLE
• Program begins at t = 0 and at t = 10, a printer interrupt occurs:
1. context is saved;
2. execution goes to the printer interrupt service routine (ISR);
3. While this routine is executing (t = 15), a communications interrupt
occurs:
1. Higher priority than the printer;
2. Printer ISR is interrupted, context is saved;
3. Execution goes to the communication ISR;
1. While this routine is executing, a disk interrupt occurs (t = 20);
2. Because this interrupt is of lower priority, it is simply held;
3. and the communications ISR runs to completion.
 EXAMPLE

4. When the communications ISR completes (t = 25):

1. printer ISR state is restored;
2. However, there is a pending higher-priority interruption (disk);
1. Processor transfers control to the disk ISR;
2. disk ISR completes at t = 35;
3. printer ISR is resumed;
4. printer ISR terminates at t = 40;

5. control returns to the original program.

 INTERCONNECTION
ISSUES

• A computer consists of a set basic

types of components:
• These modules need to communicate
with each other in order to :
• exchange data and address;
• exchange control signals;

• Any idea how this communication can

be performed?
 BUS INTERCONNECTION

• A bus is a communication pathway connecting two or more devices:

• shared transmission medium;
• connected devices can pickup data from all other devices.
• If several devices transmit during the same time period:
• their signals will overlap and become garbled:
• thus, only one device at a time can successfully transmit.
 BUS INTERCONNECTION

• A bus consists of multiple communication lines:

• Each line transmits binary signals.
• A sequence of binary digits can be transmitted:
• using a single line over time (i.e. sequentially);
• several lines can be used (i.e. in parallel ).

• A bus connecting major computer components is called a system bus.

• What type of information does the bus carry?
BUS STRUCTURE

• Bus lines can be classified into three functional groups:

• data:
• for moving data among system modules
• address
• for specifying the source or destination of the data:
• control
• for transmitting command information among the modules.
• Lets have a quick look into each one of these...
BUS STRUCTURE
DATA LINES

• The data bus may consist of 32, 64, 128, or even more separate lines:
• a.k.a. width of the data bus;

• Each line can carry only 1 bit at a time:

• the number of lines determines how many bits can be transferred at a time.

• Data bus width is key to system performance, e.g.:

• if the data bus is 32 bits wide and each instruction is 64 bits long;
• Each instruction requires two memory accesses.
 ADDRESS LINES

• Used to designate the source or destination of the data on the data bus:
• The width of the address bus determines the maximum system memory;
• How much memory the CPU can address directly Ex. 32 bits
• The address lines are generally also used to address I/O addresses;
• Higher-order bits are used to select a particular module on the bus;
• Lower-order bits select a memory location or I/O port within the module.
 CONTROL LINES

• Command signals specify operations to be performed, e.g.:

• Memory write: write bus data to a memory address;
• Memory read: read memory at memory address;
• I/O write: write bus data to an I/O address;
• I/O read: read data from an I/O address;
• Bus request: a module needs to gain control of the bus;
• Bus grant: a requesting module has been granted bus control;
• Many more control signals...
 BUS STRUCTURE

• What happens if a great number of devices are connected to the bus?

• If a great number of devices are connected bus performance will
suffer.
 SINGLE BUS PROBLEMS

• Single Bus Problems

• Lots of devices on one bus leads to:
• Propagation delays
• Long data paths mean that co-ordination of bus use can adversely
affect performance
• Bus may become bottleneck
• Most systems use multiple buses to overcome these problems
 MULTIPLE-BUS HIERARCHIES

•Idea: Use several buses to

distribute communication effort;
• This implies that there needs to be a bus
hierarchy, e.g.:
 MULTIPLE-BUS
HIERARCHIES
• Local bus connecting:
• processor;
• cache memory;
• one or more local devices.

•System bus:
• where the main memory module is attached;
• that also connects to the cache;

•Note: in contemporary systems, the cache is

in the same chip as the processor.
ELEMENTS OF BUS DESIGN

• Parameters that can be used to classify and differentiate buses e.g.:

• Lets have a look at some of these...

 BUS TYPE

• Bus lines can be separated into two generic types:

• dedicated: line is used for a single purpose:
• e.g.: the use of separate dedicated address and data lines
• multiplexed: line is used for multiple purposes:
• e.g.: address and data information may be transmitted over the same lines
• Idea: use an Address Valid control line:
• Activate Address Valid line;
• Place the address on the bus lines;
• Transfer the data after.
• Can you see any advantages / disadvantages with multiplexing?
 BUS TYPE

• Multiplexing advantage:
• use of fewer lines, which saves space and, usually, cost.
• Multiplexing disadvantage:
• more complex circuitry is needed within each module;
• potential reduction in performance:
• certain events that share the same lines cannot take place in
parallel.
ELEMENTS OF BUS DESIGN – READING ASSIGNMENT

Design two buses based on the

parameter. Compare and contrast each
design based on the parameters selected.