Lec 10 Combinational Logic Circuits
Lec 10 Combinational Logic Circuits
Lec 10 Combinational Logic Circuits
Lec 10
Combinational CMOS
Logic Circuits
In Combinational Out
Combinational
In Logic Out Logic
circuit circuit
State
Combinational Sequential
The output is determined only by The output is determined by
•Current inputs •Current inputs
•Previous inputs
In1
In2 pMOS
Pull Up Network (PUN)
…
Network
InN
f(In1,In2,…InN)
In1
In2 nMOS
… Network Pull Down Network (PDN)
InN
A B
Y = X if A and B=AB
X Y
X B Y = X if A OR B=A+B
Y
A B
X
Y = X if A AND B = A+B
Y
A
X B
Y Y = X if A OR B = AB
VDD VDD
PUN
S D
VDD
S D
A B AB
AB A B
• The complementary gate is inverting
IDB,p
IDA,p
ID
IDA,n
IDB,n
V th V T ,n I D
kn IDB,p
• PMOS-B operates in the linear region, and PMOS-A is in A
saturation for Vin = Vout, F
I DB , p
kp
2
2 V DD V th V T , p V SDB , p V 2SDB , p A IDA,n B IDB,n
kp
I DA, p
2
V DD V th V T , p V SDB , p
2
V DD V th V T , p 2 I D k
p
V T ,n
kp
V DD V T , p
kn
V th ( INV )
kp
1
kn
12 CMOS Digital Integrated Circuits
CMOS NOR2
Threshold Calculation (3/3)
• If kn = kp and VT,n = |VT,p| , Vth(INV) = VDD/2. However,
V DD V T ,n
V th ( NOR 2)
3
Equivalent-Inverter Approach (both inputs are identical)
» The parallel connected nMOS transistors can be represented
by a nMOS transistor with 2kn.
» The series connected pMOS transistors can be represented by
a pMOS transistor with kp/2.
VDD
kp/2
Vin Vout
2kn
V T ,n
kp
V DD V T , p
4k n
V th ( NOR 2)
kp
1
4k n
• To obtain a switching threshold voltage of VDD/2 for
simultaneous switching, we have to set VT,n = |VT,p| and kp=4kn
V T ,n 2
kp
V DD V T , p
kn
V th ( NAND 2)
k
1 2 p
kn
• To obtain a switching threshold voltage of VDD/2 for simultaneous
switching, we have to set VT,n = |VT,p| and kn=4kp
VDD
VDD
M2
In Out
M1
Out
In
Inverter
GND
VDD
VDD
A B
A
Out
INV NAND2
Out Out
In
GND GND
A B
19 CMOS Digital Integrated Circuits
Stick Diagram (2/2)
VDD VDD
INV
NAND2
Out Out
In A B
GND GND
A 1 B
A B A D
VDD OUT
D C B
C D C
2
OUT
GND
• On the dual graph, which of the two side nodes is labeled VDD or
OUT is functionally arbitrary. The selection may, however, affect
the location of capacitances, and hence, the performance.
23 CMOS Digital Integrated Circuits
Complex CMOS Gates
Device Sizing in Complex Gates (1/4)
• Method used for sizing NAND and NOR gates also applies to
complex gates
• Most easily transferred by examining all possible paths from
OUT to GND (and from VDD to OUT)
• Suppose that we are dealing with CMOS and the sized inverter
devices use minimum channel lengths and widths Wn and Wp.
• For the pull-down network:
1. Find the length nmax of the longest paths between OUT and through
GND the network. Make the width of the nFETs on these paths
nmaxWn.
In this algorithm, a path is a series of FETs
that does not contain any complementary pair of literals such as X
and X.
2. For next longest paths through the circuit between OUT and GND
consisting of nFETs not yet sized, repeat Step 1.
3. Repeat Step 2 until there are no full paths consisting of unsized
nFETS
24 CMOS Digital Integrated Circuits
Complex CMOS Gates
Device Sizing in Complex Gates (2/4)
4. For each longest partial path in the circuit consisting of unsized
nFETs, based on the longest path between OUT and GND on
which it lies, find the equivalent Weq required for the partial path.
5. Repeat Step 1 for each longest partial path from Step 4 with OUT
and GND replaced the endpoints of the partial path. Make the
widths of devices on the path equal to nmaxWeq where nmax is the
number of FETs on the partial path.
6. Repeat 4 and 5 for newly generated longest partial paths until all
devices are sized.
B E
G F
D
GND
• This can be illustrated for the example above. Ln =0.5μ, Wn=5 μ,
in the inverter.
1. A longest path through the network from OUT to GND is A-
B-C-D with nmax=4. Thus, the widths WA, WB, WC, WD are
45=20 μ. This is the only longest path we can find from
26 CMOS Digital Integrated Circuits
Complex CMOS Gates
Device Sizing in Complex Gates (4/4)
OUT to GND without passing through a sized device.
2. H and G are partial path. But it is important that they are
considered as part of a longest between OUT and GND for
evaluation. Thus, a “split” partial path consisting of H and G
must be considered. Based on the evaluation segments,
Weq =2Wn=10μ. Thus, WH and WG are 110=10 μ.
3. The longest remaining partial path in the circuit is E-F with nmax
= 2. Since this path is in series with A with width 4Wn=20 μ, it
needs to have an equivalent width of Weq determined from:
1 1 1 1 1 1
Wn 4W n W eq 5 20 W eq
E
B C
B C pMOS network
OUT
A B A B
E D C D E C
nMOS network
D S S D S D
pMOS
D S S D
Out
D S
nMOS
D S D S D S S D
GND
A E B D C
E E-D-A-B-C
D C B C
S D D S
pMOS
D S D S S D
Out
D S
nMOS
D S S D S D D S
GND
E D A B C
31 CMOS Digital Integrated Circuits
Complex CMOS Gates
AOI Gates
• AOI (AND-OR-INVERT): Enable the sum-of-products
realization of a Boolean function in one logic gate.
» The pull-down network consists of parallel branches of
series-connected nMOS driver transistors.
» The corresponding pull-up network can be found using the
dual-graph concept.
VDD
Example: OUT = A1A2A3+B1B2+C1C2C3 Dual pMOS
Pull-up network
A1
A2 OUT
A3
A1
B1 B1 C1
B2
A2
C2
C1
C2
C3 A3
B2 C3
C1
A3 A2 A3
OUT
C1
B1 B2
A3 A2 A3
VDD
• N transistors + Load
Resistive
Load • VOH = VDD
RL
• VOL = RPN
VDD
F RPN + RL
• tpL = 0.69 RL CL
VSS
VDD VDD
Depletion PMOS
Load VT < 0 Load
VSS
F F
In1 In1
In2 PDN In2 PDN
In3 In3
VSS VSS
VDD
F
CL
A B C D
VOL k p
2
k n VDD VTn VOL
2 2
VDD VTp
2
kp
VOL VDD VT 1 1 (Assuming VT VTn |VTp|)
k n
Sum 0 1 0 1 0 propagate
0 1 1 0 1 propagate
1 0 0 1 0 propagate
1 0 1 0 1 propagate
1 1 0 0 1 generate
1 1 1 1 1 generate
Cin Full
Cout
adder
Sum
Sum = ABCin
= ABCin + ABCin + ABCin + ABCin
= ABC + (A+B+C)Cout
at least two of A, B, and C are zeros
Cout = AB + BCin + ACin
S0 S1 S2 S3
Worst case delay linear with the number of bits
p = O(N)
adder (N-1)carry + sum
Goal: Make the fastest possible carry path circuit
42 CMOS Digital Integrated Circuits
CMOS Full-Adder Circuit
Transistor-Level of One-Bit Full-Adder Circuit
V DD
VDD
Ci A B
A B
A
B
Ci B
V DD
A
X
Ci
Ci A S
Ci
A B B V DD
A B Ci A
Co B
28 transistors
43 CMOS Digital Integrated Circuits
CMOS Full-Adder Circuit
Inversion Property
A B A B
Ci FA Co Ci FA Co
S S
S(A,B,Ci) = S(A,B,Ci)
Co(A,B,Ci) = Co(A,B,Ci)
S0 S1 S2 S3
A0 B0 A1 B1 A2 B2 A3 B3
S0 S1 S2 S3
45 CMOS Digital Integrated Circuits
CMOS Full-Adder Circuit
Minimize Critical Path by Reducing Inverting Stages (2/2)
Even cell Odd cell
A0 B0 A1 B1 A2 B2 A3 B3
S0 S1 S2 S3
VDD VDD A
A B B A B Ci B
Kill
"0"-Propagate A Ci
Co
Ci S
A Ci
"1"-Propagate Generate
A B B A B Ci A
B
24 transistors
47 CMOS Digital Integrated Circuits
CMOS Full-Adder Circuit
The Mirror Adder (2/3)
• Only need 24 transistors.
• NMOS and PMOS chains are completely symmetrical. This
guarantees identical rising and falling time if the NMOS and
PMOS devices are properly sized.
• A maximum of two series transistors can be observed in the
carry generation circuitry.
• The critical issue is to minimize the capacitance at node C0.
• Capacitance at node C0
» 4 diffusion capacitances
» 2 internal gate capacitances
» 6 gate capacitances in the connecting adder cell
A total 12 gate capacitances (Assume Cdiffusion Cgate)
• The transistors connected to Ci are placed closest to the output.
• Only the transistors in the carry stage have to be optimized for
speed. All transistors in the sum gate can be minimum-size.
A A
B A
B
A Ci
VDD
B
A B Ci B A Ci Co Ci A B
Co
Vin Vout VC = 0
A B A B
C
C
Circuit Popular Usage
51 CMOS Digital Integrated Circuits
Transmission Gates (2/2)
• Operation
» C is logic high Both transistors are turned on and provide
a low-resistance current path between nodes A and B.
» C is logic low Both transistors will be off, and the path
between nodes A and B will be open circuit. This condition
is called the high-impedance state.
• With the parallel pFET added, it can transfer a full VDD from A
to B (or B to A). It can also charge driven capacitance faster.
• The substrates of NMOS and PMOS are connected to ground
and VDD, respectively. Therefore, the substrate-bias effect must
be taken into account.
ID ISD,p
Vin=VDD Vout
IDS,n
VDD
• The nMOS transistor, VDS,n=VDD–Vout, and VGS,n=VDD–Vout. Thus,
» Turn off: If Vout > VDD – VT,n
» Saturation: If Vout < VDD – VT,n
• The pMOS transistor, VDS,p=Vout–VDD, and VGS,p= –VDD. Thus,
» Saturation: If Vout < |VT,p |
» Linear: If Vout > |VT,p |
53 CMOS Digital Integrated Circuits
Transmission Gates
DC Analysis (2/3)
Region 1 Region 2 Region 3
Vout
0V |VT,p| (VDD-VT,n ) VDD
• The current flowing through the transmission gate is equal to
ID = IDS,n + ISD,p
• The equivalent resistance for each transistor can be represented as
Req,n = (VDD-Vout)/IDS,n
Req,p = (VDD-Vout)/ IDS,p
and
Req = Req,n ║ Req,p
• Region 2
2(V DD V out )
Req ,n 2
k n V DD V out V T ,n
2
Req , p
k p 2V DD | V T , p | V DD V out
• Region 3
2
Req , p
k p 2V DD | V T , p | V DD V out
55 CMOS Digital Integrated Circuits
Resistance of Transmission Gate
R
Req,n
Req,p
Req,n║ Req,p
Vout
0 VDD-VT,n VDD
• The parallel combination of the pFET and the nFET result in an
equivalent resistance that is roughly constant. This constant value,
Req, can be used in series with an ideal switch controlled by C and
C to model the transmission gate. See p. 311 of the text book.
• The implementation of CMOS transmission gates in logic circuit
design usually results in compact circuit structures which may even
require a smaller number of transistors.
B
M2
AB A
A
AB F
M1 M3/M4
B
AS
A
S F = AS+BS
B BS