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Flip Flops

The document contains timing diagrams and descriptions of latches and flip-flops. It describes the differences between latches and flip-flops, and some common types including the SC latch, D latch, JK flip-flop, and D flip-flop. Latches have asynchronous level-sensitive inputs while flip-flops have synchronous clocked inputs. The document also shows how to build basic latches and flip-flops from logic gates including using an edge detector circuit to create a clocked flip-flop.

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Muskan Bhakhar C
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52 views12 pages

Flip Flops

The document contains timing diagrams and descriptions of latches and flip-flops. It describes the differences between latches and flip-flops, and some common types including the SC latch, D latch, JK flip-flop, and D flip-flop. Latches have asynchronous level-sensitive inputs while flip-flops have synchronous clocked inputs. The document also shows how to build basic latches and flip-flops from logic gates including using an edge detector circuit to create a clocked flip-flop.

Uploaded by

Muskan Bhakhar C
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
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SC Latch Timing Diagram

Input S S Q

Latch
0
C
1

Input C
Truth Table
0

1 S C Q

Output Q

0
JK Flipflop Operation
PRE CLR J K CLK Q
0 0 X X X ? Vcc

0 1 X X X 1
1 0 X X X 0 J S Q
1 1 X X — Q CLK
1 1 X X  Q
K
1 1 0 0  Q
C
1 1 0 1  0
1 1 1 0  1
Vcc
1 1 1 1 
JK Flipflop Timing Diagram
1
Input J Vcc
0
1 J S Q

Input K CLK
0
K C
1
Input CLK
Vcc
0
1
Output Q
0

Time
Transparent D-Latch Timing
Transparent D-Latch
D Flip Flop
Latch & Flip Flop Summary
Latches Flip-Flops

Asynchronous inputs are level sensitive Synchronous Control inputs and an


(active-high or active-low) edge-triggering CLK (rising or falling
edge triggered)

SC Latch (AKA RS Latch): SC Flip-Flop:


SET and CLEAR inputs. Could think of SET and CLEAR queries at CLK edge.
those as direct and inverting inputs. Has an unstable input combination.
Has an unstable input combination. Rare.

(No corresponding latch. JK Flip-Flop:


Can’t toggle without a CLK.) Like SC-FF, but unstable input replaced
by toggle mode.
D Latch: D Flip-Flop:
Make D-FF level sensitive. This has Remove toggle and “inverting” inputs
“transparent” and “hold” modes. of JK-FF. Output copies input at CLK
trigger.
Clock Signal Details
tw

T 1 sec
↳ f = 3 Hz
Making an Edge ‘Detector’

CLK CLK*
CLK

CLK

CLK

CLK*
Building a SC Flip Flop

S SET Q
     
 
   
CLK Edge  
Detector
CLK*
   
    Q 
C CLEAR
Building a JK Flip Flop

SET
J
  Q
 
   
Edge    
CLK CLK*
Detector    
 
  Q
 
 
K
CLEAR
Adding Preset & Clear

PRESET

J Set
  Q
CLK Edge
CLK* Detector
  Clear Q
 
K

CLEAR

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