8085 Memory Interfacing

Prepared by
Dr. Hema
Computer Organization and Architecture N 1
(15B11CI313)
 Types of Memory
• ROM
– MROM
– PROM
– EPROM
– EEPROM
• RAM
– SRAM
– DRAM
https://
www.tutorialspoint.com/computer_fundamentals/computer_rom.htm

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Types of Memory
Types of Memory
Table showing the memory device size and corresponding address pins

Size Binary Decimal Address pins Address pin

range

1K 210 1024 10 A0-A9

2K 211 2048 11 A0-A10

4K 212 4096 12 A0-A11

8K 213 8192 13 A0-A12

1M 220 1048576 20 A0-A19

Table showing the address range [starting address – ending address ]

Size Hex Example End Address

Starting Address
1K 400H 10000H 103FFH
4K 1000H 14000H 14FFFH
64K 10000H 30000H 3FFFFH
Catalog listing of memory devices
Catalog Number of Bits per Device
listing memory mem. Loc name
location
1K x 8 1K 8 8K

16K x 1 16K 1 16K

64K x 4 64K 4 256K

Table showing the EPROM part numbers and their
details

EPROM Details Number of Address Bits per mem. Data pins

number Mem. pins Loc
Locations
2704 512 x 8 512 9 8 8
2708 1K x 8 1K 10 8 8
2716 2K x 8 2K 11 8 8
2732 4K x 8 4K 12 8 8
2764 8K x 8 8K 13 8 8
27256 32K x 8 32K 15 8 8
27512 64K x 8 64K 16 8 8
271024 128K x 8 128K 17 8 8
 Memory Chip structure
• It has n input address lines, therefore, the size
of the memory is 2n.
• It has m data lines, and therefore can store m
bits of data for each address.
• The main lines of control for the memory are
OE CE
WE
• When ^OE and
^OE, ^WE, is low, the processor is reading
^CS.
from the memory and the memory should be
outputting data on its data lines.
• When ^WE is low, then the processor is
writing data and the memory should be
inputting data to store in the memory cells.
• If ^CS or ^CE or ^S is high, the data lines of
the chip are disabled. It is if the chip is not
even connected.
• When ^CS is low, the data lines are enabled
for input or output based on the state of ^OE
and ^WE.
http://faculty.etsu.edu/tarnoff/hmwk2150/chipslct/chipslct.ht
ml
 Decoder Logic in memory Interface

• 1KB memory chip

interface with 8085 RD
WE OE
• For the interfacing, WR
theremaining
address pins 8085 A0- A0- 1KB Memory
be
mustdecoded using A15 A9 Chip

thetechnique A10-
called "Address A15
CS

Decoding". IO/ M

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 Techniques for decoding
i)Logic Gate Decoder (NOT gate decoder)
ii)Logic Gate Decoder (Simple NAND Gate
decoder)
iii) Line Decoder
– The 1-to-2 line decoder
– The dual 2-to-4 line decoder
– The 3-to-8 line decoder
https://deeprajbhujel.blogspot.com/2015/09/how-do-you-interface-8085-
microprocessor.html

ODD SEM 2020 IV-SEM-CSE

 NOT gate decoder
• Consider a system in which the available 64kb memory space is
equally divided between EPROM and RAM. Interface the EPROM
and RAM with 8085 processor.
– Implement 32kb memory capacity of EPROM using single IC 27256.
– 32kb RAM capacity is implemented using single IC 62256.
– The 32kb memory requires 15 address lines and so the address lines A0
- A14 of the processor are connected to 15 address pins of both EPROM
and RAM.
– The unused address line A15 is used as to chip select. If A15 is 1, it select
RAMisand
• Inverter If A15
used forisselecting
0, it select EPROM.
the memory.
• The memory used is both RAM and EPROM, so the low RD and
WR pins of processor are connected to low WE and OE pins of
memory respectively.
• The address range of EPROM will be 0000H to 7FFFH and that of
RAM will be 7FFFH to FFFFH.

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 NAND gate Decoder logic Interfacing

1 0

• 4KB memory Interface

using NAND gate
• Address Range as follows:

https://deeprajbhujel.blogspot.com/2015/09/how-do-
you- interface-8085-microprocessor.html

ODD SEM 2020 IV-SEM-CSE

 2 to 4 decoder(74LS139) logic Memory
Interface
• In 2x4 decoder, Fora
Y0 given input, the outputs
Y0 through Y3 are active
Y1 high if enable input EN
EN
is active high (EN = 1).
Y2
Inputs Output • When (EN=0) and both
E B A Y3Y0 Y1 Y2 Y3 inputs A and B are low
0 0 0 0 1 1 1
(or A= B= 0), the output
0 0 1 1 0 1 1
0 1 0 1 1 0 1
Y0 will be active or LOW
0 1 1 1 1 1 0 and all other outputs
1 X X
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1 1 1 1 will be high.
 2 to 4 decoder logic Memory Interface
• Consider a system in which 32KB memory space is
implemented using four numbers of 8KB memory.
Interface the EPROM and RAM with 8085 processor.
– The total memory capacity is 32KB. So, let two number of 8KB
memory be EPROM and the remaining two numbers be RAM.
– Each 8KB memory requires 13 address lines and so the address
lines A0- A12 of the processor are connected to 13 address
pins of all the memory.
– The address lines and A13 - A14 can be decoded using a 2-to-4
decoder to generate four chip select signals.
– These four chip select signals can be used to select one of the
four memory chips at any one time.
– The address line A15 is used as enable for decoder.
– The simplified schematic memory organization is shown.
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 2 to 4 decoder logic Memory
Interface
15

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 2 to 4 decoder logic Memory Interface

The address allotted to

each memory IC is shown in
following table.

http://www.8085proj
ects.info/Examples-of-
Memory-Interfacing-
Contd-Page3.html

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2 to 4 decoder logic Memory
Interface
 3 to 8 decoder logic interface

• The 3-to-8 Line Decoder (74LS138)

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 3 to 8 decoder logic interface
• Consider a system in which the 64KB memory space is
implemented using eight numbers of 8KB memory.
Interface the EPROM and RAM with 8085 processor.
– The total memory capacity is 64KB. So, let 4 numbers of 8Kb
EPROM and 4 numbers of 8KB RAM.
– Each 8kb memory requires 13 address lines. So the address
line A0 - A12 of the processor are connected to 13address
pins of all the memory chip.
– The address lines A13, A14 and A15 are decoded using a 3-
to-8 coder to generate eight chip select signals. These eight
chip select signals can be used to select one of the eight
memories at any one time.
• The memory interfacing is shown in following figure.
http://www.8085projects.info/Examples-of-Memory-Interfacing-Contd-Page4.h
tml
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https://
www.slides
hare.net/Srikrishn
a Thota/8085-
interfacing-with-
memory-chips-
58311824
 8086 Memory Interface

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3 to 8 Line decoder with 8-bit Memory
Interface

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 Dual 2-to-4 Line Decoder
74LS139 is a dual 2-to-4 line decoder

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Dual 2-to-4 Line Decoder

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8086 8-Bit Memory Interface

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8086 8-Bit Memory Interface

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8086 8-Bit Memory Interface

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8-Bit Memory Interface using 2 to 4
Line Decoder

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8-Bit Memory Interface using 2 to 4 Line Decoder

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Architecture
Simplified Solution

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 Address Range
Input Chip Address Address
A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Range
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00000H
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 00001H
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 00002H
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 00003H
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 00004H
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 00005H SRAM
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 00006H
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 00007H
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 00008H
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 00009H
0 0 0 -----
0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1FFFFH
1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 E000H
1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 E0001H
1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 E0002H
1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 E0003H
1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 E0004H
1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 E0005H EPROM
1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 E0006H
1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 E0007H
1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 E0008H
1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 E0009H
1 1 1 -----
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FFFFFH

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16-Bit Memory Interface

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16-Bit Memory Interface

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16-Bit Memory Interface

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Address Range

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 Reference
• Brey, B.B., 2009. The Intel microprocessors:
8086/8088, 80186/80188, 80286, 80386,
80486, Pentium, Pentium Pro processor,
Pentium II, Pentium III, Pentium 4, and Core2
with 64-bit extensions: architecture,
programming, and interfacing. Pearson
Education India.

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