ARM controllers:

Introduction:

The British computer manufacturer Acorn Computers first developed the Acorn

RISC Machine architecture (ARM) in the 1980s to use in its personal computers.
The official Acorn RISC Machine project started in October 1983. They
chose VLSI Technology as the silicon partner, as they were a source of ROMs and
custom chips for Acorn. Wilson and Furber led the design.

https://www.mepits.com/tutorial/194/arm/arm.

 Some of the advantages of ARM processors are listed below:

 They are cheap as compared to other processors.

 They are designed with such features that it consumes less power.
 The devices with ARM processor can have a much better battery life than other
processors.
 They perform one operation at a time and thus work faster.
 The availability and applications support has also made the users choose
ARM processors.
The ARM Instruction Set - ARM University Program - V1.0
 ARM processors are a particular type of processors which are made by the ARM
holdings PLC. This processor is also known as Reduced Instruction Set
Computing (RISC) in which simple central processing units produce a high
performance quality for the users. It has 32 bits RISC load architecture.
Nowadays ARM processor are widely used in a number of electronic products
such as mobile phones, tablets, multi-media players and many more electrical
devices. The direct administration of the memory is not possible in this design
and is handled by the use of registers. They are also used in personal digital
assistants, digital media and music layers, hand-held gaming systems, and hard
drives of the computer.

ARM processors vs. Intel processors:  When you purchase a processor you will get
to know that some of the designs use Intel Atom processors while the other uses ARM
architecture. These both processors are designed in a way for low-power
operation. They are created to give the mobile a long battery life. But they are both
based on different ideology. The ARM structure is made very simple and is intended
to keep the energy wastage to the minimum. Intel processors are made of complicated
designs to match the compatibility of the company‘s desktop and laptop CPU’s. ARM
processors are being used in the portable devices from a very long time but Intel has
just entered to this area. Intel is believed to have a serious competition with the ARM
technology. The power chips of ARM processors are relatively low in price, so if Intel
will have to reconsider their pricing strategies to compete with it. The entry of ARM
processors and Set
The ARM Instruction their wide
- ARM usage
University has forced
Program - V1.0 Intel to increase their efficiency.
 Simulation is the process of using a simulation software (simulator) to verify the
functional correctness of a digital design that is modeled using a HDL (hardware
description language) like Verilog.

 Synthesis is a process in which a design behavior that is modeled using a HDL

is translated into an implementation consisting of logic gates. This is done by a
synthesis tool which is another software program.

Difference between 8051, AVR, PIC, ARM microcontrollers:

https://www.elprocus.com/difference-between-avr-arm-8051-and-pic-
microcontroller/.

http://www.firmcodes.com/difference-arm-microcontrollers/.

The ARM Instruction Set - ARM University Program - V1.0

 8051 Microcontroller

8051 microcontroller is an 8-bit family of microcontroller is developed by the Intel in the year
1981. This is one of the popular families of microcontroller are being used all across the world.
This microcontroller was moreover referred as “system on a chip” since it has 128 bytes of
RAM, 4Kbytes of a ROM, 2 Timers, 1 Serial port, and 4 ports on a single chip. The CPU can
also work for 8bits of data at a time since 8051 is an 8-bit processor. In case the data is bigger
than 8 bits, then it has to be broken into parts so that the CPU can process easily. Most
manufacturers contain put 4Kbytes of ROM even though the number of ROM can be exceeded
up to 64 K bytes.

PIC Microcontroller

Peripheral Interface Controller (PIC) is microcontroller developed by a Microchip, PIC

microcontroller is fast and simple to implement program when we contrast other
microcontrollers like 8051. The ease of programming and simple to interfacing with other
peripherals PIC become successful microcontroller. We know that microcontroller is an
integrated chip which is consists of RAM, ROM, CPU, TIMER and COUNTERS. The PIC is a
microcontroller which as well consists of RAM, ROM, CPU, timer, counter, ADC (analog to
digital converters), DAC (digital to analog converter). PIC Microcontroller also support the
protocols like CAN, SPI, UART for an interfacing with additional peripherals. PIC mostly used to
modify Harvard architecture and also supports RISC (Reduced Instruction Set Computer) by
the above requirement RISC and Harvard we can simply that PIC is faster than the 8051 based
controllers which is prepared up of Von-Newman architecture.

The ARM Instruction Set - ARM University Program - V1.0

AVR Microcontroller

AVR microcontroller was developed in the year of 1996 by Atmel Corporation. The structural
design of AVR was developed by the Alf-Egil Bogen and Vegard Wollan. AVR derives its name
from its developers and stands for Alf-Egil Bogen Vegard Wollan RISC microcontroller, also
known as Advanced Virtual RISC. The AT90S8515 was the initial microcontroller which was
based on the AVR architecture, though the first microcontroller to hit the commercial market
was AT90S1200 in the year 1997.

AVR Microcontrollers are Available in three Categories:

TinyAVR:- Less memory, small size, appropriate just for simpler applications.

MegaAVR:- These are the mainly popular ones having a good quantity of memory (up to 256
KB), higher number of inbuilt peripherals and appropriate for modest to complex applications.
XmegaAVR:- Used in commercial for complex applications, which need large program memory
and high speed.

The ARM Instruction Set - ARM University Program - V1.0

The ARM Instruction Set - ARM University Program - V1.0
The ARM Instruction Set - ARM University Program - V1.0
The ARM Instruction Set - ARM University Program - V1.0
The ARM Instruction Set - ARM University Program - V1.0
The ARM Instruction Set - ARM University Program - V1.0
The ARM Instruction Set - ARM University Program - V1.0
 Main features of the
ARM Instruction Set
* All instructions are 32 bits long.
* Most instructions execute in a single cycle.
* Every instruction can be conditionally executed.
* A load/store architecture
• Data processing instructions act only on registers
– Three operand format
– Combined ALU and shifter for high speed bit manipulation
• Specific memory access instructions with powerful auto-indexing
addressing modes.
– 32 bit and 8 bit data types and also 16 bit data types on ARM
Architecture v4.
– Flexible multiple register load and store instructions
* Instruction set extension via coprocessors

The ARM Instruction Set - ARM University Program - V1.0

 Processor Modes
 The ARM has seven operating modes:

 User : unprivileged mode under which most tasks run

 FIQ : entered when a high priority (fast) interrupt is raised

 IRQ : entered when a low priority (normal) interrupt is raised

 SVC : (Supervisor) entered on reset and when a Software Interrupt

instruction is executed

 Abort : used to handle memory access violations

 Undef : used to handle undefined instructions

 System : privileged mode using the same registers as user mode

The ARM Instruction Set - ARM University Program - V1.0

 The Registers
 ARM has 37 registers all of which are 32-bits long.
 1 dedicated program counter

 1 dedicated current program status register

 5 dedicated saved program status registers

 30 general purpose registers

 The current processor mode governs which of several banks is accessible. Each
mode can access
 a particular set of r0-r12 registers

 a particular r13 (the stack pointer, sp) and r14 (the link register, lr)

 the program counter, r15 (pc)

 the current program status register, cpsr

Privileged modes (except System) can also access

 a particular spsr (saved program status register)

The ARM Instruction Set - ARM University Program - V1.0

 The ARM Register Set

Current Visible Registers

r0
Abort
Undef
SVC
IRQ
FIQ
User Mode
Mode
Mode
Mode
Mode
r1
r2
r3 Banked out Registers
r4
r5
User,
r6 User FIQ IRQ SVC Undef Abort
SYS
r7
r8 r8 r8
r9 r9 r9
r10 r10 r10
r11 r11 r11
r12 r12 r12
r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp)
r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr)
r15 (pc)

cpsr
spsr spsr spsr spsr spsr spsr

The ARM Instruction Set - ARM University Program - V1.0

  Special function registers: Special Registers
 PC (R15): Program Counter. Any instruction with PC as its destination register is a
program branch.

 LR (R14): Link Register. Saves a copy of PC when executing the BL instruction

(subroutine call) or when jumping to an exception or interrupt routine
- It is copied back to PC on the return from those routines

 SP (R13): Stack Pointer. There is no stack in the ARM architecture. Even so, R13 is
usually reserved as a pointer for the program-managed stack

 CPSR : Current Program Status Register. Holds the visible status register

 SPSR : Saved Program Status Register. Holds a copy of the previous status register
while executing exception or interrupt routines
- It is copied back to CPSR on the return from the exception or interrupt
- No SPSR available in User or System modes

The ARM Instruction Set - ARM University Program - V1.0

 Register Organization
Summary
User,
FIQ IRQ SVC Undef Abort
SYS
r0
r1
r2 User
mode
r3 r0-r7,
r4 r15,
User User User User
and
r5 mode mode mode mode
cpsr
r0-r12, r0-r12, r0-r12, r0-r12,
r6
r15, r15, r15, r15,
r7 and and and and
r8 r8 cpsr cpsr cpsr cpsr
r9 r9
r10 r10
r11 r11
r12 r12
r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp)
r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr)
r15 (pc)

cpsr
spsr spsr spsr spsr spsr

Note: System mode uses the User mode register set

The ARM Instruction Set - ARM University Program - V1.0

 Program Status Registers
31 28 27 24 23 16 15 8 7 6 5 4 0

N Z C V undefined I F T mode

f s x c

 Condition code flags Interrupt Disable bits.

 N = Negative result from ALU I = 1: Disables the IRQ.
 Z = Zero result from ALU F = 1: Disables the FIQ.
 C = ALU operation Carried out
 V = ALU operation oVerflowed
T Bit (Arch. with Thumb mode only)
T = 0: Processor in ARM state
 Mode bits T = 1: Processor in Thumb state
10000 User
10001 FIQ Never change T directly (use BX instead)
10010 IRQ Changing T in CPSR will lead to
10011 Supervisor unexpected behavior due to pipelining
10111 Abort
11011 Undefined Tip: Don’t change undefined bits.
11111 System This allows for code compatibility with
newer ARM processors

The ARM Instruction Set - ARM University Program - V1.0

 Accessing Registers using
ARM Instructions
* No breakdown of currently accessible registers.
• All instructions can access r0-r14 directly.
• Most instructions also allow use of the PC.
* Specific instructions to allow access to CPSR and SPSR.
* Note : When in a privileged mode, it is also possible to load / store the
(banked out) user mode registers to or from memory.
• See later for details.

The ARM Instruction Set - ARM University Program - V1.0

 Condition Flags
Logical Instruction Arithmetic Instruction

Flag

Negative No meaning Bit 31 of the result has been set

(N=‘1’) Indicates a negative number in
signed operations

Zero Result is all zeroes Result of operation was zero

(Z=‘1’)

Carry After Shift operation Result was greater than 32 bits

(C=‘1’) ‘1’ was left in carry flag

Overflow No meaning Result was greater than 31 bits

(V=‘1’) Indicates a possible corruption of
the sign bit in signed
numbers

The ARM Instruction Set - ARM University Program - V1.0

 The Program Counter (R15)
* When the processor is executing in ARM state:
• All instructions are 32 bits in length
• All instructions must be word aligned
• Therefore the PC value is stored in bits [31:2] with bits [1:0] equal to
zero (as instruction cannot be halfword or byte aligned).
* R14 is used as the subroutine link register (LR) and stores the return
address when Branch with Link operations are performed,
calculated from the PC.
* Thus to return from a linked branch
• MOV r15,r14
or
• MOV pc,lr

The ARM Instruction Set - ARM University Program - V1.0

 Exception Handling
and the Vector Table
* When an exception occurs, the core: 0x00000000 Reset

• Copies CPSR into SPSR_<mode> 0x00000004 Undefined Instruction

• Sets appropriate CPSR bits 0x00000008 Software Interrupt
 If core implements ARM Architecture 4T and is 0x0000000C Prefetch Abort
currently in Thumb state, then
 ARM state is entered. 0x00000010 Data Abort

 Mode field bits 0x00000014 Reserved

 Interrupt disable flags if appropriate. 0x00000018 IRQ
• Maps in appropriate banked registers 0x0000001C FIQ
• Stores the “return address” in LR_<mode>
• Sets PC to vector address
* To return, exception handler needs to:
• Restore CPSR from SPSR_<mode>
• Restore PC from LR_<mode>

The ARM Instruction Set - ARM University Program - V1.0

ARM Addressing Modes
There are basically two types of addressing modes
available in ARM
*Pre-indexed addressing: the address generated is
used immediately, First operation then data movement
*Post-indexed addressing: the address generated later
replaces the base register, First data movement and then
operation

The ARM Instruction Set - ARM University Program - V1.0

 ARM Addressing Modes

[Rn] Register
Address accessed is value found in Rn.

Example:
Memory
ldr r0, [r1] @ r0 *r1
.
.
.

r1 r0 Destination
0x200 0x200 0x5 0x5 Register
for ldr
.
.

The ARM Instruction Set - ARM University Program - V1.0

ARM Addressing Modes (Pre-
Indexing)

[Rn, #±imm] Immediate offset

Address accessed is imm more/less than
the address found in Rn. Rn does not
change.

Memory
.
Example: .
ldr r2, [r1, #12] @ r2 ← *(r1 + 12) .

r1 Destination
188 Register
for ldr
r2
200 27 27

The ARM Instruction Set - ARM University Program - V1.0

ARM Addressing Modes (Pre-Indexing)

[Rn, ±Rm] Register offset

Address accessed is the value in Rn ±
the value in Rm. Rn and Rm do not
change values.

Example:
ldr r2, [r0, r1] @ r2 ← *(r0 + r1)

The ARM Instruction Set - ARM University Program - V1.0

 ARM Addressing Modes (Pre-Indexing)

[Rn, ±Rm, shift] Scaled register offset

Address accessed is the value in Rn ±
the value in Rm shifted as specified. Rn
and Rm do not change values.

Example:
ldr r0, [r1, r2, lsl #2] @ r0 ← *(r1 + r2*4)

The ARM Instruction Set - ARM University Program - V1.0

ARM Addressing Modes (Pre-Indexing w\
update
[Rn, #±imm]! Immediate pre-indexed w\update
Address accessed is as with immediate
offset mode, but Rn's value updates to
become the address accessed.

Example:
ldr r2, [r1, #12]! @ r1 ← r1 + 12 then r2 ← *r1

The ARM Instruction Set - ARM University Program - V1.0

ARM Addressing Modes (Pre-Indexing w\
update
[Rn, ±Rm]! Register pre-indexed w\update
Address accessed is as with register offset
mode, but Rn's value updates to become
the address accessed.

Example:
ldr r2, [r0, r1]! @ r0 ← r0 + r1 then r2 ← *r0

The ARM Instruction Set - ARM University Program - V1.0

 ARM Addressing Modes (Pre-Indexing w\ update)

[Rn, ±Rm, shift]! Scaled register pre-indexed w\update

Address accessed is as with scaled register
offset mode, but Rn's value updates to
become the address accessed.

Example:
ldr r2, [r0, r1, lsl #2]! @ r0 ← r0 + r1*4 then r2 ← *r0

The ARM Instruction Set - ARM University Program - V1.0

 ARM Addressing Modes (Post-Indexing)

[Rn], #±imm Immediate post-indexed

Address accessed is value found in Rn, and
then Rn's value is increased/decreased by
imm.

Example:
str r2, [r1], +4 @ *r1 ← r2 then r1 ← r1 + 4

The ARM Instruction Set - ARM University Program - V1.0

 ARM Addressing Modes (Post-Indexing)

[Rn], ±Rm Register post-indexed

Address accessed is value found in Rn, and
then Rn's value is increased/decreased by
Rm.
Example:
str r0, [r1], r2 @ *r1 ← r0 then r1 ← r1 + r2

The ARM Instruction Set - ARM University Program - V1.0

 ARM Addressing Modes (Post-Indexing)

[Rn], ±Rm, shift Scaled register post-indexed

Address accessed is value found in Rn, and
then Rn's value is increased/decreased by
Rm shifted according to shift.
Example:
ldr r0, [r1], r2, lsl #3 @ r0 ← *r1 then r1 ← r1 + r2*8

The ARM Instruction Set - ARM University Program - V1.0

 Examples of pre- and post- indexed
addressing
str r3, [r0, r4, lsl #3] @ pre-indexed
ldr r5, [r0, r1, lsl #3]! @ pre indexed with write back
ldr r0, [r1, #-8] @ pre-indexed with negative offset
ldr r0, [r1, -r2, lsl #2] @ negative offset shifted
ldrb r5, [r1] @ load byte from ea <r1>
ldrsh r5, [r3] @ load signed halfword from ea <r3>
ldrsb r5, [r3, #0xc1] @ load signed byte from ea <r3+193>

str r7, [r0], #4 @ store r7 to ea<r0>, then add #24 to r0

ldr r2, [r0], r4, lsl #2 @ load r2 from ea<r0>, then add r4*4 to r0
ldrh r3, [r5], #2 @ load half word to r3 from ea<r5>, then
@ add #2 to r5
strh r2, [r5], #8 @ store halfword from r2 to ea<r5>, then
@ add 8 to r5
The ARM Instruction Set - ARM University Program - V1.0
 Conditional Execution
* Most instruction sets only allow branches to be executed conditionally.
* However by reusing the condition evaluation hardware, ARM effectively
increases number of instructions.
• All instructions contain a condition field which determines whether the
CPU will execute them.
• Non-executed instructions soak up 1 cycle.
– Still have to complete cycle so as to allow fetching and decoding of
following instructions.
* This removes the need for many branches, which stall the pipeline (3
cycles to refill).
• Allows very dense in-line code, without branches.
• The Time penalty of not executing several conditional instructions is
frequently less than overhead of the branch
or subroutine call that would otherwise be needed.

The ARM Instruction Set - ARM University Program - V1.0

 The Condition Field

31 28 24 20 16 12 8 4 0

Cond

1001 = LS - C clear or Z (set unsigned

0000 = EQ - Z set (equal) lower or same)

0001 = NE - Z clear (not equal) 1010 = GE - N set and V set, or N clear

and V clear (>or =)
0010 = HS / CS - C set (unsigned higher or
same) 1011 = LT - N set and V clear, or N clear
and V set (>)
0011 = LO / CC - C clear (unsigned lower)
1100 = GT - Z clear, and either N set and
0100 = MI -N set (negative) V set, or N clear and V set (>)
0101 = PL - N clear (positive or zero) 1101 = LE - Z set, or N set and V clear,or
0110 = VS - V set (overflow) N clear and V set (<, or =)

0111 = VC - V clear (no overflow) 1110 = AL - always

1000 = HI - C set and Z clear (unsigned higher) 1111 = NV - reserved.

The ARM Instruction Set - ARM University Program - V1.0

 Using and updating the
Condition Field
* To execute an instruction conditionally, simply postfix it with the
appropriate condition:
• For example an add instruction takes the form:
– ADD r0,r1,r2 ; r0 = r1 + r2 (ADDAL)
• To execute this only if the zero flag is set:
– ADDEQ r0,r1,r2 ; If zero flag set then…
; ... r0 = r1 + r2
* By default, data processing operations do not affect the condition flags
(apart from the comparisons where this is the only effect). To cause the
condition flags to be updated, the S bit of the instruction needs to be set
by postfixing the instruction (and any condition code) with an “S”.
• For example to add two numbers and set the condition flags:
– ADDS r0,r1,r2; r0 = r1 + r2
; ... and set flags

The ARM Instruction Set - ARM University Program - V1.0

 Data processing Instructions
* Largest family of ARM instructions, all sharing the same instruction
format.
* Contains:
• Arithmetic operations
• Comparisons (no results - just set condition codes)
• Logical operations
• Data movement between registers
* Remember, this is a load / store architecture
• These instruction only work on registers, NOT memory.
* They each perform a specific operation on one or two operands.
• First operand always a register - Rn
• Second operand sent to the ALU via barrel shifter.
* We will examine the barrel shifter shortly.

The ARM Instruction Set - ARM University Program - V1.0

 Arithmetic Operations
* Operations are:
• ADD operand1 + operand2
• ADC operand1 + operand2 + carry
• SUB operand1 - operand2
• SBC operand1 - operand2 + carry -1
• RSB operand2 - operand1
• RSC operand2 - operand1 + carry - 1
* Syntax:
• <Operation>{<cond>}{S} Rd, Rn, Operand2
* Examples
• ADD r0, r1, r2
• SUBGT r3, r3, #1
• RSBLES r4, r5, #5

The ARM Instruction Set - ARM University Program - V1.0

 Comparisons
* The only effect of the comparisons is to
• UPDATE THE CONDITION FLAGS. FLAGS Thus no need to set S bit.
* Operations are:
• CMP operand1 - operand2, but result not written
• CMN operand1 + operand2, but result not written
• TST operand1 AND operand2, but result not written
• TEQ operand1 EOR operand2, but result not written
* Syntax:
• <Operation>{<cond>} Rn, Operand2
* Examples:
• CMP r0, r1
• TSTEQ r2, #5

The ARM Instruction Set - ARM University Program - V1.0

 Logical Operations
* Operations are:
• AND operand1 AND operand2
• EOR operand1 EOR operand2
• ORR operand1 OR operand2
• BIC operand1 AND NOT operand2 [ie bit clear]
* Syntax:
• <Operation>{<cond>}{S} Rd, Rn, Operand2
* Examples:
• AND r0, r1, r2
• BICEQ r2, r3, #7
• EORS r1,r3,r0

The ARM Instruction Set - ARM University Program - V1.0

 Data Movement
* Operations are:
• MOV operand2
• MVN NOT operand2
Note that these make no use of operand1.
* Syntax:
• <Operation>{<cond>}{S} Rd, Operand2
* Examples:
• MOV r0, r1
• MOVS r2, #10
• MVNEQ r1,#0

The ARM Instruction Set - ARM University Program - V1.0

 The Barrel Shifter
* The ARM doesn’t have actual shift instructions.

* Instead it has a barrel shifter which provides a mechanism to carry out shifts
as part of other instructions.

* So what operations does the barrel shifter support?

The ARM Instruction Set - ARM University Program - V1.0

 Barrel Shifter - Left Shift
* Shifts left by the specified amount (multiplies by powers of two) e.g.
LSL #5 = multiply by 32

Logical Shift Left (LSL)

CF Destination 0

The ARM Instruction Set - ARM University Program - V1.0

 Barrel Shifter - Right Shifts
Logical Shift Right
Logical Shift Right
• Shifts right by the
specified amount
(divides by powers of ...0 Destination CF
two) e.g.
LSR #5 = divide by 32

Arithmetic Shift Right Arithmetic Shift Right

• Shifts right (divides by
powers of two) and
preserves the sign bit, Destination CF
for 2's complement
operations. e.g. Sign bit shifted in
ASR #5 = divide by 32

The ARM Instruction Set - ARM University Program - V1.0

 Barrel Shifter - Rotations
Rotate Right (ROR) Rotate Right
• Similar to an ASR but the bits
wrap around as they leave the
LSB and appear as the MSB. Destination CF
e.g. ROR #5
• Note the last bit rotated is also
used as the Carry Out.

Rotate Right Extended (RRX)

• This operation uses the CPSR Rotate Right through Carry
C flag as a 33rd bit.
• Rotates right by 1 bit. Encoded
as ROR #0. Destination CF

The ARM Instruction Set - ARM University Program - V1.0

 Using the Barrel Shifter:
The Second Operand
Operand Operand * Register, optionally with shift
1 2 operation applied.
* Shift value can be either be:
• 5 bit unsigned integer
• Specified in bottom byte of
Barrel another register.
Shifter
* Immediate value
• 8 bit number
• Can be rotated right through
an even number of
ALU positions.
• Assembler will calculate
rotate for you from
constant.
Result
The ARM Instruction Set - ARM University Program - V1.0
 Second Operand :
Shifted Register
* The amount by which the register is to be shifted is contained in
either:
• the immediate 5-bit field in the instruction
– NO OVERHEAD
– Shift is done for free - executes in single cycle.
• the bottom byte of a register (not PC)
– Then takes extra cycle to execute
– ARM doesn’t have enough read ports to read 3 registers at
once.
– Then same as on other processors where shift is
separate instruction.
* If no shift is specified then a default shift is applied: LSL #0
• i.e. barrel shifter has no effect on value in register.

The ARM Instruction Set - ARM University Program - V1.0

 Second Operand :
Using a Shifted Register
* Using a multiplication instruction to multiply by a constant means first
loading the constant into a register and then waiting a number of
internal cycles for the instruction to complete.
* A more optimum solution can often be found by using some combination
of MOVs, ADDs, SUBs and RSBs with shifts.
• Multiplications by a constant equal to a ((power of 2) ± 1) can be done in
one cycle.
* Example: r0 = r1 * 5
Example: r0 = r1 + (r1 * 4)
ADD r0, r1, r1, LSL #2
* Example: r2 = r3 * 105
Example: r2 = r3 * 15 * 7
Example: r2 = r3 * (16 - 1) * (8 - 1)
RSB r2, r3, r3, LSL #4 ; r2 = r3 * 15
RSB r2, r2, r2, LSL #3 ; r2 = r2 * 7

The ARM Instruction Set - ARM University Program - V1.0

 Multiplication Instructions
* The Basic ARM provides two multiplication instructions.
* Multiply
• MUL{<cond>}{S} Rd, Rm, Rs ; Rd = Rm * Rs
* Multiply Accumulate - does addition for free
• MLA{<cond>}{S} Rd, Rm, Rs,Rn ; Rd = (Rm * Rs) + Rn
* Restrictions on use:
• Rd and Rm cannot be the same register
– Can be avoid by swapping Rm and Rs around. This works because
multiplication is commutative.
• Cannot use PC.
These will be picked up by the assembler if overlooked.
* Operands can be considered signed or unsigned
• Up to user to interpret correctly.

The ARM Instruction Set - ARM University Program - V1.0

 Multiply-Long and
Multiply-Accumulate Long
* Instructions are
• MULL which gives RdHi,RdLo:=Rm*Rs
• MLAL which gives RdHi,RdLo:=(Rm*Rs)+RdHi,RdLo
* However the full 64 bit of the result now matter (lower precision multiply
instructions simply throws top 32bits away)
• Need to specify whether operands are signed or unsigned
* Therefore syntax of new instructions are:
• UMULL{<cond>}{S} RdLo,RdHi,Rm,Rs
• UMLAL{<cond>}{S} RdLo,RdHi,Rm,Rs
• SMULL{<cond>}{S} RdLo, RdHi, Rm, Rs
• SMLAL{<cond>}{S} RdLo, RdHi, Rm, Rs
* Not generated by the compiler.
Warning : Unpredictable on non-M ARMs.

The ARM Instruction Set - ARM University Program - V1.0

 Load / Store Instructions
* The ARM is a Load / Store Architecture:
• Does not support memory to memory data processing operations.
• Must move data values into registers before using them.
* This might sound inefficient, but in practice isn’t:
• Load data values from memory into registers.
• Process data in registers using a number of data processing
instructions which are not slowed down by memory access.
• Store results from registers out to memory.
* The ARM has three sets of instructions which interact with main
memory. These are:
• Single register data transfer (LDR / STR).
• Block data transfer (LDM/STM).
• Single Data Swap (SWP).

The ARM Instruction Set - ARM University Program - V1.0

 Single register data transfer
* The basic load and store instructions are:
• Load and Store Word or Byte
– LDR / STR / LDRB / STRB
* ARM Architecture Version 4 also adds support for halfwords and signed data.
• Load and Store Halfword
– LDRH / STRH
• Load Signed Byte or Halfword - load value and sign extend it to 32 bits.
– LDRSB / LDRSH
* All of these instructions can be conditionally executed by inserting the
appropriate condition code after STR / LDR.
• e.g. LDREQB
* Syntax:
• <LDR|STR>{<cond>}{<size>} Rd, <address>

The ARM Instruction Set - ARM University Program - V1.0

 Load and Store Word or Byte:
Base Register
* The memory location to be accessed is held in a base register
• STR r0, [r1] ; Store contents of r0 to location pointed to
; by contents of r1.
• LDR r2, [r1] ; Load r2 with contents of memory location
; pointed to by contents of r1.
r0 Memory
Source
Register 0x5
for STR

r1 r2
Base Destination
Register 0x200 0x200 0x5 0x5 Register
for LDR

The ARM Instruction Set - ARM University Program - V1.0

 Load and Store Word or Byte:
Offsets from the Base Register
* As well as accessing the actual location contained in the base register, these
instructions can access a location offset from the base register pointer.
* This offset can be
• An unsigned 12bit immediate value (ie 0 - 4095 bytes).
• A register, optionally shifted by an immediate value
* This can be either added or subtracted from the base register:
• Prefix the offset value or register with ‘+’ (default) or ‘-’.
* This offset can be applied:
• before the transfer is made: Pre-indexed addressing
– optionally auto-incrementing the base register, by postfixing the instruction
with an ‘!’.
• after the transfer is made: Post-indexed addressing
– causing the base register to be auto-incremented.
auto-incremented

The ARM Instruction Set - ARM University Program - V1.0

 Load and Store Word or Byte:
Pre-indexed Addressing
r0
* Example: STR r0, [r1,#12] Memory Source
0x5 Register
for STR
Offset
12 0x20c 0x5

r1
Base
Register 0x200 0x200

* To store to location 0x1f4 instead use: STR r0, [r1,#-12]

* To auto-increment base pointer to 0x20c use: STR r0, [r1, #12]!
* If r2 contains 3, access 0x20c by multiplying this by 4:
• STR r0, [r1, r2, LSL #2]

The ARM Instruction Set - ARM University Program - V1.0

 Load and Store Word or Byte:
Post-indexed Addressing
* Example: STR r0, [r1], #12 Memory

r1 Offset r0
Updated Source
Base 0x20c 12 0x5 Register
0x20c
Register for STR

0x200 0x5
r1
Original
Base 0x200
Register
* To auto-increment the base register to location 0x1f4 instead use:
• STR r0, [r1], #-12
* If r2 contains 3, auto-incremenet base register to 0x20c by multiplying
this by 4:
• STR r0, [r1], r2, LSL #2

The ARM Instruction Set - ARM University Program - V1.0

 Load and Stores
with User Mode Privilege
* When using post-indexed addressing, there is a further form of
Load/Store Word/Byte:
• <LDR|STR>{<cond>}{B}T Rd, <post_indexed_address>

* When used in a privileged mode, this does the load/store with user mode
privilege.
• Normally used by an exception handler that is emulating a memory
access instruction that would normally execute in user mode.

The ARM Instruction Set - ARM University Program - V1.0

 Example Usage of
Addressing Modes
* Imagine an array, the first element of which is pointed to by the contents of
r0.
Memory
* If we want to access a particular element, element Offset
then we can use pre-indexed addressing:
• r1 is element we want.
• LDR r2, [r0, r1, LSL #2] 3 12
Pointer to 2 8
* If we want to step through every start of array
1 4
element of the array, for instance r0 0 0
to produce sum of elements in the
array, then we can use post-indexed addressing within a loop:
• r1 is address of current element (initially equal to r0).
• LDR r2, [r1], #4
Use a further register to store the address of final element,
so that the loop can be correctly terminated.

The ARM Instruction Set - ARM University Program - V1.0

 Offsets for Halfword and
Signed Halfword / Byte Access
* The Load and Store Halfword and Load Signed Byte or Halfword
instructions can make use of pre- and post-indexed addressing in much
the same way as the basic load and store instructions.
* However the actual offset formats are more constrained:
• The immediate value is limited to 8 bits (rather than 12 bits) giving an
offset of 0-255 bytes.
• The register form cannot have a shift applied to it.

The ARM Instruction Set - ARM University Program - V1.0

 Block Data Transfer
* The Load and Store Multiple instructions (LDM / STM) allow betweeen
1 and 16 registers to be transferred to or from memory.
* The transferred registers can be either:
• Any subset of the current bank of registers (default).
• Any subset of the user mode bank of registers when in a priviledged
mode (postfix instruction with a ‘^’).
31 28 27 24 23 22 21 20 19 16 15 0

Cond 1 0 0 P U S W L Rn Register list

Condition field Base register Each bit corresponds to a particular

register. For example:
Up/Down bit Load/Store bit • Bit 0 set causes r0 to be transferred.
0 = Down; subtract offset from base 0 = Store to memory • Bit 0 unset causes r0 not to be transferred.
1 = Up ; add offset to base 1 = Load from memory
At least one register must be
Pre/Post indexing bit Write- back bit transferred as the list cannot be empty.
0 = Post; add offset after transfer, 0 = no write-back
1 = Pre ; add offset before transfer 1 = write address into base
PSR and force user bit
0 = don’t load PSR or force user mode
1 = load PSR or force user mode

The ARM Instruction Set - ARM University Program - V1.0

 Block Data Transfer
* Base register used to determine where memory access should occur.
• 4 different addressing modes allow increment and decrement inclusive or
exclusive of the base register location.
• Base register can be optionally updated following the transfer (by
appending it with an ‘!’.
• Lowest register number is always transferred to/from lowest memory
location accessed.
* These instructions are very efficient for
• Saving and restoring context
– For this useful to view memory as a stack.
• Moving large blocks of data around memory
– For this useful to directly represent functionality of the instructions.

The ARM Instruction Set - ARM University Program - V1.0

 Direct functionality of
Block Data Transfer
* When LDM / STM are not being used to implement stacks, it is clearer to
specify exactly what functionality of the instruction is:
• i.e. specify whether to increment / decrement the base pointer, before or
after the memory access.
* In order to do this, LDM / STM support a further syntax in addition to
the stack one:
• STMIA / LDMIA : Increment After
• STMIB / LDMIB : Increment Before
• STMDA / LDMDA : Decrement After
• STMDB / LDMDB : Decrement Before

Note: Load multiple to registers specified and store multiple from

registers.

The ARM Instruction Set - ARM University Program - V1.0

 Example: Block Copy
• Copy a block of memory, which is an exact multiple of 12 words long
from the location pointed to by r12 to the location pointed to by r13.
• r14 points to the end of block to be copied.

; r12 points to the start of the source data

; r14 points to the end of the source data
; r13 points to the start of the destination data
loop LDMIA r12!, {r0-r11} ; load 48 bytes
STMIA r13!, {r0-r11} ; and store them
r13
CMP r12, r14 ; check for the end
BNE loop ; and loop until done
r14 Increasing
Memory

• This loop transfers 48 bytes in 31 cycles

• Over 50 Mbytes/sec at 33 MHz r12

The ARM Instruction Set - ARM University Program - V1.0

 Branch instructions
* Branch : B{<cond>} label
* Branch with Link : BL{<cond>}
sub_routine_label
31 28 27 25 24 23 0

Cond 1 0 1 L Offset

Link bit 0 = Branch

1 = Branch with link
Condition field

* The offset for branch instructions is calculated by the assembler:

• By taking the difference between the branch instruction and the
target address minus 8 (to allow for the pipeline).
• This gives a 26 bit offset which is right shifted 2 bits (as the
bottom two bits are always zero as instructions are word –
aligned) and stored into the instruction encoding.
• This gives a range of ± 32 Mbytes.
The ARM Instruction Set - ARM University Program - V1.0
 Branch instructions
* When executing the instruction, the processor:
• shifts the offset left two bits, sign extends it to 32 bits, and adds it to PC.
* Execution then continues from the new PC, once the pipeline has been
refilled.
* The "Branch with link" instruction implements a subroutine call by writing
PC-4 into the LR of the current bank.
• i.e. the address of the next instruction following the branch with link
(allowing for the pipeline).
* To return from subroutine, simply need to restore the PC from the LR:
• MOV pc, lr
• Again, pipeline has to refill before execution continues.
* The "Branch" instruction does not affect LR.
* Note: Architecture 4T offers a further ARM branch instruction, BX
• See Thumb Instruction Set Module for details.

The ARM Instruction Set - ARM University Program - V1.0

The ARM Instruction Set - ARM University Program - V1.0
 Stacks
* A stack is an area of memory which grows as new data is “pushed” onto
the “top” of it, and shrinks as data is “popped” off the top.
* Two pointers define the current limits of the stack.
• A base pointer
– used to point to the “bottom” of the stack (the first location).
• A stack pointer
– used to point the current “top” of the stack.
PUSH
{1,2,3} POP
SP 3 Result of
2 SP 2 pop = 3
1 1
SP
BASE BASE
BASE

The ARM Instruction Set - ARM University Program - V1.0

 Stack Operation
* Traditionally, a stack grows down in memory, with the last “pushed” value at
the lowest address. The ARM also supports ascending stacks, where the stack
structure grows up through memory.
* The value of the stack pointer can either:
• Point to the last occupied address (Full stack)
– and so needs pre-decrementing (ie before the push)
• Point to the next occupied address (Empty stack)
– and so needs post-decrementing (ie after the push)
* The stack type to be used is given by the postfix to the instruction:
• STMFD / LDMFD : Full Descending stack
• STMFA / LDMFA : Full Ascending stack.
• STMED / LDMED : Empty Descending stack
• STMEA / LDMEA : Empty Ascending stack
* Note: ARM Compiler will always use a Full descending stack.

The ARM Instruction Set - ARM University Program - V1.0

 Stack Examples
STMFD sp!, STMED sp!, STMFA sp!, STMEA sp!,
{r0,r1,r3-r5} {r0,r1,r3-r5} {r0,r1,r3-r5} {r0,r1,r3-r5}

0x418
SP r5 SP
r4 r5
r3 r4
r1 r3
r0 r1
Old SP Old SP r5 Old SP Old SP r0 0x400
r5 r4
r4 r3
r3 r1
r1 r0
SP r0 SP
0x3e8

The ARM Instruction Set - ARM University Program - V1.0

 Stacks and Subroutines
* One use of stacks is to create temporary register workspace for
subroutines. Any registers that are needed can be pushed onto the stack
at the start of the subroutine and popped off again at the end so as to
restore them before return to the caller :
STMFD sp!,{r0-r12, lr} ; stack all registers
........ ; and the return address
........
LDMFD sp!,{r0-r12, pc} ; load all the registers
; and return automatically
* See the chapter on the ARM Procedure Call Standard in the SDT
Reference Manual for further details of register usage within
subroutines.
* If the pop instruction also had the ‘S’ bit set (using ‘^’) then the transfer
of the PC when in a priviledged mode would also cause the SPSR to be
copied into the CPSR (see exception handling module).

The ARM Instruction Set - ARM University Program - V1.0

 Swap and Swap Byte
Instructions
* Atomic operation of a memory read followed by a memory write
which moves byte or word quantities between registers and
memory.
* Syntax:
• SWP{<cond>}{B} Rd, Rm, [Rn]

1
Rn
temp

2 3
Memory
Rm Rd

* Thus to implement an actual swap of contents make Rd = Rm.

* The compiler cannot produce this instruction.

The ARM Instruction Set - ARM University Program - V1.0

 Software Interrupt (SWI)
31 28 27 24 23 0

Cond 1 1 1 1 Comment field (ignored by Processor)

Condition Field

* In effect, a SWI is a user-defined instruction.

* It causes an exception trap to the SWI hardware vector (thus causing a change to
supervisor mode, plus the associated state saving), thus causing the SWI
exception handler to be called.
* The handler can then examine the comment field of the instruction to decide
what operation has been requested.
* By making use of the SWI mechansim, an operating system can implement a set
of privileged operations which applications running in user mode can request.
* See Exception Handling Module for further details.

The ARM Instruction Set - ARM University Program - V1.0

 ARM Pipelining examples

• Fetch: Read Op-code from memory to internal Instruction Register

• Decode: Activate the appropriate control lines depending on Opcode
• Execute: Do the actual processing

The ARM Instruction Set - ARM University Program - V1.0

 The Instruction Pipeline

* The ARM uses a pipeline in order to increase the speed of the flow of
instructions to the processor.
• Allows several operations to be undertaken simultaneously, rather than
serially.
ARM

PC FETCH Instruction fetched from memory

PC - 4 DECODE Decoding of registers used in instruction

Register(s) read from Register Bank

PC - 8 EXECUTE
Shift and ALU operation
Write register(s) back to Register Bank
* Rather than pointing to the instruction being executed, the
PC points to the instruction being fetched.

The ARM Instruction Set - ARM University Program - V1.0

Pipelining :
https://www.slideshare.net/black_pearl/arm-processor?next_slideshow=1.
Note: Slides from 63 to 78 only.

The ARM Instruction Set - ARM University Program - V1.0

 ARM7TDMI Pipelining

1 FETCH DECODE EXECUTE

2 FETCH DECODE EXECUTE

3 FETCH DECODE EXECUTE

instruction
time

• Simple instructions (like ADD) Complete at a rate of one per

cycle

The ARM Instruction Set - ARM University Program - V1.0

 ARM7TDMI Pipelining
• More complex instructions:

1 ADD FETCH DECODE EXECUTE

2 STR FETCH DECODE Cal. ADDR Data Xfer.

3 ADD FETCH stall DECODE EXECUTE

4 ADD FETCH stall DECODE EXECUTE

5 ADD FETCH DECODE EXECUTE

instruction
time

STR : 2 effective clock cycles (+1 cycle)

The ARM Instruction Set - ARM University Program - V1.0

 Pipeline changes for ARM9TDMI

ARM7TDMI

ARM decode
Instruction ThumbARM Reg Reg
Shift ALU
Fetch decompress Read Write
Reg Select

FETCH DECODE EXECUTE

ARM9TDMI
ARM or Thumb
Instruction Inst Decode Memory Reg
Shift + ALU Write
Fetch Reg Reg Access
Decode Read
FETCH DECODE EXECUTE MEMORY WRITE

The ARM Instruction Set - ARM University Program - V1.0

 ARM10 ARM10 vs. ARM11 Pipelines
Branch Memory
Prediction ARM or Shift + ALU
Thumb Reg Read Access Reg
Instruction Write
Instruction Decode
Multiply Multiply
Fetch
Add
FETCH ISSUE DECODE EXECUTE MEMORY WRITE

ARM11

Shift ALU Saturate

Fetch Fetch MAC MAC MAC Write

Decode Issue
1 2 1 2 3 back

Data Data
Address Cache Cache
1 2

The ARM Instruction Set - ARM University Program - V1.0

 Example ARM-based System

16 bit RAM 32 bit RAM

Interrupt
Controller
nIRQ nFIQ
Peripherals I/O

ARM
Core
8 bit ROM

The ARM Instruction Set - ARM University Program - V1.0

 An Example AMBA System
AMBA: Advanced Microcontroller Bus Architecture

High Performance APB

ARM processor UART

High Timer
Bandwidth AHB
APB
External
Bridge
Memory
Interface Keypad

High-bandwidth DMA PIO

on-chip RAM Bus Master
Low Power
Non-pipelined
High Performance Simple Interface
Pipelined
Burst Support
Multiple Bus Masters

Advanced Peripheral Bus (APB), Advanced High-performance Bus (AHB)

The ARM Instruction Set - ARM University Program - V1.0