De 212 AOI Logic Analysis
De 212 AOI Logic Analysis
PLTW Engineering
Digital Electronics
Activity 2.1.2 Frame Generator Introduction
TP1
TP2
TP3
TP5
TP4
TP1
TP2
TP3
Step 1 TP4
TP5
Step 2, 3, and 4 0 0 1 0 1 0 0 0 0
0 1 0 1 1 1 0 1 1
0 1 1 1 1 1 1 0 0
1 0 0 0 0 0 0 1 0
1 0 1 0 0 0 0 0 0
1 1 0 1 0 0 0 1 1
1 1 1 0 0 0 0 0 0
Step 5
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Circuit to Logic Expression to Truth Table
Procedure:
1. Proceed from inputs to the output to write the cumulative
logic expression at the output of each gate concluding with
the expression for the circuit output
2. Use the circuit output logic expression to derive the circuit
truth table
X Y Z F1
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 1
1 0 0 1
1 0 1 1
1 1 0 0
1 1 1 0
Step 1:
A B C F2
0 0 0 0
Step 2: 0 0 1 0
0 1 0 1
0 1 1 1
1 0 0 0
1 0 1 0
1 1 0 1
1 1 1 0