UNIT - 1

BOOLEAN ALGEBRA AND LOGIC

GATES

IFETCE/ECE /II YEAR/III SEM/19UECPC301/DSD/Unit 1/PPT 1

 Syllabus
Review of Number systems, Binary codes,
Boolean postulates: laws & theorems, Boolean
expression – Minimization techniques: Karnaugh
Map, Logic gates, NAND-NOR implementation.
TTL and CMOS family logic.

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Review of Number systems

• Number System -
Code using symbols that refer to
a number of items.

• Decimal Number System -

Uses ten symbols (base 10 system)

• Binary System -
Uses two symbols (base 2 system)
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 PLACE VALUE
• Numeric value of symbols in different positions.
• Example - Place value in binary system:

Place Value 8s 4s 2s 1s

Binary Yes Yes No No

Number 1 1 0 0
RESULT: Binary 1100 = decimal 8 + 4 + 0 + 0 = decimal 12
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 BINARY TO DECIMAL
CONVERSION

Convert Binary Number 110011

to a Decimal Number:

Binary 1 1 0 0 1 1

Decimal 32 + 16 + 0 + 0 + 2 + 1 = 51
IFETCE/ECE /II YEAR/III SEM/19UECPC301/DSD/Unit 1/PPT 5
 DECIMAL TO BINARY
CONVERSION
Divide by 2 Process

Decimal # 13 ÷ 2 = 6 remainder 1

6 ÷ 2 = 3 remainder 0

3 ÷ 2 = 1 remainder 1

1 ÷ 2 = 0 remainder 1

1
IFETCE/ECE /II YEAR/III SEM/19UECPC301/DSD/Unit 1/PPT
1 0 1
6
HEXADECIMAL NUMBER SYSTEM
Uses 16 symbols -Base 16 System
0-9, A, B, C, D, E, F

Decimal Binary Hexadecimal

1 0001 1
9 1001 9
10 1010 A
15 1111 F
16 10000 10

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 HEXADECIMAL AND BINARY
CONVERSIONS
•Hexadecimal to Binary Conversion
Hexadecimal C 3

Binary 1100 0011

•Binary to Hexadecimal Conversion

Binary 1110 1010

Hexadecimal E A
IFETCE/ECE /II YEAR/III SEM/19UECPC301/DSD/Unit 1/PPT 8
DECIMAL TO HEXADECIMAL
CONVERSION

Divide by 16 Process

Decimal # 47 ÷ 16 = 2 remainder 15

2 ÷ 16 = 0 remainder 2

2 F
IFETCE/ECE /II YEAR/III SEM/19UECPC301/DSD/Unit 1/PPT 9
 HEXADECIMAL TO DECIMAL
CONVERSION
Convert hexadecimal number 2DB
to a decimal number
256s 16s 1s
Place Value

2 D B
Hexadecimal

(256 x 2) (16 x 13) (1 x 11)

512 + 208 + 11 = 731
Decimal
IFETCE/ECE /II YEAR/III SEM/19UECPC301/DSD/Unit 1/PPT 10
 OCTAL NUMBERS

Uses 8 symbols -Base 8 System

0, 1, 2, 3, 4, 5, 6, 7

Decimal Binary Octal

1 001 1
6 110 6
7 111 7
8 001 000 10
9 001 001 11
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 Binary Codes
• “An n-bit binary code is a group of n bits that
assume up to 2n distinct combinations of 1s
and 0s, with each combination representing
one element of the set being coded”

• For the 10 digits need a 4 bit code. One code

is called Binary Coded Decimal (BCD)

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 Decimal and BCD

• The BCD is simply the 4

bit representation of the
decimal digit.
• For multiple digit base 10
numbers, each symbol is
represented by its BCD
digit
• What happened to 6
digits not used?
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 Gray Codes
• When you count up or down in binary, the
number of bit that change with each digit change
varies.
– From 0 to 1 just have a single but
– From 1 to 2 have 2 bits, a 1 to 0 transition and a0
to 1 transition
– From 7 to 8 have 3 bits changing back to 0 and 1 bit
changing to a 1
• For some applications multiple bit changes cause
significant problems.

IFETCE/ECE /II YEAR/III SEM/19UECPC301/DSD/Unit 1/PPT 25

 Gray Code
• Contrast of bit changes
– Val Bin Chg Gray Chg
– 0 000 000
– 1 001 1 001 1
– 2 010 2 011 1
– 3 011 1 010 1
– 4 100 3 110 1
– 5 101 1 111 1
– 6 110 2 101 1
– 7 111 1 100 1
– 0 000 3 000 1
IFETCE/ECE /II YEAR/III SEM/19UECPC301/DSD/Unit 1/PPT 26
 Alphanumeric Codes
• How do you handle alphanumeric data?
• Easy answer!
• Formulate a binary code to represent
characters! 
• For the 26 letter of the alphabet would need
5 bit for representation.
• But what about the upper case and lower
case, and the digits, and special characters
IFETCE/ECE /II YEAR/III SEM/19UECPC301/DSD/Unit 1/PPT 27
 Boolean Algebra
• Boolean algebra defined with a set of elements, a set of operators and a
number of postulates.

• The symbol which represent an arbitary elements of an boolean algebra is

called a “Variable”

• Any variable or a function of several variable can have either a 1 or 0.

• Complement of a variable is represented by “bar” : ex, Complement of A is
A’ (A). So If A=1, A’=0

• The logical AND operator of two Variable is represented With a dot

inbetween them (.) such as A.B or AB

• The logical OR operator is A+B

IFETCE/ECE /II YEAR/III SEM/19UECPC301/DSD/Unit 1/PPT 28
 Boolean postulates and laws
Laws of Boolean Algebra

Assume A, B, and C are logical states that can have the values 0 (false) and 1
(true).

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Demorgan’s Theorem

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 DeMorgan’s Theorems
First theorem:

Both used A+B=A B

to eliminate
long overbars
Second theorem:

A B=A+B

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 DeMorgan’s Theorems

First theorem: A+B=A B

Second theorem: A B=A+B

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DeMorgan’s Theorems
START > A B=Y

Step 1: Change all ORs to ANDs and all ANDs to ORs. A B=Y

Step 2: Complement each individual variable

(short overbar).
A+B=Y

Step 3: Complement the entire function

(long overbar).
A+B=Y

Step 4: Eliminate all groups of double overbars.

A+B=Y

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 Distributive Law
• A.(B + C) = AB + AC • A + (B.C) = (A + B).(A + C)
•
• F = WX.(Y + Z) • F = WX + (Y.Z)
• F = WXY + WXZ • F = (WX + Y).(WX + Z)
• G = B'.(AC + AD) • G = B' + (A.C.D)
• G = AB'C + AB'D
• G = (B' + A).(B' + C).(B' + D)
• H = A.(W'X + WX' + YZ)
• H = A + ( (W'X).(WX') )
• H = AW'X + AWX' + AYZ
• H = (A + W'X).(A + WX')

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 Boolean Expression
• Terminology:
– Literal: A variable or its complement
– Product term: literals connected by •
– Sum term: literals connected by +
Product terms Sum Terms

f(A,B,C,D) = A+B’C+ACD’ f(A,B,C,D)= (A+B’).(C+D).(A+C+D’)

Literals

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 Minimization of boolean expression
• Simplify: C + (BC)’:

• C + (BC)’ Original Expression

• C + (B’ + C’) DeMorgan's Law.
• (C + C’) + B’ Commutative, Associative Laws.
• T + B’ Complement Law.
• T Identity Law.

• The boolean Expression can be minimized by Various method

 Sum of Products
 Product of Sums
 Karnaugh Map minimization
 Quine Mccluskey method

IFETCE/ECE /II YEAR/III SEM/19UECPC301/DSD/Unit 1/PPT 36

 Minterms
• Represents exactly one combination in the truth table.
• Denoted by mj, where j is the decimal equivalent of the minterm’s corresponding binary
combination (bj).
• A three variable function such as f(x,y,z), has 2^3=8 minterms
• Every function can be written as a sum of minterms, which is a special kind of sum of
products form
X’Y’Z’ x=0, y=0, z=0 m0
X’Y’Z x=0, y=0, z=1 m1
X’YZ’ x=0, y=1, z=0 m2
X’YZ x=0, y=1, z=1 m3
XY’Z’ x=1, y=0, z=0 m4
XY’Z x=1, y=0, z=1 m5
XYZ’ x=1, y=1, z=0 m6
XYZ x=1, y=1, z=1 m7

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 Maxterms
• A function with n variables has 2^n maxterms
• The maxterms for a three-variable function f(x,y,z): has 8 maxterms

X+Y+Z x=0, y=0, z=0 M0

X+Y+Z’ x=0, y=0, z=1 M1
X+Y’+Z x=0, y=1, z=0 M2
X+Y’+Z’ x=0, y=1, z=1 M3
X’+Y+Z x=1, y=0, z=0 M4
X’+Y+Z’ x=1, y=0, z=1 M5
X’+Y’+Z x=1, y=1, z=0 M6
X’+Y’+Z’ x=1, y=1, z=1 M7

F = (X’+Y+Z)(X’+Y+Z’)(X’+Y’+Z’)
= M4M5M7
= ΠM(4,5,7)
IFETCE/ECE /II YEAR/III SEM/19UECPC301/DSD/Unit 1/PPT 38
• f1(a,b,c) = ∑ m(1,2,4,6), where ∑ indicates that this is a sum-of-
products form, and m(1,2,4,6) indicates that the minterms to
be included are m1, m2, m4, and m6.

• f1(a,b,c) = ∏ M(0,3,5,7), where ∏ indicates that this is a

product-of-sums form, and M(0,3,5,7) indicates that the
maxterms to be included are M0, M3, M5, and M7.

• Since mj = Mj’ for any j,

∑ m(1,2,4,6) = ∏ M(0,3,5,7) = f1(a,b,c)

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39
 Sum Of Products(SOP)
• A sum of products (SOP) expression contains:
 Only OR (sum) operations at the “outermost” level
 Each term that is summed must be a product of literals
• The advantage is that any sum of products expression can be implemented using a
two-level circuit
 literals and their complements at the “0th” level
 AND gates at the first level
 a single OR gate at the second level
f(x,y,z) = y’ + x’yz’ + xz

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• Example

F = A’B’C+A’BC’+AB’C’
= Σm(1,2,4)

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 Product of Sum(POS)
• A product of sums (POS) expression contains:
 Only AND (product) operations at the “outermost” level
 Each term must be a sum of literals
f(x,y,z) = y’ (x’ + y + z’) (x + z)

• Product of sums expressions can be implemented with two-level circuits

 literals and their complements at the “0th” level
 OR gates at the first level
 a single AND gate at the second level

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• Example
A B C F
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 1
1 0 0 1
1 0 1 1
1 1 0 0
1 1 1 0

• F= (A+B+C’)(A+B+C)(A’+B’+C)(A’+B’+C’)
= ΠM(0,2,6,7)

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 Karnaugh Map minimization
• A Karnaugh map comprises a box for every line in the truth
table; the binary value for each box is the binary value of the
input terms in the corresponding table row.
• Normal Binary Sequence (00, 01, 10, 11),
• The Karnaugh map's input values must be ordered 00, 01, 11,
and 10.
• Such that the values for adjacent columns vary by only a
single bit,

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• Two input truth table

• Coressponding K-map

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• Three input Truth table

• Corresponding K-Map

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Four Input Truth Table

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K-Map for 4 Input

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• Looping of K-Map for 2 inputs
Grouping

• In Loop 1 the variable A has both logic 0 and logic 1 values in the same loop. B
has a value of 1. Hence minterm equation is: F = B.
• In Loop 2 Variable B has both logic 0 and 1 values in the same loop. A = 1,
hence minterm equation is: F = A.
• The overall Boolean expression for F is therefore: F= A + B

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• Grouping of K-Map for 3 Input

• In Loop 1 ,C has both logic 0 and logic 1 values in the same loop. A has a
value of 0 and B has a logic value of 1. Hence minterm equation is: F = A ‘B
• In Loop 2 ,the same but A = 1 and B = 0, hence minterm eqn is: F = AB’ .
• In Loop 3 the two variables A and B both have logic 0 and logic 1 values in
the same loop. C has a value of 1. Hence minterm equation is: F = C .
• The overall Boolean expression for F is therefore F = A’B+AB’+C

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IFETCE/ECE /II YEAR/III SEM/19UECPC301/DSD/Unit 1/PPT 54
• In Loop 1 the two variables A and D both have logic 0 and logic 1 values in the same
loop. C has a value of 0 and B has a value of 1. Hence minterm equation is: F =BC’ .

• In Loop 2 the two variables B and C both have logic 0 and logic 1 values in the same
loop. A has a value of 1 and D has a value of 0. Hence minterm equation is: F =AD’ .

• In Loop 3 the variable D has logic 0 and logic 1 values in the same loop. A and B both
have a value of 0 and C has a value of 1. Hence minterm equation is: F =A’B’C .

• In Loop 4 the two variables B and C both have logic 0 and logic 1 values in the same
loop. A has a value of 0 and D has a value of 1. Hence minterm equation is: F = A’D.

• In Loop 5 the variable C has logic 0 and logic 1 values in the same loop. A and D both
have s a value of 1 and B has a value of 0. Hence minterm equation is: F = ADB’.

• The overall Boolean expression for F is therefore: F= BC’ + AD’+ A’B’C + A’D+ ADB’

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AB’C + A’B’C + A’BC + AB’C’ + A’B’C’

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A’BC’D’ + A’BC’D + ABC’D’ + ABC’D + AB’C’D + A’B’CD’

IFETCE/ECE /II YEAR/III SEM/19UECPC301/DSD/Unit 1/PPT 57

 Don’t Care Conditions
• Functions that have unspecified output for some input combinations are
called incompletely specified functions.
• Unspecified minterms of a functions are called ‘don’t care’ conditions. We
simply don’t care whether the value of 0 or 1 is assigned to F for a
particular minterm.
• Don’t care conditions are represented by X in the K-Map table.

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 Quine Mccluskey Method
• The map method is convenient for 3- or 4-variable expressions.
• As the number of variables increases, the excessive number of squares
prevents a reasonable selection of adjacent squares.
• Quine-McCluskey or Tabulation Method.
• By an exhaustive search, find all the terms (called prime implicants) that
are candidates for inclusion in the simplified function.
• Choose among the prime implicants those that give an expression with the
least number of literals.

IFETCE/ECE /II YEAR/III SEM/19UECPC301/DSD/Unit 1/PPT 59

 Algorithm

• Part 1: Find all prime implicants

• Step 2: Apply Adjacency – Compare elements of group with N 1's against
those with N+1 1's. One bit difference implies adjacent. Eliminate variable
and place in next column.
E.g., 0000 vs. 0100 yields 0-00
0000 vs. 1000 yields -000
• When used in a combination, mark with a check. If cannot be combined,
mark with a star. These are the prime implicants.
• Repeat until nothing left.

• For ex : F(A,B,C,D) = Σm(4,5,6,8,9,10,13) + d(0,7,15)

IFETCE/ECE /II YEAR/III SEM/19UECPC301/DSD/Unit 1/PPT 60

Minterms Binary Minterms Binary
Representation Representation
m4 0100 0 0000 

m5 0101 4 0100
m6 0110 8 1000
m8 1000 5 0101
m9 1001 6 0110
m10 1010 9 1001
m13 1101 10 1010
dm0 0000 7 0111
dm7 0111 13 1101
dm15 1111 15 1111

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Minterms Binary Minterm Binary
Representation s Representation
0,4 0-00 *
0,8 -000
4,5 010-  4,5,6,7 01- -
4,6 01-0  5,7,13,15 -1-1
8,9 100- *
8,10 10-0
5,7 01-1 
5,13 -101 
6,7 011- 
9,13 1-01 *
7,15 -111 
13,15 11-1 *

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• Prime implicant’s

• Note: Don’t include DCs in prime

implicant selection chart, they
don’t have to be covered by the
final logic expression

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F=AB’D’+AC’D+A’B

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 Basics gates
AND gate OR gate

Inverter or
NOT gate

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XOR gate XNOR gate

NOR gate NAND gate

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 NOR implementation
Implementing an Inverter Using only NOR Gate

All NOR input pins connect to the input signal A gives an output A’.

Implementing OR Using only NOR Gates

An OR gate can be replaced by NOR gates as shown in the figure (The OR is

replaced by a NOR gate with its output complemented by a NOR gate inverter)

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Implementing AND Using only NOR Gates

An AND gate can be replaced by NOR gates as shown in the figure (The
AND gate is replaced by a NOR gate with all its inputs complemented by
NOR gate inverters)

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 NAND Implementation
Implementing an Inverter Using only NAND Gate

The figure shows in which a NAND gate can be used as an inverter (NOT gate).
All NAND input pins connect to the input signal A gives an output A’.

Implementing AND Using only NAND Gates

An AND gate can be replaced by NAND gates as shown in the figure (The AND is
replaced by a NAND gate with its output complemented by a NAND gate
inverter).

IFETCE/ECE /II YEAR/III SEM/19UECPC301/DSD/Unit 1/PPT 69

Implementing OR Using only NAND Gates

An OR gate can be replaced by NAND gates as shown in the figure (The OR gate is
replaced by a NAND gate with all its inputs complemented by NAND gate inverters).

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 TTL and CMOS family logic
In Digital Electronics, a logic family refers to digital integrated circuit devices which
are constructed with a combination of electronic gates. A family has its own power
supply voltage and distinct logic levels.
IC digital families are
• Resistor-Transistor Logic (RTL)
• Diode-Transistor Logic (DTL)
• Transistor-Transistor Logic (TTL)
• Emitter Coupled Logic (ECL)
• Metal Oxide Semiconductor Logic (MOS)
• Complementary Metal Oxide Semiconductor Logic (CMOS)

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 Special characteristics of digital
• Fan-in
ICs
Fan-in (input load factor is the number of input signals that can be
connected to a gate without causing it to operate outside its intended operating
range. expressed in terms of standard inputs or units loads (ULs).
• Fan-out
This refers to the maximum number of loads connected to the output of the gate. A
logic element having fan-out 20 means 20 logic elements can be connected to its
output. High Fan-out is advantageous because it reduces the need for additional
drivers to drive more gates.
• Propagation Delay
• The propagation delay of a gate is the average transition-delay time for
the signal to propagate from input to output when the binary signal changes in
value. The signals through a gate take a certain amount of time to propagate from
the inputs to the output.

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 Special characteristics of digital
ICs
• Noise margin
Noise margin is the maximum noise voltage added to an input signal of a digital
circuit that does not cause an undesirable change in the circuit output. The ability
of circuits to operate reliably in a noise environment is important in many
applications. Noise margin is expressed in volts and represents the maximum noise
signal that can be tolerated by the gate. Otherwise it is called as Noise immunity.

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Resistor-Transistor Logic (RTL)

Advantages:
* Resistor-Transistor gates are not very
expensive
•They are very simple to construct.
Drawback
They draw a great amount of current from the
power supply. They are used in slower
applications, but cannot be used in today’s
computers as they cannot switch at high
speeds.
Application:
RTL gates can be used as amplifiers as well to
amplify small signals. They can also be used
as an interface between digital and linear
circuits.

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Diode Transistor Logic (DTL)
Advantage:
DTL has some advantages over DL
and RTL. As the diodes can perform AND
and OR operations but along with a
transistor the output signal can be amplified.
In DTL, the signal can be restored to full
logic levels if we add a transistor at the
output of the logic gates. This results in
logic inversion. Another advantage of DTL
is that the OR operation can be performed
by the diodes instead of resistors. This
removes the interaction between input
signals.
Disadvantage:
* The switching speed of the transistor is
limited due to the input resistor to transistor.
* It has power noise margin.
* It has high propagation delay.

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Transistor-Transistor Logic (TTL)

Advantages
* The main advantage of TTL IC’s is that they are compatible with other
IC’s.
* It has high speed of operation.
* Its smaller size yields more function on an IC.
* It has low output impedance which improves the fan out capability.
* It has good noise immunity, in worst case it is 0.4V and typically it
touches 1V.
•It is less expensive.
Disadvantages
* It generates switching transients, which can be eliminated by the use of
bypass capacitors.
* Wired output capability is not possible except with low level and open
collector IC’s.

IFETCE/ECE /II YEAR/III SEM/19UECPC301/DSD/Unit 1/PPT 76

 Emitter Coupled Logic (ECL)
• In Emitter coupled logic, the transistors are prevented from going into deep
saturation so that there are no storage delays. This logic is used in
applications with high speed environment.
• ECL is considered to be one of the best because there is a very low
propagation delay. In fact, it is the fastest bi-polar circuit available today.
• ECL was first introduced in 1962. This logic family bypasses TTL in terms
of speed.
• ECL is also a non-saturated logic. The logic levels for ECL are normally -
0.9V for high logic and -1.6 for low logic.
• The design of ECL consists of termination resistors which allows the
signals to propagate with very low reflection.

IFETCE/ECE /II YEAR/III SEM/19UECPC301/DSD/Unit 1/PPT 77

 CMOS (Complementary Metal Oxide
Semiconductor Logic)

Advantages
* Low cost. Simplicity of design.
* Low heat dissipation.
* Superior fan-out and Wide logic swings.
•Good noise margin performance and Wide-range operation.
Disadvantages
* Slower than Bipolar digital ICs such as TTL devices.
* Careful handling for protects from static discharges is needed.
* Transient voltages can damage the oxide layer in the chip.

IFETCE/ECE /II YEAR/III SEM/19UECPC301/DSD/Unit 1/PPT 78

IFETCE/ECE /II YEAR/III SEM/19UECPC301/DSD/Unit 1/PPT 79
 10111011

IFETCE/ECE /II YEAR/III SEM/19UECPC301/DSD/Unit 1/PPT 80

 Overview
• Integration, Moore’s law
• Early families (DL, RTL)
• TTL
• Evolution of TTL family
• ECL
• CMOS family and its evolution
• Overview

IFETCE/ECE /II YEAR/III SEM/19UECPC301/DSD/Unit 1/PPT 81

 Integration Levels
• Gate/transistor ratio is roughly 1/10
– SSI < 12 gates/chip
– MSI < 100 gates/chip
– LSI …1K gates/chip
– VLSI …10K gates/chip
– ULSI …100K gates/chip
– GSI …1Meg gates/chip

IFETCE/ECE /II YEAR/III SEM/19UECPC301/DSD/Unit 1/PPT 82

 Moore’s law
• A prediction made by Moore (a co-founder of Intel) in
1965: “… a number of transistors to double every 2
years.”

IFETCE/ECE /II YEAR/III SEM/19UECPC301/DSD/Unit 1/PPT 83

 In the beginning…
Diode Logic (DL)
• simplest; does not scale
• NOT not possible (need =
an active element)

Resistor-Transistor
Logic (RTL)
• replace diode switch
with a transistor switch
• can be cascaded =
• large power draw
IFETCE/ECE /II YEAR/III SEM/19UECPC301/DSD/Unit 1/PPT 84
 was…
Diode-Transistor Logic (DTL)
• essentially diode logic with transistor amplification
• reduced power consumption
• faster than RTL

DL AND gate Saturating inverter

IFETCE/ECE /II YEAR/III SEM/19UECPC301/DSD/Unit 1/PPT 85
 Logic families: V levels
VOH(min) – The minimum voltage level at an output in the logical
“1” state under defined load conditions
VOL(max) – The maximum voltage level at an output in the logical
“0” state under defined load conditions
VIH(min) – The minimum voltage required at an input to be
recognized as “1” logical state
VIL(max) – The maximum voltage required at an input that still will
be recognized as “0” logical state

VOH VIH VOL VIL

IFETCE/ECE /II YEAR/III SEM/19UECPC301/DSD/Unit 1/PPT 86
 Logic families: I requirements
IOH – Current flowing into an output in the logical “1” state under
specified load conditions
IOL – Current flowing into an output in the logical “0” state under
specified load conditions
IIH – Current flowing into an input when a specified HI level is
applied to that input
IIL – Current flowing into an input when a specified LO level is
applied to that input

IOH IIH IOL IIL

VOH VIH VOL VIL

IFETCE/ECE /II YEAR/III SEM/19UECPC301/DSD/Unit 1/PPT 87
 Logic families: fanout
Fanout: the maximum number of logic inputs (of the same
logic family) that an output can drive reliably

I OH I OL
DC fanout = min( , )
I IH I IL

IFETCE/ECE /II YEAR/III SEM/19UECPC301/DSD/Unit 1/PPT 88

 Logic families: propagation delay

TPD,HL TPD,LH

TPD,HL – input-to-output propagation delay from HI to LO output

TPD,LH – input-to-output propagation delay from LO to HI output

Speed-power product: TPD Pavg

IFETCE/ECE /II YEAR/III SEM/19UECPC301/DSD/Unit 1/PPT 89

Logic families: noise margin
HI state noise margin:
VNH = VOH(min) – VIH(min)

LO state noise margin:

VNL = VIL(max) – VOL(max)

VNH

Noise margin:
VNL VN = min(VNH,VNL)

IFETCE/ECE /II YEAR/III SEM/19UECPC301/DSD/Unit 1/PPT 90

 TTL
Bipolar Transistor-Transistor Logic (TTL)
• first introduced by in 1964 (Texas Instruments)
• TTL has shaped digital technology in many ways
• Standard TTL family (e.g. 7400) is obsolete
• Newer TTL families still
used (e.g. 74ALS00)

Distinct features
• Multi-emitter transistors
• Totem-pole transistor
arrangement
• Open LTspice example:
2-input
TTL NAND… IFETCE/ECE /II YEAR/III SEM/19UECPC301/DSD/Unit NAND
1/PPT 91
 TTL evolution
Schottky series (74LS00) TTL
• A major slowdown factor in BJTs is due to transistors
going in/out of saturation
• Shottky diode has a lower forward bias (0.25V)
• When BC junction would become forward biased, the
Schottky diode bypasses the current preventing the
transistor from going into saturation

IFETCE/ECE /II YEAR/III SEM/19UECPC301/DSD/Unit 1/PPT 92

 TTL family evolution

Legacy: don’t use Widely used today

in new designs
IFETCE/ECE /II YEAR/III SEM/19UECPC301/DSD/Unit 1/PPT 93
 ECL
Emitter-Coupled Logic (ECL)
• PROS: Fastest logic family available (~1ns)
• CONS: low noise margin and high power dissipation
• Operated in emitter coupled geometry (recall
differential amplifier or emitter-follower), transistors
are biased and operate near their Q-point (never near
saturation!)
• Logic levels. “0”: –1.7V. “1”: –0.8V
• Such strange logic levels require extra effort when
interfacing to TTL/CMOS logic families.
• Open LTspice example: ECL inverter…

IFETCE/ECE /II YEAR/III SEM/19UECPC301/DSD/Unit 1/PPT 94

 CMOS
Complimentary MOS (CMOS)
• Other variants: NMOS, PMOS (obsolete)
• Very low static power consumption
• Scaling capabilities (large integration all MOS)
• Full swing: rail-to-rail output
• Things to watch out for:
– don’t leave inputs floating (in TTL these will float to
HI, in CMOS you get undefined behaviour)
– susceptible to electrostatic damage (finger of death)
• Open LTspice example: CMOS NOT and NAND…

IFETCE/ECE /II YEAR/III SEM/19UECPC301/DSD/Unit 1/PPT 95