ZILOG Z80 CPU

1976 to present (Z80, Z180, eZ80)

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Z80 CPU Pin Assignment
Z80 CPU Pin Assignment
Z80 CPU Chip (Z0840004PSC)
Z80 CPU Internal Architecture
Z80 CPU Chip (Z0840004PSC)
Z80 Registers on the Chip
Z80 PROGRAMMING
 Z80 Registers
15 8 7 0 15 8 7 0

A F A’ F’

B C B’ C’

D E D’ E’

H L H’ L’

I R

IX Index register X
IY Index register Y
SP Stack Pointer
PC Program Counter (Instruction Pointer)
 Z80 Registers
15 8 7 0

A F

B C

D E

H L

SP Stack Pointer
PC Program Counter (Instruction Pointer)
 Z80 Flags
7 6 5 4 3 2 1 0

S Z - H - P/V N C

Carry

Add/Subtract**

Parity/Overflow*

Sign* Zero Half Carry**

* 2-nd complement arithmetic

** For Binary Coded Decimal (BCD) arithmetic
LD PUSH POP ADD ADC SUB SBC
AND OR XOR CP INC DEC EX
EXX LDI LDIR LDD LDDR CPI CPIR
CPD CPDR DAA CPL NEG CCF SCF
NOP HALT DI EI IM RLC RLCA
RL RLA RRC RRCA RR RRA SLA
SRA SRL RLD RRD BIT SET RES
JP JR DJNZ CALL RET RETI RETN
RST IN INI INIR IND INDR OUT
OUTI OTIR OUTD OTDR
 Z80 Instruction Set Overview
• 158 different instruction types (incl. all address modes)
• Includes all 78 of the Intel 8080 CPU instructions
• Total of 693 instructions (with all valid address modes)
• Instruction set is not orthogonal (it is accumulator-based)
• Instruction groups:
 8-bit and 16-bit Load
 8-bit and 16-bit Arithmetic
 Jump
 Call and Return
 Rotate, Shift
 Bit Test, Set, Reset
 Input and Output
 Exchange, Block Transfer, Search
 General-Purpose Arithmetic
 CPU Control
 Z80 Instructions Quick Reference Card

8-bit and 16-bit Load Jump Call and Return

LD PUSH POP JP JR DJNZ CALL RST RET RETI RETN

8-bit and 16-bit Arithmetic Rotate and Shift

ADD ADC SUB SBC CP RLC RLCA RL RLA RRC RRCA RR RRA
INC DEC AND OR XOR SLA SRA SRL RLD RRD

Bit Test, Set, Reset General-Purpose Arithmetic CPU Control

BIT SET RES CPL NEG CCF SCF DAA NOP HALT DI EI IM

Input and Output Exchange, Block Transfer, Search

IN INI INIR IND INDR EX EXX LDI LDIR LDD LDDR

OUT OUTI OTIR OUTD OTDR CPI CPIR CPD CPDR
8-bit and 16-bit Load

• LD – Load
• PUSH – Load to stack
• POP – Load from stack

8-bit and 16-bit Arithmetic

• ADD – Addition
• ADC – Addition with Carry flag
• SUB – Subtraction
• SBC – Subtraction with Carry flag
• AND – Logical AND
• OR – Logical OR
• XOR – Logical XOR
• CP – Compare
• INC – Increment by 1
• DEC – Decrement by 1
Jump

• JP – Jump absolute (direct or indirect to HL, IX, IY)

• JP cc – Jump absolute conditional (cc = NZ, Z, NC, C, PO, PE, P, M)
• JR – Jump Relative
• JR cc – Jump Relative conditional (cc = NZ, Z, NC, C)
• DJNZ – Decrement register B and Jump relative if Not Zero

Call and Return

• CALL – Call absolute

• CALL cc – Call absolute conditional (cc = NZ, Z, NC, C, PO, PE, P, M)
• RST – Restart (quick call)

• RET – Return from subroutine

• RET cc – Conditional Return (cc = NZ, Z, NC, C, PO, PE, P, M)
• RETI – Return from Interrupt
• RETN – Return from Non-maskable interrupt (restores DI/EI status)
Rotate and Shift

• RLC, RLCA – Rotate Left with Carry flag

• RL, RLA – Rotate Left through Carry flag
• RRC, RRCA – Rotate Right with Carry flag
• RR, RRA – Rotate Right through Carry flag
• SLA – Shift Left Arithmetic
• SRA – Shift Right Arithmetic (preserves bit 7)
• SRL – Shift Right Logical
• RLD – Rotate digit left and right between accumulator and (HL)
• RRD – Rotate digit right and left between accumulator and (HL)

Bit Set, Reset, and Test

• BIT – Bit test

• SET – Set bit
• RES – Reset bit
Input and Output

• IN – Load register with input from device (n) or (C)

• INI – Load to memory (HL) from device (C), Increment HL, decrement B
• INIR – INI Repeated until B=0
• IND – Load to memory (HL) from device (C), Decrement HL, decrement B
• INDR – IND Repeated until B=0

• OUT – Load device (n) or (C) with register

• OUTI – Load device (C) from (HL), Increment HL, decrement B
• OTIR – OUTI Repeated until B=0
• OUTD – Load device (C) from (HL), Decrement HL, decrement B
• OTDR – OUTD Repeated until B=0
Exchange, Block Transfer, and Search

• EX – Exchange
• EXX – Exchange extended

• LDI – Load (DE)(HL), Decrement BC, Increment DE, HL

• LDIR – LDI Repeated until BC=0
• LDD – Load (DE)(HL), Decrement BC, Decrement DE, HL
• LDDR – LDD repeated unitl BC=0

• CPI – Compare A and (HL), Increment HL, Decrement BC

• CPIR – CPI until BC=0 or A=(HL)
• CPD – Compare A and (HL), Decrement HL, Decrement BC
• CPDR – CPD until BC=0 or A=(HL)
General-Purpose Arithmetic

• CPL – Binary complement (1st complement)

• NEG – Negative (2nd complement)
• CCF – Complement Carry Flag
• SCF – Set Carry Flag
• DAA – Decimal Adjust

CPU Control

• NOP – No Operation
• HALT – Executes NOPs internally until INT, NMI or RESET
• DI – Disable Interrupts
• EI – Enable Interrupts
• IM n – Interrupt Mode 0, 1, or 2
Z80 Assembly Code Example (ASM)
DISPLAY_FIELD:

LD HL,$5821
LD B,$16
LD C,$1E

.FILL_ROW:
LD (HL),%00100000
INC HL
DEC C
JR NZ,.FILL_ROW

INC HL
INC HL
LD C,$1E
DEC B
JR NZ,.FILL_ROW

RET
Z80 Machine Code Example (BIN)

00100001 00100001 01011000 00000110

00010110 00001110 00011110 00110110
00100000 00100011 00001101 00100000
11111010 00100011 00100011 00001110
00011110 00000101 00100000 11110011
11001001
Z80 Machine Code Example (HEX)

21 21 58 06 16 0E 1E 36
20 23 0D 20 FA 23 23 0E
1E 05 20 F3 C9
Z80 Assembly Code Example
DISPLAY_FIELD:

LD HL,$5821
LD B,$16
LD C,$1E

.FILL_ROW:
LD (HL),%00100000
INC HL
DEC C
JR NZ,.FILL_ROW

INC HL
INC HL
LD C,$1E
DEC B
JR NZ,.FILL_ROW

RET
Z80 Assembly Code to Machine Code
DISPLAY_FIELD:

LD HL,$5821 → 21 21 58
LD B,$16 → 06 16
LD C,$1E → 0E 1E

.FILL_ROW:
LD (HL),%00100000 → 36 20
INC HL → 23
DEC C → 0D
JR NZ,.FILL_ROW → 20 FA

INC HL → 23
INC HL → 23
LD C,$1E → 0E 1E
DEC B → 05
JR NZ,.FILL_ROW → 20 F3

RET → C9
Pseudo Assembly Source to Machine Code
DISPLAY_FIELD:

LDHL $5821 → 21 21 58
LDB $16 → 06 16
LDC $1E → 0E 1E

.FILL_ROW:
LDHLI %00100000 → 36 20
INCHL → 23
DECC → 0D
JRNZ .FILL_ROW → 20 FA

INCHL → 23
INCHL → 23
LDC $1E → 0E 1E
DECB → 05
JRNZ .FILL_ROW → 20 F3

RET → C9
Pseudo Assembly Source to Machine Code
DISPLAY_FIELD:

LDHL $5821 → 21 21 58
LDB $16 → 06 16
LDC $1E → 0E 1E

.FILL_ROW:
LDHLI %00100000 → 36 20
INCHL → 23
DECC → 0D
JRNZ .FILL_ROW → 20 FA

INCHL → 23
INCHL → 23
LDC $1E → 0E 1E
DECB → 05
JRNZ .FILL_ROW → 20 F3

RET → C9
 Zilog Z80 CPU
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