0% found this document useful (0 votes)
50 views30 pages

Lect 04

The document discusses different instruction set architectures including stack, accumulator, register-memory, load-store/register-register. It provides examples of code for adding two numbers in each architecture. Load-store/register-register architectures became dominant after 1980 due to advantages like compact encoding and position independence. The document also discusses addressing modes, popular instructions, control flow instructions, branch encodings, and conditional branching options in instruction sets.
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPT, PDF, TXT or read online on Scribd
0% found this document useful (0 votes)
50 views30 pages

Lect 04

The document discusses different instruction set architectures including stack, accumulator, register-memory, load-store/register-register. It provides examples of code for adding two numbers in each architecture. Load-store/register-register architectures became dominant after 1980 due to advantages like compact encoding and position independence. The document also discusses addressing modes, popular instructions, control flow instructions, branch encodings, and conditional branching options in instruction sets.
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPT, PDF, TXT or read online on Scribd
You are on page 1/ 30

Classifying Instruction Set Architectures

Stack  Register- Register  Register Memory  Accumulator  Memory Memory




Stack


The code C=A+B


   

Push A Push B Add Pop C

Accumulator


The Code C=A+B


  

Load A Add B Store C

Register-Memory


The Code C=A+B


  

Load R1,A Add R3,R1,B Store R3,C

Load-Store/ Register-register


Code C=A+B
   

Load R1,A Load R2,B Add R3,R1,R2 Store R3,C

Virtually every new architecture design after 1980 uses loadstore register architecture!

ANOTHER EXAMPLE
A=B+C B=A+C D=A B Assumptions:
Op Code is 8 bit represented by O, Address is 16-bit represented by A. All registers and data is 32-bit.

(Prob 2.4)

EXAMPLE: Accumulator
Instruc Comments Size of Operand Code
Bytes

Memory Usage
Bytes

Load B Add C Store A Add C Store B Negate Add A Store D

accumulator n B accumulator n B + C store B + C in [A] accumulator n A + C store A + C in B negate accumulator accumulator n B + A store A B in D

O+A O+A O+A O+A O+A O O+A O+A Total =

3 3 3 3 3 1 3 3 22

4 4 4 4 4

4 4 28

Example: Mem to Mem


Instruction Comments Size of Operand Code Bytes Memory Usage

add A, B, C add B, A, C sub D, A, B

; MEM[A] = MEM[B] + MEM[C] ; MEM[B] = MEM[A] + MEM[C] ; MEM[D] = MEM[A] MEM[B]

O+A+A+A O+A+A+A O+A+A+A Total =

7 7 7 21

12 12 12 36

Load-Store
Instruc
LW LW R1, B R2, C

Comments

Size of Operand Code


R= Reg Field (4-bit)
Bytes

Memory Usage
Bytes

R1 n MEM[B] R2 n MEM[C] R3 n B + C MEM[A] = B + C R1 n A + C MEM[B] = A + C R4 n A B MEM[D] = A B

O+A+R = 28bits O+A+R = 28bits O+R+R+R = 20bits O+A+R = 28bits O+R+R+R = 20bits O+A+R = 28bits O+R+R+R = 20bits

4 4 3 4 3 4 3 4 29

4 4

ADD R3, R1, R2 SW A, R3 ADD R1, R3, R2 SW B, R1 SUB R4, R3, R1 SW D, R4

O+A+R = 28bits

4 20

Total =

STACK
Instruc Push B Push C Add Pop A Push A Push C Add Pop B Push A Push B Sub Pop D Comments
; push B onto stack ; push C onto stack ; top <- B + C ; A= B+ C ; push A onto stack ; push C onto stack ; top <- A + C ; B =A+ C ; push A onto stack ; push B onto stack ; top <- A B ; D=AB

Size of Operand O+A O+A O O+A O+A O+A O O+A O+A O+A O O+A Total =

Code
Bytes

Memory Usage
Bytes

3 3 1 3 3 3 1 3 3 3 1 3 30

4 4 4 4 4 4 4 4 4 36

Example: Reg
Instruction Comments

Mem (Intel
Size of Operand
R = Reg Spec (1 Byte)

ISA-32

)
Memory Usage
Bytes

Code
Bytes

Mov ECX, DWORD PTR [C] ADD EBX, DWORD PTR [B] Mov EDX, EBX Mov EAX,EBX Mov DWORD PTR [A], EAX ADD EAX, ECX Mov EBX,EAX Mov DWROD PTR [B], EBX SUB EDX, EBX Mov DWORD PTR [D], EDX

Mov C to ECX B= B+C Temp Save A = B+C Save A A+C B = A+C Save B D=A- B Save D

O+A+R O+A+R O+R O+R O+A O+A O+A O+A+R O+A O+A+R

6 6 2 2 6 2 2 6 2 6

4 4 0 0 4 0 0 4 0 4

Total =

40

20

Conclusion
Architecture Instruction Memory Accesses (in bytes) 22 21 30 29 40 Data Memory Accesses (In bytes) 28 36 36 20 20 Total

Accumulator Memory/Memory Stack Load/Store Reg-Mem(Intel)

50 57 66 49 60

Pros & Cons


Type Instruction Code # of Clock Encoding Generation Cycles/ Inst. Fixed-length Simple Similar Code Size

Registerregister Registermemory Memorymemory

Large

Variable Length Variablelength

Moderate

Different

Medium

Complex

Large variation

Compact

Source: Louisiana state University, ece

Advantages Disadvantages

Addressing Modes

Addressing Modes

Common memory addressing mode in SPEC89 on VAX architecture


Memory indirect 1% 6% 1% Tex Spice gcc Tex Spice gcc Tex Spice gcc Tex Spice gcc 32% 55% 40% 0% 16% 6% 24% 3% 11% 43%
17%

Scaled

Indirect, Immediate and Displacement Cover 75% to 99%

Register Indirect Immediate

39%

Displacement

10%

20%

30%

40%

50%

Frequency of the addressing mode

Size of Displacement
40%

SPEC2000 FP

Perc enta35% ge of Displ 30% acem ent 25%


20% 15% 10% 5% 0% 0 1 2 3 4 5 6 7 8 9

16-bit displacement covers 75% to 99%

10

11

12

13

14

15

Number of Bits needed for Displacement

Use of Immediate Operand

Immediate Addressing ModeSize of Immediate Operand


45% 40%

FP

16-bit Immediate covers 50% to 80% in SPEC2000

Perc enta 30% ge of Imm25% ediat e 20%


15%

35%

Int
10% 5% 0% 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

Number of Bits needed for Immediate Operand

Popular Instructions
RANK 1 2 3 4 5 6 7 8 9 10 80x86 (SPECint92) Load (Memory Read) Conditional Branch Compare Store Add And Sub Reg-Reg Move Call Return Total: % Total Executed 22% 20% 16% 12% 8% 6% 5% 4% 1% 1% 96%

Instructions for Control Flow




The Measurements of branch and jump behavior are fairly independent of other measurements and applications.

Four types of control flow change:


   

Conditional branches Jumps Procedure calls Procedure returns

Control flow instructions SPEC2000


Floating point average 8%

Call/return
19%

Integer average

Jump
6%

10%

Conditional Branch

82% 75%

25%

50%

75%

100%

Control Flow instructions into three classes

Flow control instructions PC Relative also called Branches




Destination is specified by supplying a displacement that is added to the Program Counter (PC) This type of flow control instructions are called PC-relative. This way code can run independent of where it is loaded; this is called position independence

Branch distances in terms of number of instructions in SPEC

Conditional branch options




Conditional Code (CC) register


  

E.g. 80x86,ARM etc. Tests special bit set by ALU operations Advantage


Sometimes condition is set free CC is extra state. Condition codes constrain the ordering of instructions since they pass information from one instruction to a branch

Disadvantage


Conditional branch options




Conditional Register
 

E.g. Alpha, MIPS Tests arbitrary register with the result of a comparison Advantage


Simple Uses up register

Disadvantage


Conditional branch options




Compare and branch


 

E.g. PA-RISC, VAX Compare is part of the branch. Often compare is limited to subset Advantage


One instruction rather than two for a branch May be too much work per instruction for pipelined execution

Disadvantage


Control


Register Indirect

Implement returns and indirect jumps using a register when target address is not known at compile time. These register indirect jumps are important for other features:
   

Case or switch statements Virtual functions or methods High order functions Dynamically shared libraries

Types of compares in conditional branching


Not Equal 2% 16% 18% Floating point average Integer average Greater than or equal 0% 11% 0% 0% 44% 33% 5% Equal

Greater than

Less than or equal

Less than

34% 35%

10%

20%

30%

40%

50%

Frequency of comparison types in braches

Encoding an instruction set

You might also like