Lect 04
Lect 04
Stack
Accumulator
Register-Memory
Load-Store/ Register-register
Code C=A+B
Virtually every new architecture design after 1980 uses loadstore register architecture!
ANOTHER EXAMPLE
A=B+C B=A+C D=A B Assumptions:
Op Code is 8 bit represented by O, Address is 16-bit represented by A. All registers and data is 32-bit.
(Prob 2.4)
EXAMPLE: Accumulator
Instruc Comments Size of Operand Code
Bytes
Memory Usage
Bytes
accumulator n B accumulator n B + C store B + C in [A] accumulator n A + C store A + C in B negate accumulator accumulator n B + A store A B in D
3 3 3 3 3 1 3 3 22
4 4 4 4 4
4 4 28
7 7 7 21
12 12 12 36
Load-Store
Instruc
LW LW R1, B R2, C
Comments
Memory Usage
Bytes
O+A+R = 28bits O+A+R = 28bits O+R+R+R = 20bits O+A+R = 28bits O+R+R+R = 20bits O+A+R = 28bits O+R+R+R = 20bits
4 4 3 4 3 4 3 4 29
4 4
O+A+R = 28bits
4 20
Total =
STACK
Instruc Push B Push C Add Pop A Push A Push C Add Pop B Push A Push B Sub Pop D Comments
; push B onto stack ; push C onto stack ; top <- B + C ; A= B+ C ; push A onto stack ; push C onto stack ; top <- A + C ; B =A+ C ; push A onto stack ; push B onto stack ; top <- A B ; D=AB
Size of Operand O+A O+A O O+A O+A O+A O O+A O+A O+A O O+A Total =
Code
Bytes
Memory Usage
Bytes
3 3 1 3 3 3 1 3 3 3 1 3 30
4 4 4 4 4 4 4 4 4 36
Example: Reg
Instruction Comments
Mem (Intel
Size of Operand
R = Reg Spec (1 Byte)
ISA-32
)
Memory Usage
Bytes
Code
Bytes
Mov ECX, DWORD PTR [C] ADD EBX, DWORD PTR [B] Mov EDX, EBX Mov EAX,EBX Mov DWORD PTR [A], EAX ADD EAX, ECX Mov EBX,EAX Mov DWROD PTR [B], EBX SUB EDX, EBX Mov DWORD PTR [D], EDX
Mov C to ECX B= B+C Temp Save A = B+C Save A A+C B = A+C Save B D=A- B Save D
O+A+R O+A+R O+R O+R O+A O+A O+A O+A+R O+A O+A+R
6 6 2 2 6 2 2 6 2 6
4 4 0 0 4 0 0 4 0 4
Total =
40
20
Conclusion
Architecture Instruction Memory Accesses (in bytes) 22 21 30 29 40 Data Memory Accesses (In bytes) 28 36 36 20 20 Total
50 57 66 49 60
Large
Moderate
Different
Medium
Complex
Large variation
Compact
Advantages Disadvantages
Addressing Modes
Addressing Modes
Scaled
39%
Displacement
10%
20%
30%
40%
50%
Size of Displacement
40%
SPEC2000 FP
10
11
12
13
14
15
FP
35%
Int
10% 5% 0% 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Popular Instructions
RANK 1 2 3 4 5 6 7 8 9 10 80x86 (SPECint92) Load (Memory Read) Conditional Branch Compare Store Add And Sub Reg-Reg Move Call Return Total: % Total Executed 22% 20% 16% 12% 8% 6% 5% 4% 1% 1% 96%
The Measurements of branch and jump behavior are fairly independent of other measurements and applications.
Call/return
19%
Integer average
Jump
6%
10%
Conditional Branch
82% 75%
25%
50%
75%
100%
Destination is specified by supplying a displacement that is added to the Program Counter (PC) This type of flow control instructions are called PC-relative. This way code can run independent of where it is loaded; this is called position independence
E.g. 80x86,ARM etc. Tests special bit set by ALU operations Advantage
Sometimes condition is set free CC is extra state. Condition codes constrain the ordering of instructions since they pass information from one instruction to a branch
Disadvantage
Conditional Register
E.g. Alpha, MIPS Tests arbitrary register with the result of a comparison Advantage
Disadvantage
E.g. PA-RISC, VAX Compare is part of the branch. Often compare is limited to subset Advantage
One instruction rather than two for a branch May be too much work per instruction for pipelined execution
Disadvantage
Control
Register Indirect
Implement returns and indirect jumps using a register when target address is not known at compile time. These register indirect jumps are important for other features:
Case or switch statements Virtual functions or methods High order functions Dynamically shared libraries
Greater than
Less than
34% 35%
10%
20%
30%
40%
50%