Clock domain crossing (CDC)

By vinod kumar
 CDC
• What is cdc?
• A clock domain crossing occurs whenever data is transferred from a flop driven by
one clock to a flop driven by another clock.
•  signal A is launched by the C1 clock domain
and needs to be captured properly by
the C2 clock domain.

• Depending on the relationship between the two clocks, there could be different
types of problems in transferring data from the source clock to the destination
clock
Clock Domain Crossing Issues
This section describes three main issues which can possibly occur whenever there is a
clock domain crossing. 
A. Metastability
Problem. If the transition on signal A happens very close to the active edge of clock
C2, it could lead to setup or hold violation at the destination flop "FB". As a result,
the output signal B may oscillate for an indefinite amount of time. Thus the output is
unstable and may or
may not settle down to some stable value
before the next clock edge of C2 arrives.
This phenomenon is known as metastability
and the flop "FB" is said to have entered
a metastable state.
see Figure  If the input signal A transitions very close to the posedge of clock C2, the
output of the destination flop can be metastable. As a result it can be unstable and
may finally settle to 1 or 0 as depicted by signals B1 and B2.

• Metastability in turn can have the following consequences from a design

perspective:
• If the unstable data is fed to several other places in the design, it may lead to a
high current flow and even chip burnout in the worst case.
• Different fan-out cones may read different values of the signal, and may cause the
design to enter into an unknown functional state, leading to functional issues in the
design.
• The destination domain output may settle down to the new value or may return to
the old value. However, the propagation delay could be high leading to timing
issues.
Solution.
Metastability problems can be avoided by adding special structures known as
synchronizers in the destination domain. The synchronizers allow sufficient time for
the oscillations to settle down and ensure that a stable output is obtained in the
destination domain. A commonly used synchronizer is a multi-flop synchronizer as
shown in Figure 3.

This structure is mainly used for single and multi-bit control signals and single bit
data signals in the design.
Other types of synchronization schemes are required for multi-bit data signals such as
MUX recirculation, handshake, and FIFO.
B. Data Loss:Problem.
Whenever a new source data is generated, it may not be captured by the destination
domain in the very first cycle of the destination clock because of metastability. As long
as each transition on the source signal is captured in the destination domain, data is not
lost. In order to ensure this, the source data should remain stable for some minimum
time, so that the setup and hold time requirements are met with respect to at least one
active edge of destination clock.

Effect of metastability on data capture.

If the active clock edges of C1 and C2 arrive close together, the first clock edge of C2,
which comes after the transition on source data A, is not able to capture it. The data
finally gets captured by the second edge of clock C2 
However, if there is sufficient time between the transition on data A and the active
edge of clock C2, the data is captured in the destination domain in the first cycle of C2.
• For example:
• Assume that the source clock C1 is twice as fast as the destination clock C2 and
there is no phase difference between the two clocks. Further assume that the
input data sequence "A" generated on the positive edge of clock C1 is "00110011".
The data B captured on the positive edge of clock C2 will be "0101". Here, since all
the transitions on signal A are captured by B, the data is not lost.

• Fig-1 fig-2

• However, if the input sequence is "00101111", then the output in the destination
domain will be "0011". Here the third data value in the input sequence which is "1"
is lost as shown in Figure 2.
• Solution.
• In order to prevent data loss, the data should be held constant in the source
domain long enough to be properly captured in the destination domain. In other
words, after every transition on source data, at least one destination clock edge
should arrive where there is no setup or hold violation so that the source data is
captured properly in the destination domain. There are several techniques to
ensure this.

For example,
a finite state machine (FSM) can be used to generate source data at a rate, such
that it is stable for at least 1 complete cycle of the destination clock. This can be
generally useful for synchronous clocks when their frequencies are known. For
asynchronous clock domain crossings, techniques like handshake and FIFO are more
suitable.
• C.DataIncoherency

Problem. As seen in the previous section whenever new data is generated in the
source clock domain, it may take 1 or more destination clock cycles to capture it,
depending on the arrival time of active clock edges.
Consider a case where multiple signals are being transferred from one clock domain
to another and each signal is synchronized separately using a multi-flop
synchronizer.
If all the signals are changing simultaneously and the source and destination clock
edges arrive close together, some of the signals may get captured in the destination
domain in the first clock cycle while some others may be captured in the second
clock cycle by virtue of metastability. This may result in an invalid combination of
values on the signals at the destination side. Data coherency is said to have been
lost in such a case.
• If these signals are together controlling some function of the design, then this
invalid state may lead to functional errors.
• C.DataIncoherency

For example: Assume that "00" and "11" are two valid values for a signal X[0:1] generated
by clock C1. As shown in Figure 7, initially there is a transition from 1->0 on both the bits
of X. Both the transitions get captured by clock C2 in the first cycle itself. Hence the
signal Y[0:1] becomes "00".

Next, there is a transition from 0->1 on both the bits of signal X. Here the rising edge of
clock C2 comes close to the transition on signal X. While the transition on X[0] is captured
in the first clock cycle, the transition on X[1] gets captured in second clock cycle of C2.
This results in an intermediate value of "10" on Y[0:1] which is an invalid state. Data
coherency is lost in this case.
• C.DataIncoherency
• Solution. In the above example, the problem results because all the bits are not
changing to a new state in the same cycle of destination clock. If all the bits
either retain their original value or change to the new value in the same cycle,
then the design either remains in the original state or goes to a correct new state.
• Now, if the circuit is designed in such a way that while changing the design from
one state to another, only one bit change is required, then either that bit would
change to a new value or would retain the original value. Since all the other bits
have the same value in both the states, the complete bus will either change to the
new value or retain the original value in this case.
• This in turn implies that if the bus is Gray-encoded, the problem would get
resolved and an invalid state would never be obtained.
• However, this is applicable only for control busses as it may not be possible to
Gray-encode the data busses. In such cases, other techniques like handshake, FIFO
and MUX recirculation can be used to generate a common control logic to transfer
data correctly.
• C.DataIncoherency
• The MUX recirculation technique is shown in Figure 

• Here, a control signal EN, generated in the source domain is synchronized in the
destination domain using a multi-flop synchronizer. The synchronized control signal
EN_Sync drives the select pin of the muxes, thereby controlling the data transfer for all
bits of the bus A. In this way, individual bits of the bus are not synchronized separately,
and hence there is no data incoherency. However, it is important to ensure that when
the control signal is active, the source domain data A[0:1] should be held constant.