ELEC 2200-002

Digital Logic Circuits

Fall 2015
Binary Arithmetic (Chapter 1)
Vishwani D. Agrawal
James J. Danaher Professor
Department of Electrical and Computer Engineering
Auburn University, Auburn, AL 36849
http://www.eng.auburn.edu/~vagrawal
[email protected]

Fall 2015, Aug 19 . . . ELEC2200-002 Lecture 2 1

 Digital Systems

Bin n
Ari ar a
le a
thm y o
eti Bo ebr
c Alg
DIGITAL
CIRCUITS
g Se
i n mi
i t ch y Te con
Sw heor ch du
no cto
T l og r
y

Fall 2015, Aug 19 . . . ELEC2200-002 Lecture 2 2

 Why Binary Arithmetic?

3+5 =8

0011 + = 1000
0101

Fall 2015, Aug 19 . . . ELEC2200-002 Lecture 2 3

 Why Binary Arithmetic?
Hardware can only deal with binary digits,
0 and 1.
Must represent all numbers, integers or
floating point, positive or negative, by
binary digits, called bits.
Can devise electronic circuits to perform
arithmetic operations: add, subtract,
multiply and divide, on binary numbers.

Fall 2015, Aug 19 . . . ELEC2200-002 Lecture 2 4

 Positive Integers
Decimal system: made of 10 digits, {0,1,2, . . . , 9}
41 = 4×101 + 1×100
255 = 2×102 + 5×101 + 5×100
Binary system: made of two digits, {0,1}
00101001 = 0×27 + 0×26 + 1×25 + 0×24 +1×23
+ 0×22 + 0×21 + 1×20
= 32 + 8 +1 = 41
11111111 = 255, largest number with 8 binary
digits, 28-1

Fall 2015, Aug 19 . . . ELEC2200-002 Lecture 2 5

 Base or Radix
For decimal system, 10 is called the base or
radix.
Decimal 41 is also written as 4110 or 41ten
Base (radix) for binary system is 2.
Thus, 41ten = 1010012 or 101001two
Also, 111ten = 1101111two
and 111two = 7ten
What about negative numbers?
Fall 2015, Aug 19 . . . ELEC2200-002 Lecture 2 6
Signed Magnitude – What Not to Do

Use fixed length binary representation

Use left-most bit (called most significant bit
or MSB) for sign:
0 for positive
1 for negative
Example: +18ten = 00010010two
–18ten = 10010010two

Fall 2015, Aug 19 . . . ELEC2200-002 Lecture 2 7

 Difficulties with Signed Magnitude
Sign and magnitude bits should be differently treated
in arithmetic operations.
Addition and subtraction require different logic
circuits.
Overflow is difficult to detect.
“Zero” has two representations:
+ 0ten = 00000000two
– 0ten = 10000000two
Signed-integers are not used in modern
computers.

Fall 2015, Aug 19 . . . ELEC2200-002 Lecture 2 8

 Problems with Finite Math
Finite size of representation:
– Digital circuit cannot be arbitrarily large.
– Overflow detection – easy to determine when
the number becomes too large.
0000 0100 1000 1100 10000 10100
Infinite -∞ -4 0 4 8 12 16 20 ∞
universe
of integers
4-bit numbers
Represent negative numbers:
– Unique representation of 0.
Fall 2015, Aug 19 . . . ELEC2200-002 Lecture 2 9
 4-bit Universe

0000 0000
1111 0001 1111 0001
16/0 15 0
Modulo-16 15
-0
(4-bit) 1100 12 4 0100 1100 12 -3 4 0100
universe
-7 7
8 7 8
0111
1000 1000

Only 16 integers: 0 through 15, or – 7 through 7

Fall 2015, Aug 19 . . . ELEC2200-002 Lecture 2 10

 One Way to Divide Universe
1’s Complement Numbers
Binary number
0000 Decimal
1111
15 0
0001 magnitude Positive Negative
-0
1100 12 -3 4 0100 0 0000 1111
-7 1 0001 1110
7
8
0111 2 0010 1101
1000
3 0011 1100

Negation rule: invert bits. 4 0100 1011

5 0101 1010
Problem: 0 ≠ – 0 6 0110 1001
7 0111 1000
Fall 2015, Aug 19 . . . ELEC2200-002 Lecture 2 11
 Another Way to Divide Universe
2’s Complement Numbers
Binary number
Decimal
0000 magnitude Positive Negative
1111 0001
15 0
-1
0 0000
1100 12 -4 4 0100
1 0001 1111
Subtract 1 -8 7 2 0010 1110
8
on this side 0111
1000 3 0011 1101

Negation rule: invert bits 4 0100 1100

and add 1 5 0101 1011
6 0110 1010
7 0111 1001
Fall 2015, Aug 19 . . . 8
ELEC2200-002 Lecture 2 1000 12
 Integers With Sign – Two Ways
Use fixed-length representation, but no
explicit sign bit:
– 1’s complement: To form a negative number,
complement each bit in the given number.
– 2’s complement: To form a negative number,
start with the given number, subtract one, and
then complement each bit, or
first complement each bit, and then add 1.
2’s complement is the preferred
representation.

Fall 2015, Aug 19 . . . ELEC2200-002 Lecture 2 13

 2’s-Complement Integers
Why not 1’s-complement? Don’t like two zeros.
Negation rule:
Subtract 1 and then invert bits, or
Invert bits and add 1
Some properties:
Only one representation for 0
Exactly as many positive numbers as negative numbers
Slight asymmetry – there is one negative number with no
positive counterpart

Fall 2015, Aug 19 . . . ELEC2200-002 Lecture 2 14

 General Method for Binary
Integers with Sign
Select number (n) of bits in representation.
Partition 2n integers into two sets:
00…0 through 01…1 are 2n/2 positive integers.
10…0 through 11…1 are 2n/2 negative integers.
Negation rule transforms negative to positive, and vice-
versa:
Signed magnitude: invert MSB (most significant bit)
1’s complement: Subtract from 2n – 1 or 1…1 (same as
“inverting all bits”)
2’s complement: Subtract from 2n or 10…0 (same as 1’s
complement + 1)

Fall 2015, Aug 19 . . . ELEC2200-002 Lecture 2 15

 Three Systems (n = 4)
10000
0000 0000 0000
1111 1111 1111
0 0010 0 0
–7 2 –0
–1

6 –6 6
–2 7 7 7
–0 –5 –7 1010 –8
1010 0111 1010 0111 0111
1000 1000 1000

1010 = – 2 1010 = – 5 1010 = – 6

Signed magnitude 1’s complement integers 2’s complement integers

Fall 2015, Aug 19 . . . ELEC2200-002 Lecture 2 16

 Three Representations
Sign-magnitude 1’s complement 2’s complement

000 = +0 000 = +0 000 = +0

001 = +1 001 = +1 001 = +1
010 = +2 010 = +2 010 = +2
011 = +3 011 = +3 011 = +3
100 = - 0 100 = - 3 100 = - 4
101 = - 1 101 = - 2 101 = - 3
110 = - 2 110 = - 1 110 = - 2
111 = - 3 111 = - 0 111 = - 1

(Preferred)

Fall 2015, Aug 19 . . . ELEC2200-002 Lecture 2 17

2’s Complement Numbers (n = 3)
0

subtraction
000 addition

-1 111 001 +1

Pos
Neg

itiv
ativ

e
010 +2
e
-2 110

num
num

ber
ber

s
s

-3 101 011 +3

100 rfl ow Negation

Ove
-4
Fall 2015, Aug 19 . . . ELEC2200-002 Lecture 2 18
 2’s Complement n-bit Numbers
Range: – 2n –1 through 2n –1 – 1
Unique zero: 00000000 . . . . . 0
Negation rule: see slide 11 or 13.
Expansion of bit length: stretch the left-most bit all the
way, e.g., 11111101 is still 101 or – 3. Also, 00000011
is same as 011 or 3.
Most significant bit (MSB) indicates sign.
Overflow rule: If two numbers with the same sign bit
(both positive or both negative) are added, the overflow
occurs if and only if the result has the opposite sign.
Subtraction rule: for A – B, add – B and A.

Fall 2015, Aug 19 . . . ELEC2200-002 Lecture 2 19

 Summary
For a given number (n) of digits we have a
finite set of integers. For example, there are
103 = 1,000 decimal integers and 23 = 8 binary
integers in 3-digit representations.
We divide the finite set of integers [0, rn – 1],
where radix r = 10 or 2, into two equal parts
representing positive and negative numbers.
Positive and negative numbers of equal
magnitudes are complements of each other: x
+ complement (x) = 0.
Fall 2015, Aug 19 . . . ELEC2200-002 Lecture 2 20
Summary: Defining Complement
Decimal integers:
10’s complement: – x = Complement (x) = 10 n – x
9’s complement: – x = Complement (x) = 10 n – 1 – x
– For 9’s complement, subtract each digit from 9
– For 10’s complement, add 1 to 9’s complement
Binary integers:
2’s complement: – x = Complement (x) = 2 n – x
1’s complement: – x = Complement (x) = 2 n – 1 – x
– For 1’s complement, subtract each digit from 1
– For 2’s complement, add 1 to 1’s complement
Fall 2015, Aug 19 . . . ELEC2200-002 Lecture 2 21
 Understanding Complement
Complement means “something that
completes”:
e.g., X + complement (X) = “Whole”.
Complement also means “opposite”,
e.g., complementary colors are placed
opposite in the primary color chart.
Complementary numbers are like electric
charges. Positive and negative charges
of equal magnitudes annihilate each
other.

Fall 2015, Aug 19 . . . ELEC2200-002 Lecture 2 22

 2’s-Complement Numbers
000 001 010 011 100 101
Infinite -∞ . . . -1 0 1 2 3 4 5... ∞
universe
of integers
Finite
1000 1000
Universe
999 000 111 000
Finite of 3-bit
001 001
Universe of binary
3-digit numbers
Decimal
numbers
499 011
501 101
500 100
Fall 2015, Aug 19 . . . ELEC2200-002 Lecture 2 23
 Examples of Complements
Decimal integers (r = 10, n = 3):
10’s complement: – 50 = Compl (50) = 103 – 50 = 950;
50 + 950 = 1,000 = 0 (in 3 digit representation)
9’s complement: – 50 = Compl (50) = 10n – 1 – 50 =
949; 50 + 949 = 999 = – 0 (in 9’s complement rep.)
Binary integers (r = 2, n = 4):
2’s complement: – 5 = Complement (5) = 24 – 5 = 1110
or 1011; 5 + 11 = 16 = 0 (in 4-bit representation)
1’s complement: – 5 = Complement (5) = 24 – 1 – 5 =
1010 or 1010; 5 + 10 = 15 = – 0 (in 1’s complement
representation)

Fall 2015, Aug 19 . . . ELEC2200-002 Lecture 2 24

 2’s-Complement to Decimal
Conversion
n-2
bn-1 bn-2 . . . b1 b0 = – 2n-1bn-1 + Σ 2i bi
i=0

8-bit conversion box

-128 64 32 16 8 4 2 1

Example -128 64 32 16 8 4 2 1
1 1 1 1 1 1 0 1
– 128 + 64 + 32 + 16 + 8 + 4 + 1 = – 128 + 125 = – 3

Fall 2015, Aug 19 . . . ELEC2200-002 Lecture 2 25

 For More on 2’s-Complement

Donald E. Knuth (1938 - ) Abu Abd-Allah ibn Musa

al’Khwarizmi (~780 – 850)
Chapter 4 in D. E. Knuth, The Art of Computer Programming:
Seminumerical Algorithms, Volume II, Second Edition, Addison-
Wesley, 1981.
A. al’Khwarizmi, Hisab al-jabr w’al-muqabala, 830.
Read: A two part interview with D. E. Knuth, Communications
of the ACM (CACM), vol. 51, no. 7, pp. 35-39 (July), and no. 8,
pp. 31-35 (August), 2008.
Fall 2015, Aug 19 . . . ELEC2200-002 Lecture 2 26
 Addition
Adding bits:
0+0= 0
0+1= 1
1+0= 1
carry
1 + 1 = (1) 0
Adding integers:
1 1 0
0 0 0...... 0 1 1 1 two = 7ten
+ 0 0 0...... 0 1 1 0 two = 6ten
= 0 0 0 . . . . . . 1 (1)1 (1)0 (0)1 two = 13ten
Fall 2015, Aug 19 . . . ELEC2200-002 Lecture 2 27
 Subtraction
Direct subtraction

0 0 0......0 1 1 1 two = 7ten

– 0 0 0......0 1 1 0 two = 6ten
= 0 0 0...... 0 0 0 1two = 1ten
Two’s complement subtraction by adding
1 1 1......1 1 0
0 0 0......0 1 1 1 two = 7ten
+ 1 1 1......1 0 1 0 two = – 6ten
= 0 0 0 . . . . . . 0 (1) 0 (1) 0 (0)1 two = 1ten

Fall 2015, Aug 19 . . . ELEC2200-002 Lecture 2 28

 Overflow: An Error
Examples: Addition of 3-bit integers (range - 4 to +3)
000
-2-3 = -5 110 = -2
111 0 001
+ 101 = -3 1
-1
= 1011 = 3 (error) – +
2 010
110 -2
3+2 = 5 011 = 3
-3 3
010 = 2 101 -4 011
= 101 = -3 (error) 100 Overflow
crossing

Overflow rule: If two numbers with the same sign bit

(both positive or both negative) are added, the overflow
occurs if and only if the result has the opposite sign.
Fall 2015, Aug 19 . . . ELEC2200-002 Lecture 2 29
 Overflow and Finite Universe
Decrease Increase
Infinite -∞ . . .1111 0000 0001 0010 0011 0100 ∞
universe 0101 . . .
of integers
No overflow
0000
1111 0001
1110 0010 Finite
1101 Decrease Universe

Increase
0011 of 4-bit
1100
0100 binary
1011 integers
0101
1010 0110
0111
1001 1000
Forbidden fence
Fall 2015, Aug 19 . . . ELEC2200-002 Lecture 2 30
 Adding Two Bits

s=a+b
a b
Decimal Binary
0 0 0 00
0 1 1 01
1 0 1 01
1 1 2 10

CARRY
SUM

Fall 2015, Aug 19 . . . ELEC2200-002 Lecture 2 31

 Half-Adder Adds two Bits
“half” because it has no carry input
Adding two bits:
a b a+b
0 0 00 AND carry
0 1 01
HA
1 0 01 a
XOR sum
1 1 10 b

carry sum

Fall 2015, Aug 19 . . . ELEC2200-002 Lecture 2 32

 Full Adder: Include Carry Input
s=a+b+c
a b c
Decimal value Binary value
0 0 0 0 00
0 0 1 1 01
0 1 0 1 01
0 1 1 2 10
1 0 0 1 01
1 0 1 2 10
1 1 0 2 10
1 1 1 3 11
CARRY SUM
Fall 2015, Aug 19 . . . ELEC2200-002 Lecture 2 33
 Full-Adder Adds Three Bits

OR carry
AND
AND
HA
HA
a XOR sum
XOR
b
c
FA

Fall 2015, Aug 19 . . . ELEC2200-002 Lecture 2 34

 32-bit Ripple-Carry Adder
c32
c32 c31 . . . c2 c1 0 a31 (discard)
a31 . . . a2 a1 a0 b31 FA31
+ b31 . . . b2 b1 b0 s31
c31
s31 . . . s2 s1 s0

a2
b2 FA2 s2
a1
b1 FA1 c2 s1
a0
b0 FA0 c1 s0
c0 = 0

Fall 2015, Aug 19 . . . ELEC2200-002 Lecture 2 35

 How Fast is Ripple-Carry Adder?
Longest delay path (critical path) runs from
(a0, b0) to sum31.
Suppose delay of full-adder is 100ps.
Critical path delay = 3,200ps
Clock rate cannot be higher than
1/(3,200×10 –12) Hz = 312MHz.
Must use more efficient ways to handle
carry.

Fall 2015, Aug 19 . . . ELEC2200-002 Lecture 2 36

 Speeding Up the Adder
a0-a15 16-bit
ripple s0-s15
b0-b15
carry
c0 = 0 adder
a16-a31 16-bit
ripple 0
b16-b31

Multiplexer
carry
0 adder s16-s31
a16-a31 16-bit
ripple 1
b16-b31
carry This is a carry-select adder
1 adder
Fall 2015, Aug 19 . . . ELEC2200-002 Lecture 2 37
 Fast Adders
In general, any output of a 32-bit adder can
be evaluated as a logic expression in terms
of all 65 inputs.
Number of levels of logic can be reduced to
log2N for N-bit adder. Ripple-carry has N
levels.
More gates are needed, about log2N times
that of ripple-carry design.
Fastest design is known as carry lookahead
adder.
Fall 2015, Aug 19 . . . ELEC2200-002 Lecture 2 38
 N-bit Adder Design Options
Type of adder Time complexity Space complexity
(delay) (size)
Ripple-carry O(N) O(N)

Carry-lookahead O(log2N) O(N log2N)

Carry-skip O(√N) O(N)

Carry-select O(√N) O(N)

Reference: J. L. Hennessy and D. A. Patterson, Computer Architecture:

A Quantitative Approach, Second Edition, San Francisco, California,
1990, page A-46.

Fall 2015, Aug 19 . . . ELEC2200-002 Lecture 2 39

 Binary Multiplication (Unsigned)
1 0 0 0 two = 8ten multiplicand
1 0 0 1 two = 9ten multiplier
____________

1000
0000 partial products
0000
1000 Basic algorithm: For n = 1, 32,
____________ only If nth bit of multiplier is 1,
1 0 0 1 0 0 0two = 72ten then add multiplicand × 2 n –1
to product

Fall 2015, Aug 19 . . . ELEC2200-002 Lecture 2 40

 Digital Circuits for Multiplication
Need:
Three registers for multiplicand, multiplier and product.
Adder or arithmetic logic unit (ALU).
What is a register
A memory device – unit cell stores one bit.
A 32-bit register has 32 storage cells. It can store a
32-bit integer.
1 bit right shift divides integer by 2
bit 32 bit 0

1 bit left shift multiplies integer by 2

Fall 2015, Aug 19 . . . ELEC2200-002 Lecture 2 41

 Multiplication Flowchart
Start Initialize product register to 0 Partial product number, n = 1

Add multiplicand to 1 LSB 0

product and place result of multiplier
in product register ?

Left shift multiplicand register 1 bit

N = 32 Right shift multiplier register 1 bit

n = 32 n < 32
Done n=? n=n+1

Fall 2015, Aug 19 . . . ELEC2200-002 Lecture 2 42

 Serial Multiplication
shift left shift right
Shift l/r
N = 32 Multiplicand (expanded 64-bits) 32-bit multiplier

64

after add

LSB
64 LSB = 0

add Test LSB

64-bit ALU
LSB N = 32 times

after add
=1
64
64-bit product register, initially 0 3 operations per bit:
write shift right
shift left
add
Need 64-bit ALU
Fall 2015, Aug 19 . . . ELEC2200-002 Lecture 2 43
 Serial Multiplication (Improved)
Multiplicand 2 operations per bit:
N = 32
shift right
32 add
32 32-bit ALU

(1) add 1
Test LSB
32-bit ALU
32 times
LSB
32
1 ir te
) w
(2 1 or 0
64-bit product register
(3) shift right

00000 . . . 00000 32-bit multiplier Initialized product register

Fall 2015, Aug 19 . . . ELEC2200-002 Lecture 2 44

 Example: 0010two× 0011two
0010two × 0011two = 0110two, i.e., 2ten × 3ten = 6ten

Iteration Step Multiplicand Product

0 Initial values 0010 0000 0011
1 LSB =1 → Prod = Prod + Mcand 0010 0010 0011
Right shift product 0010 0001 0001
2 LSB =1 → Prod = Prod + Mcand 0010 0011 0001
Right shift product 0010 0001 1000
3 LSB = 0 → no operation 0010 0001 1000
Right shift product 0010 0000 1100
4 LSB = 0 → no operation 0010 0000 1100
Right shift product 0010 0000 0110

Fall 2015, Aug 19 . . . ELEC2200-002 Lecture 2 45

 Multiplying with Signs
Convert numbers to magnitudes.
Multiply the two magnitudes through 32
iterations.
Negate the result if the signs of the multiplicand
and multiplier differed.
Alternatively, the previous algorithm will work
with some modifications. See B. Parhami,
Computer Architecture, New York: Oxford
University Press, 2005, pp. 199-200.

Fall 2015, Aug 19 . . . ELEC2200-002 Lecture 2 46

 Alternative Method with Signs
In the improved method:
Use 2N + 1 bit product register
Use N + 1 bit multiplicand register
Use N + 1 bit adder
Proceed as in the improved method,
except –
In the last (Nth) iteration, if LSB = 1,
subtract multiplicand instead of adding.

Fall 2015, Aug 19 . . . ELEC2200-002 Lecture 2 47

 Example 1: 1010two× 0011two
1010two × 0011two = 101110two, i.e., – 6ten × 3ten = – 18ten

Iteration Step Multiplicand Product

0 Initial values 11010 00000 0011
1 LSB = 1 → Prod = Prod + Mcand 11010 11010 0011
Right shift product 11010 11101 0001
2 LSB = 1 → Prod = Prod + Mcand 11010 10111 0001
Right shift product 11010 11011 1000
3 LSB = 0 → no operation 11010 11011 1000
Right shift product 11010 11101 1100
4 LSB = 0 → no operation 11010 11101 1100
Right shift product 11010 11110 1110

Fall 2015, Aug 19 . . . ELEC2200-002 Lecture 2 48

 Example 2: 1010two× 1011two
1010two × 1011two = 011110two, i.e., – 6ten × ( – 5ten) = 30ten

Iteration Step Multiplicand Product

0 Initial values 11010 00000 1011
1 LSB =1 → Prod = Prod + Mcand 11010 11010 1011
Right shift product 11010 11101 0101
2 LSB =1 → Prod = Prod + Mcand 11010 10111 0101
Right shift product 11010 11011 1010
3 LSB = 0 → no operation 11010 11011 1010
Right shift product 11010 11101 1101
4 LSB =1 → Prod = Prod – Mcand* 00110 00011 1101
Right shift product 11010 00001 1110
*Last iteration with a negative multiplier in 2’s complement.
Fall 2015, Aug 19 . . . ELEC2200-002 Lecture 2 49
 Adding Partial Products
y3 y2 y1 y0 multiplicand
x3 x2 x1 x0 multiplier
________________________
x0y3 x0y2 x0y1 x0y0 four
carry← x1y3 x1y2 x1y1 x1y0 partial
carry← x2y3 x2y2 x2y1 x2y0 products
carry← x3y3 x3y2 x3y1 x3y0 to be
__________________________________________________ summed
p7 p6 p5 p4 p3 p2 p1 p0

Requires three 4-bit additions.

Slow.

Fall 2015, Aug 19 . . . ELEC2200-002 Lecture 2 50

 Array Multiplier: Carry Forward
y3 y2 y1 y0 multiplicand
x3 x2 x1 x0 multiplier
________________________
x0y3 x0y2 x0y1 x0y0 four
x1y3 x1y2 x1y1 x1y0 partial
x2y3 x2y2 x2y1 x2y0 products
x3y3 x3y2 x3y1 x3y0 to be
__________________________________________________ summed
p7 p6 p5 p4 p3 p2 p1 p0

Note: Carry is added to the next partial product (carry-save addition).

Adding the carry from the final stage needs an extra (ripple-carry
stage. These additions are faster but we need four stages.

Fall 2015, Aug 19 . . . ELEC2200-002 Lecture 2 51

 Basic Building Blocks
Two-input AND ith bit of
kth partial
Full-adder yi xk
product
sum bit
from (k-1)th carry bits
yi x0 from (k-1)th
sum
sum

Full
adder Slide 24
p0i = x0yi carry bits
to (k+1)th sum bit
0 partial product
th
sum to (k+1)th
sum
Fall 2015, Aug 19 . . . ELEC2200-002 Lecture 2 52
 y3 y2 y1 y0
Array Multiplier x0
ppk
yj
xi 0
x1
ci 0 0 0 0

FA 0
x2
co
ppk+1
0
x3
Critical path
0

0
FA FA FA FA
p7 p6 p5 p4 p3 p2 p1 p0
Fall 2015, Aug 19 . . . ELEC2200-002 Lecture 2 53
 Types of Array Multipliers
Baugh-Wooley Algorithm: Signed product
by two’s complement addition or
subtraction according to the MSB’s.
Booth multiplier algorithm
Tree multipliers
Reference: N. H. E. Weste and D. Harris,
CMOS VLSI Design, A Circuits and
Systems Perspective, Third Edition,
Boston: Addison-Wesley, 2005.
Fall 2015, Aug 19 . . . ELEC2200-002 Lecture 2 54
 Binary Division (Unsigned)

13 Quotient 00001101
11/147 Divisor / Dividend 1 0 1 1 / 1 0 0 1 0 0 1 1
11 1011
37 Partial remainder 001110
33 1011
4 Remainder 001111
1011
100

Fall 2015, Aug 19 . . . ELEC2200-002 Lecture 2 55

 4-bit Binary Division (Unsigned)
0001
Dividend: 6 = 0110 0000110

Iteration 2 Iteration 1
Divisor: 4 = 0100 1100
– 4 = 1100 1100 negative → quotient bit 0
0100 → restore remainder
6
─ = 1, remainder 2 0000110
4 1100
1101 negative → quotient bit 0
0100 → restore remainder
000110
Iteration 4 Iteration 3

1100
1111 negative → quotient bit 0
0100 → restore remainder
00110
1100
0010 positive → quotient bit 1

Fall 2015, Aug 19 . . . ELEC2200-002 Lecture 2 56

 32-bit Binary Division Flowchart
Start $R = 0, $M = Divisor, $Q = Dividend, count = n

$R (33 b) | $Q (32 b)
Shift 1-bit left $R, $Q
$R and $M have
one extra sign bit
$R ← $R – $M beyond 32 bits.

No Yes $Q0=0
$Q0 = 1 $R < 0?
$R ← $R + $M
Restore $R
count = count – 1 (remainder)

No Yes Done
count = 0? $Q = Quotient
$R = Remainder
Fall 2015, Aug 19 . . . ELEC2200-002 Lecture 2 57
count 4-bit Example: 6/4 = 1, Remainder 2
Actions n $R, $Q $M = Divisor
4 Initialize 4 00000|0110 00100
Shift left $R, $Q 4 00000|1100 00100
Add – $M (11100) to $R 4 11100|1100 00100
Restore, add $M (00100) to $R 3 00000|1100 00100
3 Shift left $R, $Q 3 00001|1000 00100
Add – $M (11100) to $R 3 11101|1000 00100
Restore, add $M (00100) to $R 2 00001|1000 00100
2 Shift left $R, $Q 2 00011|0000 00100
Add – $M (11100) to $R 2 11111|0000 00100
Restore, add $M (00100) to $R 1 00011|0000 00100
1 Shift left $R, $Q 1 00110|0000 00100
Add – $M (11100) to $R 1 00010|0000 00100
Set LSB of $Q = 1 0 00010|0001 00100
0 Remainder | Quotient
Fall 2015, Aug 19 . . . ELEC2200-002 Lecture 2 58
 Division
33-bit $M (Divisor)

33 Step 2: Subtract $R ← $R – $M
33

33-bit ALU

Initialize 33 Step 1: 1- bit left shift $R and $Q 32 times

$R←0
33-bit $R (Remainder) 32-bit $Q (Dividend)

Step 3: If sign-bit ($R) = 0, set Q0 = 1

If sign-bit ($R) = 1, set Q0 = 0 and restore $R
V. C. Hamacher, Z. G. Vranesic and S. G. Zaky, Computer Organization, Fourth Edition,
New York: McGraw-Hill, 1996.

Fall 2015, Aug 19 . . . ELEC2200-002 Lecture 2 59

 Example: 8/3 = 2, Remainder = 2
Initialize $R = 00000 $Q = 1 0 0 0 $M = 00011
Iteration 1

Step 1, L-shift $R = 00001 $Q = 0000

Step 2, Add – $M = 11101
$R = 11110
Step 3, Set Q0 $Q = 0000
Restore + $M = 00011
$R = 00001

Step 1, L-shift $R = 00010 $Q = 0 0 0 0 $M = 00011

Iteration 2

Step 2, Add – $M = 1 1 1 0 1
$R = 1 1 1 1 1
Step 3, Set Q0 $Q = 0000
Restore + $M = 0 0 0 1 1
$R = 0 0 0 1 0

Fall 2015, Aug 19 . . . ELEC2200-002 Lecture 2 60

 Example: 8/3 = 2 (Remainder = 2)
(Continued)
$R = 00010 $Q = 0 0 0 0 $M = 00011
Iteration 3

Step 1, L-shift $R = 00100 $Q = 0 0 0 0 $M = 00011

Step 2, Add – $M =11101
$R = 00001
Step 3, Set Q0 $Q = 0001

Step 1, L-shift $R,Q = 0 0 0 1 0 $Q = 0 0 1 0 $M = 00011

Step 2, Add – $M = 1 1 1 0 1
Iteration 4

$R = 1 1 1 1 1
Step 3, Set Q0 $Q = 0 0 1 0 Final quotient
Restore + $M = 0 0 0 1 1
$R Remainder
= 00010
Note “Restore $R” in Steps 1, 2 and 4. This method is known as
the RESTORING DIVISION. An improved method, NON-
RESTORING
DIVISION, is possible (see Hamacher, et al.)
Fall 2015, Aug 19 . . . ELEC2200-002 Lecture 2 61
 Non-Restoring Division
Avoid unnecessary addition (restoration).
How it works?
– Initially $R contains dividend ✕ 2 – n for n-bit numbers. Example (n = 8):

– In some iteration after left shift, suppose $R = x and divisor is y

– Subtract divisor, $R = x – y
– Restore: If $R is negative, add y, $R = x
–
Dividend 00101101
Next step: Left shift, $R = 2x+b, and subtract y, $R = 2x – y + b

$R, $Q 00000000 00101101

Fall 2015, Aug 19 . . . ELEC2200-002 Lecture 2 62

 How It Works: Last two Steps
– Suppose we do not restore and go to next step:
– Left shift, $R = 2(x – y) + b = 2x – 2y + b, and add y, then $R = 2x
– 2y + y + b = 2x – y + b (same result as with restoration)

Non-restoring division
Initialize and start iterations same as in restoring
division by subtracting divisor
In any iteration after left shift and subtraction/addition
– If $R is positive, subtract divisor (y) in next iteration
– If $R is negative, add divisor (y) in next iteration
After final iteration, if $R is negative then restore it by
adding divisor (y)

Fall 2015, Aug 19 . . . ELEC2200-002 Lecture 2 63

 Example: 8/3 = 2, Remainder = 2
Non-Restoring Division
Initialize $R = 00000 $Q = 1 0 0 0 $M = 00011
Iteration 1

Step 1, L-shift $R = 0 0 0 0 1 $Q = 0000

Step 2, Add – $M = 1 1 1 0 1
$R = 1 1 1 1 0 $Q = 0000
Step 3, Set Q0

Step 1, L-shift $R = 11100 $Q = 0 0 0 0 $M = 00011

Step 2, Add + $M = 0 0 0 1 1
$R = 1 1 1 1 1 $Q = 0000
Iteration 2

Step 3, Set Q0

Add + $M in next iteration

Fall 2015, Aug 19 . . . ELEC2200-002 Lecture 2 64

 Example: 8/3 = 2 (Remainder = 2)
Non-Restoring Division (Continued)
$R = 11111 $Q = 0 0 0 0 $M = 00011
Iteration 3

Step 1, L-shift $R = 11110 $Q = 0 0 0 0 $M = 00011

Step 2, Add + $M =00011
$R = 00001 $Q = 0001
Step 3, Set Q0

Step 1, L-shift $R,Q = 0 0 0 1 0 $Q = 0 0 1 0 $M = 00011

Step 2, Add – $M = 1 1 1 0 1
Iteration 4

$R = 1 1 1 1 1 $Q = 0 0 1 0 Final quotient = 2
Step 3, Set Q0
Restore + $M = 0 0 0 1 1
$R = 00010 Remainder = 2

See, V. C. Hamacher, Z. G. Vranesic and Z. G. Zaky, Computer

Organization, Fourth Edition, McGraw-Hill, 1996, Section 6.9, pp.
281-285.
Fall 2015, Aug 19 . . . ELEC2200-002 Lecture 2 65
 Signed Division
Remember the signs and divide
magnitudes.
Negate the quotient if the signs of divisor
and dividend disagree.
There is no other direct division method for
signed division.

Fall 2015, Aug 19 . . . ELEC2200-002 Lecture 2 66

 Symbol Representation
Early versions (60s and 70s)
Six-bit binary code (Control Data Corp., CDC)
EBCDIC – extended binary coded decimal
interchange code (IBM)
Presently used –
ASCII – American standard code for information
interchange – 7 bit code specified by American
National Standards Institute (ANSI), see Table
1.11 on page 63; an eighth MSB is often used as
parity bit to construct a byte-code.
Unicode – 16 bit code and an extended 32 bit
version

Fall 2015, Aug 19 . . . ELEC2200-002 Lecture 2 67

 ASCII
Each byte pattern represents a character (symbol)
– Convenient to write in hexadecimal, e.g., with even parity,
00000000 0ten 00hex null
01000001 65ten 41hex A
11100001 225ten E1hex a
– Table 1.11 on page 63 gives the 7-bit ASCII code.
– C program – string – terminating with a null byte (odd
parity):
01000101 01000011 01000101 10000000
69ten or 45hex 67ten or 43hex 69ten or 45hex 128ten or 80hex
E C E (null)

Fall 2015, Aug 19 . . . ELEC2200-002 Lecture 2 68

 Error Detection Code
Errors: Bits can flip due to noise in circuits
and in communication.
Extra bits used for error detection.
Example: a parity bit in ASCII code
7-bit ASCII code

Even parity code for A 01000001

(even number of 1s) Parity bits
Odd parity code for A 11000001
(odd number of 1s)
Single-bit error in 7-bit code of “A”, e.g., 1000101, will change
symbol to “E” or 1000000 to “@”. But error will be detected in
the 8-bit code because the error changes the specified parity.
Fall 2015, Aug 19 . . . ELEC2200-002 Lecture 2 69
 Richard W. Hamming
Error-correcting codes
(ECC).
Also known for
Hamming distance (HD)
= Number of bits two
binary vectors differ in
Example:
HD(1101, 1010) = 3
Hamming Medal, 1988

1915 -1998
Fall 2015, Aug 19 . . . ELEC2200-002 Lecture 2 70
 The Idea of Hamming Code
N=4
Code space contains 2N possible N-bit code words: Code Symbol

0010 1110 0000 0

”2” ”E” 0001 1
HD = 1 0010 2
HD = 1 0011 3
1010 0100 4
1-bit error in “A” ”A” 0101 5
HD = 1 0110 6
HD = 1 0111 7
1000 8
1000 1011
”8” ”B”
1001 9
1010 A
1011 B
Error not correctable. Reason: No redundancy. 1100 C
Hamming’s idea: Increase HD between valid code words. 1101 D
1110 E
1111
Fall 2015, Aug 19 . . . ELEC2200-002 Lecture 2
F 71
 Hamming’s Distance ≥ 3 Code
1110100
0010101
”2” HD = 4 ”E”

HD = 4 HD = 3

HD = 3

0010010 HD = 1 HD = 3
1-bit error in “A” ”?” 1010010 0011110
”A” ”3”
shortest distance
decoding eliminates HD = 2
error
HD = 4

HD = 3 HD = 3
1000111
”8”
1011001
”B”
Fall 2015, Aug 19 . . . ELEC2200-002 Lecture 2 72
 Minimum Distance-3 Hamming Code
Original Odd-parity
Symbol
code code
ECC, HD ≥ 3
Original code: Symbol “0” with a
0 0000 10000 0000000 single-bit error will be Interpreted as
1 0001 00001 0001011 “1”, “2”, “4” or “8”.
2 0010 00010 0010101
3 0011 10011 0011110 Reason: Hamming distance between
4 0100 00100 0100110 codes is 1. A code with any bit error will
5 0101 10101 0101101 map onto another valid code.
6 0110 10110 0110011
7 0111 00111 0111000
Remedy 1: Design codes with HD ≥ 2.
8 1000 01000 1000111
Example: Parity code. Single bit error
9 1001 11001 1001100
detected but not correctable.
A 1010 11010 1010010
Remedy 2: Design codes with HD ≥ 3.
B 1011 01011 1011001
For single bit error correction, decode
C 1100 11100 1100001
as the valid code at HD = 1.
D 1101 01101 1101010
E 1110 01110 1110100
For more error bit detection or
F 1111 11111 1111111
correction, design code with HD ≥ 4.
Fall 2015, Aug 19 . . . ELEC2200-002 Lecture 2 73
 Integers and Real Numbers
Integers: the universe is infinite but discrete
– No fractions
– No numbers between consecutive integers, e.g., 5 and 6
– A countable (finite) number of items in a finite range
– Referred to as fixed-point numbers
Real numbers – the universe is infinite and continuous
– Fractions represented by decimal notation
Rational numbers, e.g., 5/2 = 2.5
Irrational numbers, e.g., 22/7 = 3.14159265 . . .
– Infinite numbers exist even in the smallest range
– Referred to as floating-point numbers

Fall 2015, Aug 19 . . . ELEC2200-002 Lecture 2 74

 Wide Range of Numbers
A large number:
976,000,000,000,000 = 9.76 × 1014
A small number:
0.0000000000000976 = 9.76 × 10 –14

Fall 2015, Aug 19 . . . ELEC2200-002 Lecture 2 75

 Scientific Notation
Decimal numbers
0.513×105, 5.13×104 and 51.3×103 are written in
scientific notation.
5.13×104 is the normalized scientific notation.
Binary numbers
Base 2
Binary point – multiplication by 2 moves the point
to the right.
Normalized scientific notation, e.g., 1.0two×2 –1

Fall 2015, Aug 19 . . . ELEC2200-002 Lecture 2 76

 Floating Point Numbers
General format
±1.bbbbbtwo×2eeee

or (-1)S × (1+F) × 2E
Where
S = sign, 0 for positive, 1 for negative
F = fraction (or mantissa) as a binary integer,
1+F is called significand
E = exponent as a binary integer, positive or
negative (two’s complement)

Fall 2015, Aug 19 . . . ELEC2200-002 Lecture 2 77

 Binary to Decimal Conversion

Binary (-1)S (1.b1b2b3b4) × 2E

Decimal (-1)S × (1 + b1×2-1 + b2×2-2 + b3×2-3 + b4×2-4) × 2E

Example: -1.1100 × 2-2 (binary) = - (1 + 2-1 + 2-2) ×2-2

= - (1 + 0.5 + 0.25)/4

= - 1.75/4

= - 0.4375 (decimal)

Fall 2015, Aug 19 . . . ELEC2200-002 Lecture 2 78

 William Morton (Velvel) Kahan
Architect of the IEEE floating point standard

1989 Turing Award Citation:

For his fundamental contributions to

numerical analysis. One of the foremost
experts on floating-point computations.
Kahan has dedicated himself to "making
the world safe for numerical
computations."

b. 1933, Canada
Professor of Computer Science, UC-Berkeley
Fall 2015, Aug 19 . . . ELEC2200-002 Lecture 2 79
 Numbers in 32-bit Formats
Two’s complement integers

Expressible numbers
-231 0 231-1

Floating point numbers Positive underflow

Negative underflow
–∞ Negative zero Positive zero
+∞
Negative Expressible Expressible Positive
Overflow negative positive Overflow
numbers numbers

- (2 – 2-23)×2128 -2-127 0 2-127 (2 – 2-23)×2128

Ref: W. Stallings, Computer Organization and Architecture, Sixth
Edition, Upper Saddle River, NJ: Prentice-Hall.

Fall 2015, Aug 19 . . . ELEC2200-002 Lecture 2 80

 IEEE 754 Floating Point Standard
Biased exponent: true exponent range
[-126,127] is changed to [1, 254]:
Biased exponent is an 8-bit positive binary integer.
True exponent obtained by subtracting 127ten or
01111111two
First bit of significand is always 1:
± 1.bbbb . . . b × 2E
1 before the binary point is implicitly assumed.
Significand field represents 23 bit fraction after the
binary point.
Significand range is [1, 2), to be exact [1, 2 – 2-23]
Fall 2015, Aug 19 . . . ELEC2200-002 Lecture 2 81
 Examples
Biased exponent (1-254), bias 127 (01111111) to be subtracted

1.1010001 × 210100 = 0 10010011 10100010000000000000000 = 1.6328125 × 220

-1.1010001 × 210100 = 1 10010011 10100010000000000000000 = -1.6328125 × 220

1.1010001 × 2-10100 = 0 01101011 10100010000000000000000 = 1.6328125 × 2-20

-1.1010001 × 2-10100 = 1 01101011 10100010000000000000000 = -1.6328125 × 2-20

1.0 8-bit biased exponent 23-bit Fraction (F)

0.5 Sign bit 107 – 127 of significand
0.125 = – 20
0.0078125
1.6328125
Fall 2015, Aug 19 . . . ELEC2200-002 Lecture 2 82
 Example: Conversion to Decimal
normalized E F
Sign bit S bits 23-30 bits 0-22

1 10000001 01000000000000000000000

Sign bit is 1, number is negative

Biased exponent is 27+20 = 129
The number is
(-1)S × (1 + F) × 2(exponent – bias) = (-1)1 × (1 + F) × 2(129 – 127)
= - 1 × 1.25 × 22
= - 1.25 × 4
= - 5.0

Fall 2015, Aug 19 . . . ELEC2200-002 Lecture 2 83

 IEEE 754 Floating Point Format
Floating point numbers
normalized E F
bits 23-30 bits 0-22
Sign bit S
1 1011001 01001100000000010001101
Positive integer – 127 = E
Positive underflow
Negative underflow
–∞ –0 +0 +∞
Negative Expressible Expressible Positive
Overflow negative positive Overflow
numbers numbers

- (2 – 2 -23
)×2 127 -2-126 0 2-126 (2 – 2-23)×2127

Fall 2015, Aug 19 . . . ELEC2200-002 Lecture 2 84

 Positive Zero in IEEE 754
0 00000000 00000000000000000000000
Biased Fraction
exponent

+ 1.0 × 2 –127
Smaller than the smallest positive number in
single-precision IEEE 754 standard.
Interpreted as positive zero.
True exponent less than –126 is positive
underflow; can be regarded as zero.

Fall 2015, Aug 19 . . . ELEC2200-002 Lecture 2 85

 Negative Zero in IEEE 754
1 00000000 00000000000000000000000
Biased Fraction
exponent

– 1.0 × 2 –127
Greater than the largest negative number in
single-precision IEEE 754 standard.
Interpreted as negative zero.
True exponent less than –126 is negative
underflow; may be regarded as 0.

Fall 2015, Aug 19 . . . ELEC2200-002 Lecture 2 86

 Positive Infinity in IEEE 754
0 11111111 00000000000000000000000
Biased Fraction
exponent

+ 1.0 × 2128
Greater than the largest positive number in
single-precision IEEE 754 standard.
Interpreted as + ∞
If true exponent > 127, then the number is
greater than ∞. It is called “not a number” or
NaN and may be interpreted as ∞.

Fall 2015, Aug 19 . . . ELEC2200-002 Lecture 2 87

 Negative Infinity in IEEE 754
1 11111111 00000000000000000000000
Biased Fraction
exponent

–1.0 × 2128
Smaller than the smallest negative number in
single-precision IEEE 754 standard.
Interpreted as - ∞
If true exponent > 127, then the number is less
than - ∞. It is called “not a number” or NaN and
may be interpreted as - ∞.

Fall 2015, Aug 19 . . . ELEC2200-002 Lecture 2 88

 Addition and Subtraction
0. Zero check
- Change the sign of subtrahend, i.e., convert to summation
- If either operand is 0, the other is the result
1. Significand alignment: right shift significand of
smaller exponent until two exponents match.
2. Addition: add significands and report error if
overflow occurs. If significand = 0, return result
as 0.
3. Normalization
- Shift significand bits to normalize.
- report overflow or underflow if exponent goes out of range.
4. Rounding
Fall 2015, Aug 19 . . . ELEC2200-002 Lecture 2 89
 Example (4 Significant Fraction Bits)
Subtraction: 0.5ten – 0.4375ten
Step 0: Floating point numbers to be added
1.000two× 2 –1 and –1.110two× 2 –2
Step 1: Significand of lesser exponent is shifted
right until exponents match
–1.110two× 2 –2 → – 0.111two× 2 –1
Step 2: Add significands, 1.000two + ( – 0.111two)
01000
Result is 0.001two × 2 –1
+11001
00001
2’s complement addition, one bit added for sign
Fall 2015, Aug 19 . . . ELEC2200-002 Lecture 2 90
 Example (Continued)
–4
Step 3: Normalize, 1.000two× 2
No overflow/underflow since
127 ≥ exponent ≥ –126
Step 4: Rounding, no change since the sum
fits in 4 bits.

–4
1.000two × 2 = (1+0)/16 = 0.0625ten

Fall 2015, Aug 19 . . . ELEC2200-002 Lecture 2 91

 FP Multiplication: Basic Idea
1. Separate sign
2. Add exponents (integer addition)
3. Multiply significands (integer multiplication)
4. Normalize, round, check overflow/underflow
5. Replace sign

Fall 2015, Aug 19 . . . ELEC2200-002 Lecture 2 92

 FP Multiplication: Step 0
Multiply, X × Y = Z

no no
X = 0? Y = 0? Steps 1 - 5

yes yes

Z=0

Return

Fall 2015, Aug 19 . . . ELEC2200-002 Lecture 2 93

 FP Multiplication Illustration
Multiply 0.5ten and – 0.4375ten
(answer = – 0.21875ten) or
Multiply 1.000two×2 –1 and –1.110two×2 –2

Step 1: Add exponents

–1 + (–2) = – 3
Step 2: Multiply significands
1.000
×1.110
0000
1000
1000
1000
1110000 Product is 1.110000

Fall 2015, Aug 19 . . . ELEC2200-002 Lecture 2 94

 FP Mult. Illustration (Cont.)
Step 3:
– Normalization: If necessary, shift significand right and
increment exponent.
Normalized product is 1.110000 × 2 –3
– Check overflow/underflow: 127 ≥ exponent ≥ –126
Step 4: Rounding: 1.110 × 2 –3
Step 5: Sign: Operands have opposite signs,
Product is –1.110 × 2 –3
(Decimal value = – (1+0.5+0.25)/8 = – 0.21875ten)

Fall 2015, Aug 19 . . . ELEC2200-002 Lecture 2 95

 FP Division: Basic Idea
Separate sign.
Check for zeros and infinity.
Subtract exponents.
Divide significands.
Normalize and detect overflow/underflow.
Perform rounding.
Replace sign.

Fall 2015, Aug 19 . . . ELEC2200-002 Lecture 2 96