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Interrupts 8086

The document discusses interrupts in the 8086 microprocessor. It describes hardware interrupts from the NMI and INTR pins, as well as software interrupts caused by INT instructions. The interrupt vector table stores the addresses of interrupt service routines. Common hardware interrupts include NMI, INTR, and overflow interrupts handled by the INTO instruction. Software interrupts include the INT3 instruction for breakpoint handling.

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58 views11 pages

Interrupts 8086

The document discusses interrupts in the 8086 microprocessor. It describes hardware interrupts from the NMI and INTR pins, as well as software interrupts caused by INT instructions. The interrupt vector table stores the addresses of interrupt service routines. Common hardware interrupts include NMI, INTR, and overflow interrupts handled by the INTO instruction. Software interrupts include the INT3 instruction for breakpoint handling.

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Aswin Aswin
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PPTX, PDF, TXT or read online on Scribd
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INTERRUPTS-8086

8086 Interrupts
● Interrupt i s t h e m e t h o d o f c r e a t i n g a
t e m p o r a r y halt during p r o g r a m execution
a n d allows p e r i p h e r a l d e v i c e s to a c c e s s the
microprocessor. The microprocessor
r e s p o n d s to that interrupt with
a n ISR ( I n t e r r u p t S e r v i c e R o uti n e) , w h i c h i s
a short p r o g r a m to instruct th e
m i c r o p r o c e s s o r o n h o w to h a n d l e the
interrupt.
⚫ Hardware Interrupts
⚫ T h e 8 0 8 6 h a s two h a r d w a r e interrupt pins,
i.e. N M I a n d INTR. N M I i s a n o n - m a s k a b l e
i n t e r r u p t a n d I NTR i s a m a s k a b l e i n t e r r u p t
h a v i n g l o w e r p r i o r i t y.
NMI
⚫ It i s a s i n g l e n o n - m a s k a b l e i n t e r r u p t p i n (NMI)
having higher priority than the maskable
i n t e r r u p t r e q u e s t p i n ( I N TR )a n d it i s o f t y p e 2
interrupt.
⚫ MP obtains the ISR address from location
2*4=00008H from the IVT
INTR
⚫ T h e INTR is a m a s k a b l e interrupt b e c a u s e th e
m i c r o p r o c e s s o r w i l l b e i n t e r r u p t e d o n l y if i n t e r r u p t s
a r e e n a b l e d using set interrupt fl a g instruction.
⚫ On receiving interrupt on INTR line , MP executes to
I N TA p u l s e s
⚫ Interrupting device calculate the vector number
⚫ Interrupting device sends the vector number
Software
Interrupts
⚫ These interrupts are caused by writing the software interrupt
instruction INTn
⚫ n->0 to 255
⚫ Hence all 256 interrupts can be invoked by software
INTERRUPT VECTOR TABLE
⚫ T h e starting a d d r e s s for t y p e 0 interrupt is
0 0 0 0 0 0 H , for t y p e 1 interrupt is 0 0 0 0 4 H
s i m i l a r l y f o r t y p e 2 i s 0 0 0 0 8 H a n d ……so o n .
T h e first fi ve pointers a r e d edi ca t e d interrupt
p o i n t e r s . i.e. −
● TYPE 0 i n t e r r u p t r e p r e s e n t s d i v i s i o n b y z e r o
situation.
● TYPE 1 i n t e r r u p t r e p r e s e n t s s i n g l e - s t e p
execution during the debugging of a program.
● TYPE 2 i n t e r r u p t r e p r e s e n t s n o n - m a s k a b l e
NMI interrupt.
● TYPE 3 i n t e r r u p t r e p r e s e n t s b r e a k -
point interrupt.
● TYPE 4 i n t e r r u p t r e p r e s e n t s o v e r fl o w
interrupt.
INTO - Interrupt on overflow
instruction
⚫ It i s a 1 - b y t e i n s t r u c t i o n a n d t h e i r
m n e m o n i c INTO. T h e o p - c o d e for this
i n s t r u c t i o n i s C E H . A s t h e n a m e s u g g e s t s it i s
a
c o n d i t i o n a l i n t e r r u p t i n s t r u c t i o n , i.e. it i s a c t i v e
o n l y w h e n the o v e r fl o w fl a g is set to 1 a n d
b r a n c h e s to the interrupt h a n d l e r w h o s e interrupt
t y p e n u m b e r i s 4. If t h e o v e r fl o w fl a g i s r e s e t t h e n ,
the e xe c u t io n cont inues to the n e x t instruction.
⚫ Its e x e c u t i o n i n c l u d e s t h e f o l l o w i n g s t e p s −
⚫ Flag register val ues a r e p u s h e d o n to the stack.
⚫ C S va l u e of t h e r e tu r n a d d r e s s a n d IP va l u e of th e
return a d d r e s s a r e p u s h e d o n to the stack.
⚫ I P i s l o a d e d f r o m t h e c o n t e n t s o f w o r d l o c a t i o n 4×4 =
00010H
⚫ C S is l o a d e d f r o m the contents of the n e x t w o r d
location.
INT 3-Break Point Interrupt
Instruction
⚫ It i s a 1 - b y t e i n s t r u c t i o n h a v i n g o p - c o d e is
CCH. T h e s e instructions a r e inserted into
the p r o g r a m so that w h e n the p r o c e s s o r
r e a c h e s t h e r e , t h e n it s t o p s t h e n o r m a l
e x e c u t i o n o f p r o g r a m a n d fo l l o w s t h e
break-point procedure.
⚫ Its e x e c u t i o n i n c l u d e s t h e f o l l o w i n g s t e p s −
⚫ Flag register va l u e is p u s h e d o n to t he stack.
⚫ C S v a l u e of t h e r e t ur n a d d r e s s a n d IP v a l u e of
the return a d d r e s s a r e p u s h e d o n to the
stack.
⚫ IP is l o a d e d f r o m t h e co n t e n t s of t h e w o r d
l o c a t i o n 3×4 = 0 0 0 0 C H
⚫ C S is l o a d e d f r o m t he contents of the n e x t
wo r d location.

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