INTEGRATED CIRCUIT(IC)

 It is an electronic assembly built in such a way

that all the components in the circuit are
fabricate on a single container called Chip.
 CLASSIFICATION OF ICS

BASED ON APPLICATION
BASED ON FABRICATION TECHNIQUES
BASED ON TECHNOLOGY
BASED ON DEVICE COUNT
 BASED ON APPLICATION

• LINEAR Ics: These are discrete circuits which need

external components like resistor, and capacitors for
satisfactory performance apart from the input. They
work on analog signal rather digital signal. Eg. Op-
amp, ADC, DAC, Timer (555).

• DIGITAL Ics : They require only digital input and not

any other component for operation.
eg. All Ics like Logic gates, adders, comparators, etc
 BASED ON FABRICATION
TECHNIQUES
Monolithic Ics: All the active and passive components
of a circuit can be fabricated on a single piece of
silicon. (Metallization is used for interconnection.)
Hybrid Ics:
Separate component parts are attached to ceramic
substrate and interconnected by means of either
metallization pattern (or ) wire bonds.
 BASED ON DEVICE COUNT
(LEVEL OF INTEGRATION
• Device count is restricted to the number of
active devices (FET and BJT)
Nomenclature Active Devices Typical functions
SSI 1-100 Gates, oP amps …
MSI 100-1000 Registers, Filters,
etc
LSI 1000-100,000 Microprocessors,
A/D
VLSI 105 TO 106 Memories,
computers, signal
processors
ULSI 106 (Ultra Large Scale
Integration
Especially)
WSI Wafer scale Integration under processing
 CMOS LOGIC
• A very effective logic circuit can be established
by constructing a p-channel and an n-channel
MOSFET on the same substrate.

• The configuration is referred to as a

complementary MOSFET arrangement (CMOS)
that has extensive applications in computer
logic design.
 CMOS LOGIC
• The relatively
high input impedance,
fast switching speeds, and
lower operating power levels of the CMOS
configuration have resulted in a whole new discipline
referred to as CMOS logic design.
CMOS cont.
 Chapter 2 HARDWARE
DESCRIPTION LANGUAGE (HDL).
A hardware description language is a language
used to describe a digital system:
for example,
 a network switch,
 a microprocessor or a memory or
 a simple flip-flop.

This just means that, by using a HDL, one can

describe any (digital) hardware at any level.
Why HDL?
 HDL (continued)
• One can describe a simple Flip flop as that in the above figure,
as well as a complicated design having 1 million gates.

• Verilog is one of the HDL languages available in the industry

for hardware designing.

• It allows us to design a Digital design at

 Behavior Level,
 Register Transfer Level (RTL),
 Gate level and at switch level.
Verilog allows hardware designers to express their designs with behavioral constructs,
deferring the details of implementation to a later stage in the final design.
 1 // D flip-flop Code
2 module d_ff ( d, clk, q, q_bar);
3 input d ,clk;
4 output q, q_bar;
5 wire d ,clk;
6 reg q, q_bar;
7
8 always @ (posedge clk)
9 begin
10 q <= d;
11 q_bar <= ! d;
12 end
13
14 endmodule
Modeling Structure: Modules
• The module is the basic building block in Verilog
– Modules can be interconnected to describe the structure of your digital system
– Modules start with keyword module and end with keyword endmodule

Module AND <port list> Module CPU <port list>

• •
• •
• •

– Modules have ports for interconnection with other modules

endmodule endmodule
 Operators
• Logical operators map into primitive
logic gates addr = ~data << 2
• Arithmetic operators map into
adders, subtractors, …
– Unsigned 2s complement data3 addr5
– Model carry: target is one-bit data2 addr4
wider that source
– Watch out for *, %, and / data1 addr3
• Relational operators generate data0 addr2
comparators
addr1
• Shifts by constant amount are just
wire connections
– No logic invoved addr0
• Variable shift amounts a whole
different story --- shifter
• Conditional expression generates
logic or MUX
9/20/07 EECS 150, Fa07, Lec 08-timing-synth 46
 Operators
Arithmetic Operators +, -, *, /, %
Relational Operators <, <=, >, >=
Equality Operators ==, !=, ===, !==
Logical Operators !, &&, ||
Bit-Wise Operators ~, &, |, ^, ~^
Unary Reduction &, ~&, |, ~|, ^, ~^
Shift Operators >>, <<
Conditional Operators ?:
Concatenations {}
 Operators ~ bit-wise NOT
{} concatenation
+ - * / & bit-wise AND
arithmetic | bit-wise OR
% modulus ^ bit-wise XOR
^~ ~^ bit-wise XNOR
> >= < <=
& reduction AND
relational
| reduction OR
! logical NOT ~& reduction NAND
&& logical AND ~| reduction NOR
|| logical OR ^ reduction XOR
== logical equality ~^ ^~ reduction XNOR
!= logical inequality << shift left
?: conditional >> shift right
 Brief Comparison Between
VHDL and Verilog
Introduction
There are now two industries standard hardware description languages,

VHDL and Verilog

Verilog: Verilog HDL is a harware description language that can describe
hardware not only at the gate level and the register-transistor level
(RTL), but also at the algorithmic level. This makes translating a design
described in Verilog HDL to logic gates a non-trivial (significant) process.
 has been used far longer than VHDL and has been used extensively since it was
launched by Gateway in 1983.
 Cadence bought Gateway in 1989 and opened Verilog to the public domain in
1990.

 Became IEEE standard 1364 in December 1995.

 Comparison (Continued)
VHDL (Very high speed integrated circuit Hardware Description Language)
 Become IEEE standard 1076 in 1987.
 It was updated in 1993 and is known today as “IEEE standard 1076 1993 ”

1. Capability
 Hardware structure can be modeled equally effectively in both VHDL and
Verilog.
 When modelling abstract hardware, the capability of VHDL can sometimes
only be achived in Verilog when using the PLI.

 The choice of which to use is not therefore based society on technical

capability but on: Personal preference, EDA tool availability and
commercial business and marketing issues.
 2. compilation
VHDL.
 Multiple design-units (entity/architecture pairs) that reside in the same system
file, may be separately compiled if so desired.
 However, it is good design practice to keep each design unit in it’s own system file
in which case separate compilation should not be an issue.

Verilog.
 Is still rooted its native interpretative mode.
 Compilation is a means of speeding up simulation, but has not changed the
original nature of the language.
 As a result, care must be taken with both the compilation order of multiple files.
 Simulation result can change by simply changing the order of compilation.
 3.Data types
VHDL.
 A multitude of Language or user defined data types can be used.
 This may mean dedicated conversion functions are needed to convert objects
from one type to another.
 The choice of which data types to use should be considered wisely, especially
enumerated (abstract) data types.

 This will make models easier to write, clearer to read and avoid
unnecessary conversion function that can clutter the code.

 VHDL may be preferred because it allows a multitude of Language or user

defined data type to be used.
 Data type (continued)
Verilog.
 Compared to VHDL, verilog data types are very simple, easy to use and very much
geared towards modelling hadware structure as opposed to abstract hardware
modelling.
 Unlike VHDL, all data types used in a verilog model are defined by the verilog
language and not by the user.
 There are net data types, for example wire, and a register data type called reg.
 A model with a signal whose type is one of the net data types has a corresponding
electrical wire in the implied modelled circuit.
 Objects, that are signals, of type reg hold their value over simulation delta cycles
and should not be confused with the modelling of a hardware register.

 Verilog may be preferred because of its simplicity.

 4. Design reusability
VHDL.
 Procedures and functions may be placed in a package so that they are available to

any design unit that wishes to use them .

Verilog.
 There is no concept of package in verilog.

 Function and procedures used within a model must be defined in the module.

 To make functions and procedures generally accessible from different module

statements the functions and procedures must be placed in a separate system file
and included using the included complier directive.
 5.Easiest to Learn
 Starting with zero knowledge of either language. Verilog is probably the
easiest to grasp and understand. This assumes the verilog complier
directive language for simulation and the PLI language is not included. If
these languages are included, they can be looked upon as two additional
language that need to be learned.

 VHDL may seem less intuitive(easy to use and understand) at first for two
primary reasons.
 First, it is very strongly typed; a feature that makes it robust and
powerful for the advanced user after a longer learning phase.
 Second, there are many ways to model the same circuit. Specially
those with large hierarchical structures.
 6.High level construction
VHDL. There are more constructs and features for high-level modelling in VHDL
than there is in Verilog. Abstract data types can be used along with the following
statements:
 Package statements for model reuse.
 Configure statement for replication structure
 Generate statements for generic models that can be individually
characterized, for example, bit width
All these language statements are useful in synthesizable models.

Verilog.
Except for being able to parameterise models by overloading parameter constants,
there is no equivalent to the high-level VHDL modelling statements in Verilog.
 7.Language Extension
 The use of extension will make a model non standard and most likely not portable
across other design tools. However they are necessary in order to achieve the
desired results.

 VHDL .Has an attribute called “foreign that allows architectures and

subprograms to be modelled in another language.

 Verilog. The programming Language Interface (PLI) is an interface

mechanism between Verilog models and Verilog software tools. For example, a
designer, or more likely, a verilog tool vendor, can specify user defined tasks or
functions in the C programming language, and then call them from the verilog
source description .
 Use of such tasks or functions make a verilog model non-standard and so may
not be usable by other Verilog tools. Their use is not recommended.
 8.Libraries
VHDL.
 A library is a store for compiled entities, architectures, packages and
configurations. Useful for managing multiple design projects.

9.Structural replication
VHDL.
 The generate statement replicates a number of instances of the same design-unit
or some sub part of a design, and connects it appropriately.
Verilog.
 There is no equivalent to the generate statement in Verilog
Chapter 3. Digital System Design
• Many engineers who want to learn this
language, very often ask this question, how
much time will it take to learn Verilog?
Well my answer to them is

• "It may take no more than one week, if you

happen to know at least one programming
language".
 Design Methodology
Structure and Function HDL
(Behavior) of a Design Specification

Simulation Synthesis

Verification: Design Generation: Map

Behave as Required? Specification to
Functional: I/O Behavior Implementation
Register-Level (Architectural)
Logic-Level (Gates)
Transistor-Level (Electrical)
Timing: Waveform Behavior

9/6/2007 EECS 150, Fa07, Lec 04-HDL 67

 Design Styles

Verilog, like any other hardware description

language, permits a design in either

Bottom-up

or

Top-down methodology.
 Bottom-Up Design
– The traditional method of electronic design is bottom-up.
Each design is performed at the gate-level using the
standard gates (refer to the Digital Section for more
details). With the increasing complexity of new designs
this approach is nearly impossible to maintain. New
systems consist of ASIC or microprocessors with a
complexity of thousands of transistors. These traditional
bottom-up designs have to give way to new structural,
hierarchical design methods. Without these new practices it
would be impossible to handle the new complexity.
 Top-Down Design
– The desired design-style of all designers is the top-
down one. A real top-down design allows early
testing, easy change of different technologies, a
structured system design and offers many other
advantages. But it is very difficult to follow a pure
top-down design. Due to this fact most designs
are a mix of both methods, implementing some
key elements of both design styles.
 Verilog level of Abstraction
• Verilog supported levels of abstraction
– Behavioral (algorithmic) level
• Describe the algorithm used
• Very similar to C programming
– Dataflow level
• Describe how data flows between registers and is processed
– Gate level
• Interconnect logic gates
– Switch level
• Interconnect transistors (MOS transistors)
• Register-Transfer Level (RTL)
– Generally known as a combination of behavioral+dataflow that is
synthesizable by EDA tools

2005 Verilog HDL 73

 Behavioral level
• This level describes a system by concurrent
algorithms (Behavioral). Each algorithm itself
is sequential, that means it consists of a set of
instructions that are executed one after the
other.
• Functions, Tasks and Always blocks are the
main elements. There is no regard to the
structural realization of the design.
 Register-Transfer Level

• Designs using the Register-Transfer Level

specify the characteristics of a circuit by
operations and the transfer of data between
the registers. An explicit clock is used.
• RTL design contains exact timing bounds:
operations are scheduled to occur at certain
times. Modern RTL code definition is "Any
code that is synthesizable is called RTL code".
 Gate Level

• Within the logic level the characteristics of a system

are described by logical links and their timing
properties. All signals are discrete signals. They can
only have definite logical values (`0', `1', `X', `Z`). The
usable operations are predefined logic primitives
(AND, OR, NOT etc gates).
• Using gate level modeling might not be a good idea
for any level of logic design. Gate level code is
generated by tools like synthesis tools and this netlist
is used for gate level simulation and for backend.
 Verilog Basic Building Block
• Module

module not_gate(in, out); // module name+ports

// comments: declaring port type
input in;
output out;

// Defining circuit functionality

assign out = ~in;

endmodule

2005 Verilog HDL 92

 Verilog
• Supports structural and behavioral
descriptions
• Structural
– Explicit structure of the circuit
– How a module is composed as an interconnection of more primitive
modules/components
– E.g., each logic gate instantiated and connected to others

• Behavioral
– Program describes input/output behavior of circuit
– Many structural implementations could have same behavior
– E.g., different implementations of one Boolean function

9/6/2007 EECS 150, Fa07, Lec 04-HDL 93

 Verilog Introduction
• the module describes a component in the circuit
• Two ways to describe:
– Structural Verilog
• List of components and how they are connected
• Just like schematics, but using text
– A net list
• tedious to write, hard to decode
• Essential without integrated design tools
– Behavioral Verilog
• Describe what a component does, not how it does it
• Synthesized into a circuit that has this behavior
• Result is only as good as the tools

• Build up a hierarchy of modules

9/6/2007 EECS 150, Fa07, Lec 04-HDL 94

 Structural Model - XOR
module name

module xor_gate ( out, a, b ); port list

input a, b;
output out;
wire abar, bbar, t1, t2; declarations
Built-in gates
inverter invA (abar, a); statements
inverter invB (bbar, b);
and_gate and1 (t1, a, bbar);
A
and_gate and2 (t2, b, abar); and1 t1
out
or_gate or1 (out, t1, t2); invA
or1
B
and2
endmodule interconnections t2
invB
Instance name

– Composition of primitive gates to form more complex module

– Note use of wire declaration!
By default, identifiers are wires
9/6/2007 EECS 150, Fa07, Lec 04-HDL 98
 Structural Model: 2-to1 mux
//2-input multiplexor in gates • Notes:
module mux2 (in0, in1, select, out); – comments
input in0,in1,select; – “module”
output out; – port list
wire s0,w0,w1; – declarations
– wire type
not (s0, select); – primitive gates
and (w0, s0, in0), – Instance names?
(w1, select, in1); – List per type
or (out, w0, w1);

endmodule // mux2

in1 w1

s0 out
select
in0 w0

9/6/2007 EECS 150, Fa07, Lec 04-HDL 99

 Simple Behavioral Model
• Combinational logic
– Describe output as a function of inputs
– Note use of assign keyword: continuous assignment

module and_gate (out, in1, in2);

input in1, in2;
Output port of a primitive must
output out; be first in the list of ports

assign out = in1 & in2; Restriction does not apply to

modules in general
endmodule

When is this “evaluated”?

9/6/2007 EECS 150, Fa07, Lec 04-HDL 101

 2-to-1 mux behavioral description
• Notes:
// Behavioral model of 2-to-1 – behavioral descriptions using
// multiplexor. keyword always followed by
module mux2 (in0,in1,select,out); blocking procedural assignments
input in0,in1,select; – Target output of procedural
output out; assignments must of of type reg
// (not a real register)
– Unlike wire types where the
reg out;
target output of an assignment
always @ (in0 or in1 or select) may be continuously updated, a
if (select) out=in1; reg type retains it value until a
else out=in0; new value is assigned (the
endmodule // mux2 assigning statement is executed).
– Optional initial statement

Sensitivity list

9/6/2007 EECS 150, Fa07, Lec 04-HDL 102

 Behavioral 4-to1 mux
//Does not assume that we have • Notes:
// defined a 2-input mux. – No instantiation
– Case construct equivalent to nested if
//4-input mux behavioral description constructs.
module mux4 (in0, in1, in2, in3, select, out);
input in0,in1,in2,in3; – Definition: A structural description is
input [1:0] select; one where the function of the module
output out; is defined by the instantiation and
interconnection of sub-modules.
reg out;
– A behavioral description uses higher
level language constructs and
always @ (in0 in1 in2 in3 select) operators.
case (select) – Verilog allows modules to mix both
2’b00: out=in0; behavioral constructs and sub-module
2’b01: out=in1; instantiation.
2’b10: out=in2;
2’b11: out=in3;
endcase
endmodule // mux4
9/6/2007 EECS 150, Fa07, Lec 04-HDL 103
 Mixed Structural/Behavioral Model
Example 4-bit ripple adder
module full_addr (S, Cout, A, B, Cin );
input A, B, Cin;
output S, Cout;

assign {Cout, S} = A + B + Cin;

endmodule
Behavior
module adder4 (S, Cout, A, B, Cin);
input [3:0] A, B;
input Cin;
output [3:0] S;
output Cout;
wire C1, C2, C3;

full_addr fa0 (S[0], C1, A[0], B[0], Cin); Structural

full_addr fa1 (S[1], C2, A[1], B[1], C1);
full_addr fa2 (S[2], C3, A[2], B[2], C2);
full_addr fa3 (S[3], Cout, A[3], B[3], C3);
endmodule

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Order of ports? 104
 Verilog Data Types and Values
• Bits - value on a wire
– 0, 1
– X - don’t care/don’t know
– Z - undriven, tri-state

• Vectors of bits
– A[3:0] - vector of 4 bits: A[3], A[2], A[1], A[0]
– Treated as an unsigned integer value
• e.g. , A < 0 ??
– Concatenating bits/vectors into a vector
• e.g., sign extend
• B[7:0] = {A[3], A[3], A[3], A[3], A[3:0]};
• B[7:0] = {3{A[3]}, A[3:0]};
– Style: Use a[7:0] = b[7:0] + c;
Not: a = b + c; // need to look at declaration

9/6/2007 EECS 150, Fa07, Lec 04-HDL 110

 Verilog Operators

9/6/2007 EECS 150, Fa07, Lec 04-HDL 111

 Verilog Variables
• wire
– Variable used simply to connect components together

• reg
– Variable that saves a value as part of a behavioral description
– Usually corresponds to a wire in the circuit
– Is NOT necessarily a register in the circuit

• usage:
– Don’t confuse reg assignments with the combinational continuous assign
statement! (more soon)
– Reg should only be used with always blocks (sequential logic, to be
presented …)

9/6/2007 EECS 150, Fa07, Lec 04-HDL 112

 Verilog Module
• Corresponds to a circuit component
– “Parameter list” is the list of external connections, aka “ports”
A B Cin
– Ports are declared “input”, “output” or “inout”
• inout ports used on tri-state buses
– Port declarations imply that the variables are wires

module name ports

module full_addr (A, B, Cin, S, Cout); Cout S

input A, B, Cin;
output S, Cout; inputs/outputs

assign {Cout, S} = A + B + Cin;

endmodule

9/6/2007 EECS 150, Fa07, Lec 04-HDL 113

 Verilog Continuous Assignment
• Assignment is continuously evaluated
• assign corresponds to a connection or a
simple component with the described
function
• Target is NEVER a reg variable
use of Boolean operators
(~ for bit-wise, ! for logical negation)
assign A = X | (Y & ~Z);
• Dataflow style bits can take on four values
assign B[3:0] = 4'b01XX; (0, 1, X, Z)

assign C[15:0] = 4'h00ff; variables can be n-bits wide

(MSB:LSB)

assign #3 {Cout, S[3:0]} = A[3:0] + B[3:0] + Cin;

use of arithmetic operator

multiple assignment (concatenation)

delay of performing computation, only used by simulator, not synthesis

9/6/2007 EECS 150, Fa07, Lec 04-HDL 114
 Verilog® HDL

Hierarchical Modeling Concepts

 Design Methodologies

2005 Verilog HDL 116

 4-bit Ripple Carry Counter

2005 Verilog HDL 117

 Behavioral Level

• Describing function of a design using HDL

without specifying the architecture of
registers
• Contains timing information required to
represent a function
 Synthesis
• One of the best uses of VHDL today is to synthesize ASIC
and FPGA devices.
• Synthesis is an automatic method of converting a higher
level of abstraction to a lower level of abstraction.
• The current synthesis tools available today convert
Register Transfer Level (RTL) descriptions to gate level
netlists.
• These gate level netlists consist of interconnected gate
level macro cells.
• Models for the gate level cells are contained in
technology libraries for each type of technology
supported.
Chapter 5
• Systems-on-chips (SoCs). Fabrication
technology has advanced to the point that we
can put a complete system on a single chip.
For example, a single-chip computer can
include a CPU, bus, I/O devices, and memory.
SoCs allow systems to be made at much lower
cost than the equivalent board-level system.
 SoCs can also be higher performance and
lower power than board-level equivalents
because on-chip connections are more
efficient than chip-to-chip connections.
• Application-specific integrated circuits (ASICs).
Rather than build a system out of standard
parts, designers can now create a single chip
for their particular application.

• Because the chip is specialized, the functions

of several standard parts can often be
squeezed into a single chip, reducing system
size, power, heat, and cost..
• Application-specific ICs are possible because
of computer tools that help humans design
chips much more quickly.
• Systems-on-chips (SoCs). Fabrication
technology has advanced to the point that we
can put a complete system on a single chip.
For example, a single-chip computer can
include a CPU, bus, I/O devices, and memory.
SoCs allow systems to be made at much lower
cost than the equivalent board-level system.
• SoCs can also be higher performance and
lower power than board-level equivalents
because on-chip connections are more
efficient than chip-to-chip connections.