UNIT IV

8051 INSTRUCTION SET AND PROGRAMMING

 INSTRUCTION SET OF 8051

• Instruction supported by 8051 can be classified into different

types depending upon their operational functions.

• The instruction set classification is as followed.

  
Data Transfer Instructions

• As the name indicates, instructions in this set are used to

transfer data.
• The data can be transferred from or to external RAM or within
the internal memory itself.
• The instruction MOV is used to transfer the data between
internal registers/memory.
• The general format is
• MOV Reg destination, Reg source.
• The source and destination registers within the 8051 chip can
be addressed by any one of the addressing modes except
indexed addressing mode discussed earlier.
Data Transfer Instructions
Addressing Modes
Mnemonic Operation Indirec Register
Direct Immediate
t

MOV A, R0 A = <src> √ √ √ √

MOV R0, A <dest> = A √ √ √

MOV R0, R1 <dest> = <src> √ √ √ √

DPTR = 16-bit
MOV DPTR, #4000 immediate data
√

INC SP:
PUSH A MOV “@SP”, √
<scr>
MOV <dest>,
POP A “@SP”: DEC SP
√
Data Transfer Instructions
ACC and <byte> Exchange
XCH A, R0 Data
√ √ √

ACC and @ Ri exchange

XCHD A, @R0 low order nibbles √

Copy 8 bit data from the

external RAM location
MOVX A, @R2 pointed to by Ri
Only Indirect Addressing mode
to register A

Copy 8-bit data from

MOVX @ Ri, A register A to the external Only Indirect Addressing mode
RAM location pointed to
by Ri
Data Transfer Instructions
Copy 8-bit data from the
Only Indirect Addressing
MOVX A, @ DPTR external RAM location mode
pointed to by the 16-bit
DPTR to register A

Copy 8-bit data from register Only Indirect Addressing

MOVX @ DPTR, A A to the external RAM mode
location pointed to by the 16-
bit DPTR

Only Indirect Addressing

Read Program Memory at (A
MOVC A, @A + DPTR + DPTR)
mode

Only Indirect Addressing

Read Program Memory at (A
MOVC A, @A + PC + PC)
mode
 Arithmetic Instructions

• These instructions are used to do arithmetic operations.

• The common arithmetic operations like addition, subtraction,

multiplication and division are possible with 8051

• All the data used in arithmetic instructions must be available

inside the controller i.e. in the internal RAM area only.
 Arithmetic Instructions

• In addition to - ADD, ADDC and SUBB instructions in 8085, -have

instructions MUL and DIV.

• The register B is exclusively used for these two instructions. The

operands should be stored in the registers A and B for the MUL
and DIV instructions
 Arithmetic Instructions
• The MUL instruction multiplies the contents of A and B registers
and stores the 16 bit result in the combined A and B registers.

• The lower order byte -result is stored in A register and the higher
order byte - stored in B register.

• The DIV instruction upon execution will divide the contents of A

register by the contents of B register.

• The quotient of the result - stored in A register and the remainder

is stored in B register
Arithmetic Instructions
Addressing Modes
Mnemonic Operation
Direct Indirect Register Immediate
ADD A ,7F A = A + <byte> √ √ √ √

ADDC A,<byte> A = A + <byte>+C √ √ √ √

SUBB A, <byte> A = A – <byte>–C √ √ √ √

INC A A=A+1 Accumulator Only

DEC A A=A-1 Accumulator Only
<byte> = <byte>–
DEC 7F 1 √ √ √ √
MUL AB B:A= B  A Accumulator Only

A = Int [A/B]
DIV AB B = Mod [A/B]
Accumulator Only

Decimal Adjust
DAA Accumulator
Accumulator Only
 Logical Instructions
• In addition to logical AND, OR and XRL operation, 8051 has
additional instructions - CLR, CPL. All the data for the logical
instructions -available in the internal RAM only.

• The instruction CLR A -to clear the contents of A register, CPL is

used to complement or logically invert the contents of the A
register and SWAP - to swap the nibbles of A register.

• 8051 supports four rotate operations with the options –rotating

left or right and rotating through carry or not.
 Logical Instructions
Addressing Modes
Mnemonic Operation
Direct Indirect Register Immediate

ANL A, R0, 7F, # 74 A = A AND <byte> √ √ √ √

<byte> = <byte>
ANL 7F, A AND A √

<byte> = <byte>
ANL 7F, #7F AND # data √

ORL A, <byte> A = A OR <byte> √ √ √ √

<byte> = <byte>
ORL <byte>, A OR A
√

<byte> = <byte>
ORL <byte>, # data OR # data
√
 Logical Instructions
XRL A, <byte> A = A XOR <byte> √ √ √ √

XRL <byte>, A <byte> = <byte> XOR A √

<byte> = <byte> XOR #

XRL <byte>, # data data
√

CLR A A = 00H Accumulator only

RL A Rotate ACC Left 1 bit Accumulator only

Rotate Left through

RLC A Carry Accumulator only

RR A Rotate ACC Right 1 bit Accumulator only

Rotate Right through

RRC A Carry Accumulator only
 Branching Instructions

• 8051 supports unconditional jumping and subroutine calling in

three different ways.

• They are Absolute jump AJMP, ACALL, long jump LJMP, LCALL, and
short jump SJMP.
Unconditional Jumps
• SJMP <XX> ; Short jump, relative
address is 8-bit 2’s complement number, so
jump can be up to 127 locations forward, or
128 locations back.
• LJMP, 8100; Long jump
• AJMP <address 11> ; Absolute jump to
anywhere within 2K block of program memory
• JMP @A + DPTR ; Long indexed
jump
Conditional jumps
Mnemonic Description
JZ <rel addr> Jump if a = 0
JNZ <rel addr> Jump if a != 0

JC <rel addr> Jump if C = 1

JNC <rel addr> Jump if C != 1

JB <bit>, <rel addr> Jump if bit = 1

JNB <bit>,<rel addr> Jump if bit != 1

JBC <bir>, <rel addr> Jump if bit =1, &clear

bit
CJNE A, direct, <rel Compare A and memory,
addr> jump if not equal
More Conditional Jumps
Mnemonic Description
CJNE A, #05 <rel addr> Compare A and data, jump
if not equal
CJNE R0, #05 <rel addr> Compare Rn and data,
jump if not equal
CJNE @Rn, #data <rel addr> Compare Rn and memory,
jump if not equal
DJNZ R0, <rel addr> Decrement Rn and then
jump if not zero
DJNZ 45, <rel addr> Decrement memory and
then jump if not zero
Un Conditional Branching
Instructions
Conditional Branching Instructions
Addressing Modes
Mnemonic Operation
Direct Indirect Registe Immediate
r

Jump if A ≠=
CJNE A,<byte> <byte>
√ √

Jump if <byte> =
CJNE <byte>,#data #data
√ √

JZ Jump if A = 0 Accumulator only

JNZ Jump if A ≠ 0 Accumulator only

Call and Return
• Call is similar to a jump, but
• Call pushes PC on stack before branching

acall <address ll> ; stack  PC

; PC  address 11 bit

lcall <address 16> ; stack  PC

; PC  address 16 bit
Return

• Return is also similar to a jump, but

• Return instruction pops PC from stack to get address to
jump to

ret ; PC  stack
 Branching Instructions
• The micro controller 8051 -single instruction for counter operation
to decrement -result (DJNZ). -very useful in looping using a
counter similar to “for loop” in high level languages.

• Similarly, jumping after checking the result of a comparison -done

by a single instruction (CJNE) -very useful for looping of
instruction execution based on a condition.

• Used in programming constructs similar to “do while” in high level

languages.
 Bit Manipulation Instructions
• The special feature of the 8051 micro controller is that it can
handle bit data also like that of byte data.

• The internal data memory map of 8051 has a bit- addressable area
also.

• The special function registers that have the address with 0 or 8 as

last digit in their hex address, are also bit addressable.

• The bit manipulation instructions include logical instructions and

conditional branching
Bit Manipulation Instructions
Mnemonic Operation
ANL C,bit C = C AND bit
ANL C,/bit C = C AND (NOT bit)
ORL C,bit C = C OR bit
ORL C,/bit C = C OR (NOT bit)
MOV C,bit C = bit
MOV bit,C bit = C
CLR C C=0
CLR bit bit = 0
SETB C C=1
SETB bit bit = 1
CPL C C = NOT C
CPL bit bit = NOT bit
JC rel Jump if C = 1
JNC rel Jump if C = 0
JB bit,rel Jump if bit = 1
JNB bit,rel Jump if bit = 0
JBC bit,rel Jump if bit = 1 ; CLR bit
© Oxford University Press 2013
Instructions that affect Flag bits
Flags Affected
Instruction
C OV AC
ADD √ √ √
ADDC √ √ √
SUBB √ √ √
MUL 0 √
DIV 0 √
DA √
RRC √
RLC √
SETB C 1
CLR C 0
CPL C √
ANL C,bit √

ANL C,/bit √

ORL C,bit √

ORL C,/bit √

MOV C,bit √
CJNE √
© Oxford University Press 2013
 ADDRESSING MODES OF 8051

• The way by which a data in specified in an instruction is

called as addressing mode.

• The data fetched for execution depends upon the addressing

mode

• The instruction set of 8051 supports 5 addressing modes.

Immediate Addressing Mode
• The data to be manipulated is directly given in the instruction
itself.
• The data is preceded by a # symbol.

• E.g. ADD A, #80h.

• This instruction adds the data 80h to the contents of the

accumulator and the result is stored in the accumulator itself.
• This addressing mode will be used when the data for the
arithmetic and logical operation is needed only once and is a
constant.
  
Register Direct Addressing
• The register, that contains the data to be manipulated, is specified
in the instruction.

E.g. ADD A, R0.

• This instruction will add the contents stored in register R0 with the
accumulator contents and store the result in accumulator.
• The Registers A, B, DPTR and R0 to R7 are used in Register direct
addressing.
• This addressing mode uses temporary registers which hold the
data for the operation.
 Memory Direct Addressing
• The memory address that contains the data to be operated is
specified here in the instruction.
• E.g. ADD A, 74h.
• This instruction adds the data in accumulator with that stored in
memory address 74h.
• All internal RAM addresses including that of special function
registers can be used in memory direct addressing instructions.
• This addressing mode is used when the data stored in memory is
to be used in arithmetic and logical instructions.
• The data in memory used in the direct addressing can be changed
at any other point in the program.
  
Memory Indirect Addressing
• The register, which contains the actual memory address of the
data, is specified in the instruction.
• The register specified is preceded by @ symbol in assembly
language format.

• E.g. ADD A, @R0. MOVX A, @DPTR

• The value stored in the register R0 is now the address of the

memory location of the data to be fetched.
• From this memory location, the data is fetched and the instruction
is executed
 Memory Indirect Addressing

• The data pointer register (DPTR) is used to access the data in the
external memory with 16-bit addresses.

• E.g. MOVX, A @DPTR

• The indirect addressing mode is very much useful for accessing

data which are continuously stored in memory and accessed
consecutively in program.
  
Indexed Addressing

• In this type of addressing, the instruction consists of two parts - a

base address and an offset.
• This type of addressing is useful in relative memory accessing and
relative jumping.
• The base address is stored in data pointer (DPTR) or any other
register.
• The offset value is stored in Accumulator.

• E.g. MOVC A, @A+DPTR.

  Indexed Addressing
• This instruction adds the contents of the accumulator with the
contents of the data pointer and the result forms the actual
address of the data from where it is fetched. This data is moved
on to the accumulator.

• The indexed addressing mode is useful in accessing data

structures similar to lookup tables. The base address will hold the
address of the starting point of the table and the offset will point
the particular entry in the table.