Chapter 10

Design Input/Output System

Objectives :
At the end of this lesson , students should be able to :
i. Explain how to interface 68000 microprocessor with peripheral device.
ii. Explain the function of buffer and latch and operation.
 Chapter 10
Design Input/Output System

10.1 Introduction
• There are two ways to interface 68000 microprocessor with peripheral
devices.

a) Dedicated I/O
- A specific address is assign to I/O device
- Required a larger package
- Some of the 68000 feature would have be abandoned

b) Memory mapped I/O

- I/O are assumed part of memory
- A memory address is assign to I/O device
- Use of existing address, data and control buses to handle I/O transaction
 Chapter 10
Design Input/Output System

10.2 Memory mapped Input/Output

• Assume I/O is a part of memory.
• Access I/O same as accessing memory
• Need interpreter :

- LATCH : to interface with output

- BUFFER : to interface with input

• Controlling latch and buffer using address decoder circuit.

 Chapter 10
Design Input/Output System

10.2.1 Latch
• Use to interface output device with 68000 microprocessor.
• Example : 74LS574
: (Octal D-Type Positive Triggered Flip-flop)
74LS574 Pin Function

D0 Q0 D0 – D7 connect to data bus of 68000

2 19
D1 18 Q1 Q0 - Q7 connect to output devices such as LED, 7-segment.
3
D2 17 Q2 CP clock pulse where when CP is positive triggered (HIGH to
4
D3 Q3 LOW clock transition), values on D are latched to outputs, Q.
5 16
D4 Q4
6 15 OE* when active (LOW), contents of D are available at outputs Q.
D5 Q5
7 14
D6 Q6
8 13
D7 12 Q7 Input (D0-D7)
9
CP OE* Clock

11 1 Output
 Chapter 10
Design Input/Output System

10.2.1 Latch
• Interfacing latch (output LED) with the decoder

D0 – D7 : Odd address

D8 – D15 : Even address

 Chapter 10
Design Input/Output System

10.2.1 Latch
• Example of program can be use to test connection of LED and latch
; Running Light
LED EQU $E00001 ; depend on the real address system
ORG $1000 ; depend on the real address system
START MOVE.B #%11111110 , D0
AGAIN MOVE.B D0 , LED
BSR DELAY ; delay 1s
ROL.B #1,D0
BRA AGAIN
END

DELAY MOVE.L #384614,D6 ; load D6 with a fixed value

DEL1 SUBI.L #1,D6 ; decrement D6
BNE DEL1 ;is it zero, if not jump back to DEL1
RTS ;it is zero, then exit
 Chapter 10
Design Input/Output System

10.2.1 Latch
• Interfacing latch (output 7-Segmen) with the decoder

Latch
Latch

Common Anode Common Cathode

 Chapter 10
Design Input/Output System

10.2.1 Latch
• Interfacing latch (output 7-Segmen common cathode) with the decoder
 Chapter 10
Design Input/Output System

10.2.1 Latch
• Example of program can be use to test connection of 7 segment and latch

; Display 4 lower bit value at switch to 7 segment

DISPLAY MOVE.B SWITCH , D0

BSR TRANS7
MOVE.B D0 , LED
BRA DISPLAY

TRANS7 ANDI.W #$0F, D0

MOVE.L #CODE7 , A0
MOVE.B 0(A0,D0.B) , D0
RTS

CODE7 DC.B $40 , $79 , $24 , $30 , $19 , $12 , $12 , $02 , $78
DC.B $00 , $18 , $08 , $03 , $46 , $41, $21 , $06 , $0E
 Chapter 10
Design Input/Output System

10.2.1 Latch
• Example of program can be use to test connection of 7 segment and latch
; Display 4 lower bit value at switch to 2 unit 7 segment

DISPLAY MOVE.B SWITCH , D0

MOVE.B D0 , -(SP) ; store temporary in stack pointer
BSR TRANS7
MOVE.B DO , LEDDOWN
MOVE.B (SP)+ ,D0 ; retrieve data back from stack pointer
ASR.B #4, D0 ; shift 4 bit to the right
BSR TRANS7
MOVE.B D0 , LEDUP
BRA DISPLAY

TRANS7 ANDI.W #$0F, D0

MOVE.L #CODE7 , A0
MOVE.B 0(A0,D0.B) , D0
RTS

CODE7 $40 , $79 , $24 , $30 , $19 , $12 , $12 , $02 , $78
$00 , $18 , $08 , $03 , $46 , $41, $21 , $06 , $0E
 Chapter 10
Design Input/Output System

10.2.1 Latch
• Interfacing latch (output 7-Segmen) with the decoder
• 7447 is a BCD to 7-segment decoder/driver
7447

7447
Latch
Latch

7447

7447
Common Anode Common Cathode
 Chapter 10
Design Input/Output System

10.2.1 Latch
• Example of program can be use to test connection of latch and 7-Segment via
decoder 7447

; Display 8 bit value at switch to 2 unit 7 segment via decoder 7447 (BCD tot7 Segment)

DISPLAY MOVE.B SWITCH , D0

CMP.B #99 , D0 ; if D0>99 , ignore it

BCC DISPLAY

AND.L #$FF, D0 ; delete 3 upper byte

DIVU #10,D0 ; convert to decimal
MOVE.L D0 , D1 ; copy to D1
SWAP D0 ; digit SE in D0
ASL.B #4,D1 ; shift decimal digit 4 bit to the left
OR.B D1,D0 ; combine digit decimal with SE
MOVE.B D0,LED ; display
BRA DISPLAY
 Chapter 10
Design Input/Output System

10.2.2 Buffer
• Use to interface input device with 68000 microprocessor.
• Example : 74LS244
: (Octal Buffer with 3-State Output)
74LS244

D0 Q0
2 18
D1 16 Q1
4
D2 Q2 Pin Function
6 14
D3 Q3 D0 – D7 connect to input devices such as switch
8 12
D4 Q4
11 9 Q0 - Q7 connect to data bus of 68000.
D5 Q5
13 7 OE1* when active (LOW), contents of inputs D0-D7 are place to
D6 Q6
15 5 OE2* outputs Q.
D7 3 Q7
17
OE1 OE2

1 19
 Chapter 10
Design Input/Output System

10.2.2 Buffer
• Interfacing buffer with switches (input)

D0 – D7 : Odd address

D8 – D15 : Even address

 Chapter 10
Design Input/Output System

10.2.2 Buffer
• Interfacing buffer with switches (input)
 Chapter 10
Design Input/Output System

10.2.2 Buffer
• Example of program can be use to test input switches

SWITCH EQU $800001 ; depend on the real address system

LED EQU $A00001

ORG $400400
START MOVE.B SWITCH , LED
BRA START
END
 Chapter 10
Design Input/Output System

10.2.3 68230 PI/T

Vcc
Register Select Data bus
Pin Description
RS1 D0 – D7
– RS5
RS1 – RS5 Connected to address bus A1 –
(Register Select) A5 of 68k microprocessor

D0 – D7 Connected to data bus of 68k

PI/T (can be either D0 – D7 or D8 –
D15)

R/W* CS* (Chip Select) Make the chip active.

CS* Connected from address
decoder circuit.
GND R/W* Determine either read or write
(Read/Write) cycle. Connected to pin R/W*
of 68k
 Chapter 10
Design Input/Output System

10.2.3 68230 PI/T

UDS*
LDS*
 Chapter 10
Design Input/Output System

10.2.3 68230 PI/T

• Example :
A system containing a total of 32kByte of ROM with based address $00 0000,
a total of 128kByte of RAM with based address $40 0000 and a PI/T with its
based address, $80 0001. Design a partial address decoder using 74LS138
for this system. Note: This PI/T will occupy the memory map from address $80
0000 until $80 003F. The register select pins, RS1 – RS5, of the PI/T is
connected to A1 – A5 of the microprocessor’s address bus respectively.

Steps :
a) For every chip, determine address range for each component
 Chapter 10
Design Input/Output System

10.2.3 68230 PI/T

ROM
Based address : $000000
Size : 32KB
End address = Based Address + (Size in Hex) - 1
= $000000 + $8000 – 1
= $007FFF
RAM
Based address : $400000
Size : 128KB
End address = Based Address + (Size in Hex) - 1
= $400000 + $20000 – 1
= $41FFFF
PI/T
Start address : $800000
End address : $80003F
 Chapter 10
Design Input/Output System

10.2.3 68230 PI/T

ADDRESS LINES
DEVICES ADDRESS RANGE
A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 $00 0000 Start

ROM 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 $00 7FFF End

0 0 0 * * * * * * X X X X X X X X X X X X X X # TOTAL ROM: 32kB

0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 $40 0000 Start

RAM 0 1 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 $41 FFFF End

0 1 0 * * * * X X X X X X X X X X X X X X X X # TOTAL RAMY: 128kB

1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 $80 0000 Start

PI/T 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 $80 003F End

1 0 0 * * * * * * * * * * * * * * * X X X X X #
 Chapter 10
Design Input/Output System

10.2.3 68230 PI/T

(even) (odd)

(even) (odd)

1 1 PI/T

UDS* LDS*
 Chapter 10
Design Input/Output System

References
i. Antonakos, J. L., The 68000 Microprocessor: Hardware and Software
Principles and Applications 5th edition , Prentice Hall, 2004.

ii. Clements, A., Microprocessor Systems Design: 68000 Hardware, Software,

and Interfacing 3rd edition, PWS, 1997.

iii. Tocci, R. J., Digital Systems: Principles and Applications 9th edition, Prentice
Hall,2004.

iv. Floyd, T. L., Digital Fundamentals 8th edition, Prentice Hall, 2003.

v. Spasov, P., Microcontroller Technology: The 68HC11 and 68HC12 5th edition,

Prentice Hall, 2004.