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DecodersandEncoders Notes

A decoder is a circuit that converts an n-bit binary input into a maximum of 2n unique output lines. Decoders are commonly used for binary-to-octal conversion. Encoders perform the inverse operation of decoders by taking 2n inputs and encoding them into an n-bit binary output. Priority encoders include priority encoding to handle situations where multiple inputs are active simultaneously.

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25 views

DecodersandEncoders Notes

A decoder is a circuit that converts an n-bit binary input into a maximum of 2n unique output lines. Decoders are commonly used for binary-to-octal conversion. Encoders perform the inverse operation of decoders by taking 2n inputs and encoding them into an n-bit binary output. Priority encoders include priority encoding to handle situations where multiple inputs are active simultaneously.

Uploaded by

Rohit
Copyright
© © All Rights Reserved
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Download as PPTX, PDF, TXT or read online on Scribd
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DECODERS

• A decoder is a combinational circuit that converts binary information


from n input lines to a maximum of 2n unique output lines.
• If the n -bit coded information has unused combinations, the decoder
may have fewer than 2n outputs.
• The decoders are called n -to- m -line decoders, where m ≤ 2n.
• Decoders generate the 2n (or fewer) minterms of n input variables
• The name decoder is also used in conjunction with other code
converters, such as a BCD-to-seven-segment decoder.
Consider the three-to-eight-line decoder circuit

 The three inputs are decoded into eight outputs, each representing one of
the minterms of the three input variables.
A particular application of this decoder is binary-to-octal conversion.
 Some decoders are constructed with NAND gates.
 Since a NAND gate produces the AND operation with an inverted output, it becomes
more economical to generate the decoder minterms in their complemented form.
 Furthermore, decoders include one or more enable inputs to control the circuit
operation.
 A two-to-four-line decoder with an enable input constructed with NAND gates is
shown in the next slide.
 The circuit operates with complemented outputs and a complement enable input.
 The decoder is enabled when E is equal to 0 (i.e., active-low enable).
A decoder with enable input can function as a demultiplexer—
 a circuit that receives information from a single line and directs it to one of 2n
possible output lines.
 The selection of a specific output is controlled by the bit combination of n selection
lines.
 The decoder in the previous slide can function as a one-to-four-line demultiplexer
when E is taken as a data input line and A and B are taken as the selection inputs.
 The single input variable E has a path to all four outputs, but the input information is
directed to only one of the output lines, as specified by the binary combination of the
two selection lines A and B . This feature can be verified from the truth table of the
circuit.
 Decoders with enable inputs can be connected together to form a larger decoder circuit.
 Two 3-to-8-line decoders with enable inputs connected to form a 4-to-16-line decoder.
 When w = 0, the top decoder is enabled and the other is disabled.
 The bottom decoder outputs are all 0’s, and the top eight outputs generate minterms
0000 to 0111.
 When w = 1, the enable conditions are reversed:
 The bottom decoder outputs generate minterms 1000 to 1111, while the outputs of
the top decoder are all 0’s.
 A function with a long list of minterms requires an OR gate with a
large number of inputs.
 A function having a list of k minterms can be expressed in its
complemented form F’ with 2n - k minterms.
 If the number of minterms in the function is greater than 2 n/2, then
F’ can be expressed with fewer minterms. In such a case, it is
advantageous to use a NOR gate to sum the minterms of F’.
 The output of the NOR gate complements this sum and generates
the normal output F .
 If NAND gates are used for the decoder, then the external gates
must be NAND gates instead of OR gates.
 This is because a two-level NAND gate circuit implements a sum-of-
minterms function and is equivalent to a two-level AND–OR circuit.
ENCODERS
 An encoder is a digital circuit that performs the inverse operation of a decoder.
 An encoder has 2n (or fewer) input lines and n output lines.
 The output lines, generate the binary code corresponding to the input value.
 An example of an encoder is the octal-to-binary encoder
 It has eight inputs and three outputs that generate the corresponding binary
number.
 It is assumed that only one input has a value of 1 at any given time.
 The encoder above has the limitation that only one input can be active at any given
time.
 If two inputs are active simultaneously, the output produces an undefined combination.
 For example, if D3 and D6 are 1 simultaneously, the output of the encoder will be
111 because all three outputs are equal to 1.
 The output 111 does not represent either binary 3 or binary 6.
 To resolve this ambiguity, encoder circuits must establish an input priority to ensure
that only one input is encoded.
 If we establish a higher priority for inputs with higher subscript numbers, and if both
D3 and D6 are 1 at the same time, the output will be 110 because D6 has higher
priority than D3.
 Another ambiguity in the octal-to-binary encoder is that an output with all 0’s is
generated when all the inputs are 0; but this output is the same as when D0 is equal to1.
 The discrepancy can be resolved by providing one more output to indicate whether
atleast one input is equal to 1.

Priority Encoder

 A priority encoder is an encoder circuit that includes the priority function.


 The operation of the priority encoder is such that if two or more inputs are equal to 1
at the same time, the input having the highest priority will take precedence.
 The truth table of a four-input priority encoder is given in Table below.
Instead of listing all 16 minterms of four variables,
the truth table uses an X to represent either 1 or 0.
For example, X 100 represents the two minterms
0100 and 1100.

 In addition to the two outputs x and y , the circuit has a third output designated
by V
 this is a valid bit indicator that is set to 1 when one or more inputs are equal
to 1.
 If all inputs are 0, there is no valid input and V is equal to 0.
 The other two outputs are not inspected when V equals 0 and are specified as
don’t-care conditions.
 Note that whereas X ’s in output columns represent don’t-care conditions,
 The X ’s in the input columns are useful for representing a truth table in
condensed form.
 The higher the subscript number, the higher the priority of the input.
 Input D3 has the highest priority, so, regardless of the values of the other inputs, when
this input is 1, the output for xy is 11 (binary 3).
 D2 has the next priority level. The output is 10 if D2 = 1, provided that D3 = 0, regardless
of the values of the other two lower priority inputs.
 The output for D1 is generated only if higher priority inputs are 0, and so on down the
priority levels.
Maps for a priority encoder

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