Wa0012
Wa0012
Wa0012
• Background
• Swapping
• Contiguous Memory Allocation
• Segmentation
• Paging
• Structure of the Page Table
• Example: The Intel 32 and 64-bit Architectures
• Example: ARM Architecture
• Program must be brought (from disk) into memory and placed within a
process for it to be run
• Main memory and registers are only storage CPU can access directly
• Logical and physical addresses are the same in compile-time and load-
time address-binding schemes; logical (virtual) and physical addresses
differ in execution-time address-binding scheme
• Logical address space is the set of all logical addresses generated by a
program
• Physical address space is the set of all physical addresses generated by
a program
• To start, consider simple scheme where the value in the relocation register is added to
every address generated by a user process at the time it is sent to memory
– Base register now called relocation register
– MS-DOS on Intel 80x86 used 4 relocation registers
• The user program deals with logical addresses; it never sees the real physical addresses
– Execution-time binding occurs when reference is made to
location in memory
– Logical address bound to physical addresses
• If next processes to be put on CPU is not in memory, need to swap out a process and swap in target process
• Context switch time can then be very high
• 100MB process swapping to hard disk with transfer rate of 50MB/sec
– Swap out time of 2000 ms
– Plus swap in of same sized process
– Total context switch swapping component time of 4000ms (4 seconds)
• Can reduce if reduce size of memory swapped – by knowing how much memory really being used
– System calls to inform OS of memory use via request_memory() and release_memory()
• Other constraints as well on swapping
– Pending I/O – can’t swap out as I/O would occur to wrong process
– Or always transfer I/O to kernel space, then to I/O device
• Known as double buffering, adds overhead
• Standard swapping not used in modern operating systems
– But modified version common
• Swap only when free memory extremely low
• Relocation registers used to protect user processes from each other, and from changing operating-system code
and data
– Base register contains value of smallest physical address
– Limit register contains range of logical addresses – each logical address must be
less than the limit register
– MMU maps logical address dynamically
– Can then allow actions such as kernel code being transient and kernel changing
size
• Best-fit: Allocate the smallest hole that is big enough; must search entire list, unless ordered by size
– Produces the smallest leftover hole
• Worst-fit: Allocate the largest hole; must also search entire list
– Produces the largest leftover hole
First-fit and best-fit better than worst-fit in terms of speed and storage utilization
• First fit analysis reveals that given N blocks allocated, 0.5 N blocks
lost to fragmentation
– 1/3 may be unusable -> 50-percent rule
4
1
3 2
4
• Protection
– With each entry in segment table associate:
• validation bit = 0 illegal segment
• read/write/execute privileges
p d
m-n n
• On a TLB miss, value is loaded into the TLB for faster access next time
– Replacement policies must be considered
– Some entries can be wired down for permanent fast access
• Consider = 80%, = 20ns for TLB search, 100ns for memory access
– EAT = 0.80 x 100 + 0.20 x 200 = 120ns
• Consider more realistic hit ratio -> = 99%, = 20ns for TLB search, 100ns for memory access
– EAT = 0.99 x 100 + 0.01 x 200 = 101ns
• Hierarchical Paging
• A logical address (on 32-bit machine with 1K page size) is divided into:
– a page number consisting of 22 bits
– a page offset consisting of 10 bits
• Since the page table is paged, the page number is further divided into:
– a 12-bit page number
– a 10-bit page offset
• Thus, a logical address is as follows:
p1 p2 d
12 10 10
• where p1 is an index into the outer page table, and p2 is the displacement within the
page of the inner page table
• Known as forward-mapped page table
p1 p2 d
42 10 12
• Each element contains (1) the virtual page number (2) the value of the mapped page frame (3) a pointer to the
next element
• Virtual page numbers are compared in this chain searching for a match
– If a match is found, the corresponding physical frame is extracted
• Rather than each process having a page table and keeping track of all possible logical
pages, track all physical pages
• Entry consists of the virtual address of the page stored in that real memory location,
with information about the process that owns that page
• Decreases memory needed to store each page table, but increases time needed to
search the table when a page reference occurs
• Use hash table to limit the search to one — or at most a few — page-table entries
– TLB can accelerate access