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William Stallings
Computer Organization
and Architecture
9th Edition
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Chapter 4
Cache Memory
Key Characteristics of Computer
Memory Systems
Table 4.1 Key Characteristics of Computer Memory Systems
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Characteristics of Memory Systems
Location
Refers to whether memory is internal and external to the computer
Internal memory is often equated with main memory
Processor requires its own local memory, in the form of registers
Cache is another form of internal memory
External memory consists of peripheral storage devices that are accessible to the
processor via I/O controllers
Capacity
Memory is typically expressed in terms of bytes
Unit of transfer
For internal memory the unit of transfer is equal to the number of electrical lines
into and out of the memory module
Method of Accessing Units of Data
Sequential Random
Direct access Associative
access access
Each addressable location in
A word is retrieved based on
Memory is organized into Involves a shared read-write memory has a unique,
a portion of its contents
units of data called records mechanism physically wired-in
rather than its address
addressing mechanism
Each location has its own
The time to access a given
Individual blocks or records addressing mechanism and
Access must be made in a location is independent of
have a unique address based retrieval time is constant
specific linear sequence the sequence of prior
on physical location independent of location or
accesses and is constant
prior access patterns
Any location can be selected
Cache memories may
Access time is variable Access time is variable at random and directly
employ associative access
addressed and accessed
Main memory and some
cache systems are random
access
Capacity and Performance:
The two most important characteristics of memory
Three performance parameters are used:
Memory cycle time
Access time (latency) Transfer rate
• Access time plus any additional time
• For random-access memory it is the required before second access can • The rate at which data can be
time it takes to perform a read or write commence transferred into or out of a memory unit
operation • Additional time may be required for • For random-access memory it is equal
• For non-random-access memory it is transients to die out on signal lines or to 1/(cycle time)
the time it takes to position the read- to regenerate data if they are read
write mechanism at the desired location destructively
• Concerned with the system bus, not the
processor
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The most common forms are:
Semiconductor memory
Magnetic surface memory
Optical
Magneto-optical
Several physical characteristics of data storage are important:
Volatile memory
Information decays naturally or is lost when electrical power is switched off
Nonvolatile memory
Once recorded, information remains without deterioration until deliberately changed
No electrical power is needed to retain information
Magnetic-surface memories
Are nonvolatile
Semiconductor memory
May be either volatile or nonvolatile
Nonerasable memory
Cannot be altered, except by destroying the storage unit
Semiconductor memory of this type is known as read-only memory (ROM)
For random-access memory the organization is a key design issue
Organization refers to the physical arrangement of bits to form words
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Memory Hierarchy
Design constraints on a computer’s memory can be summed up by
three questions:
How much, how fast, how expensive
There is a trade-off among capacity, access time, and cost
Faster access time, greater cost per bit
Greater capacity, smaller cost per bit
Greater capacity, slower access time
The way out of the memory dilemma is not to rely on a single
memory component or technology, but to employ a memory
hierarchy
+ Memory Hierarchy - Diagram
Cache and Main Memory
Cache/Main Memory Structure
Cache Read
Operation
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Typical Cache Organization
Elements of Cache Design
Table 4.2 Elements of Cache Design
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Cache Addresses
Virtual Memory
Virtual memory
Facility that allows programs to address memory from a logical point of
view, without regard to the amount of main memory physically available
When used, the address fields of machine instructions contain virtual
addresses
For reads to and writes from main memory, a hardware memory
management unit (MMU) translates each virtual address into a physical
address in main memory
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Logical
and
Physical
Caches
Table 4.3
Cache Sizes
of Some
Processors
a
Two values
separated by a slash
refer to instruction
and data caches.
b
Both caches are
instruction only; no
data caches.
Mapping Function
Because there are fewer cache lines than main memory blocks, an
algorithm is needed for mapping main memory blocks into cache
lines
Three techniques can be used:
Direct Associative Set Associative
• The simplest technique • Permits each main memory • A compromise that exhibits
• Maps each block of main block to be loaded into any the strengths of both the
memory into only one line of the cache direct and associative
possible cache line approaches while reducing
• The cache control logic
their disadvantages
interprets a memory address
simply as a Tag and a Word
field
• To determine whether a block
is in the cache, the cache
control logic must
simultaneously examine
every line’s Tag for a match
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Direct
Mapping
Direct Mapping Cache Organization
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Direct
Mapping
Example
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Direct Mapping Summary
Address length = (s + w) bits
Number of addressable units = 2s+w words or bytes
Block size = line size = 2w words or bytes
Number of blocks in main memory = 2s+ w/2w = 2s
Number of lines in cache = m = 2r
Size of tag = (s – r) bits
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Victim Cache
Originally proposed as an approach to reduce the conflict misses of
direct mapped caches without affecting its fast access time
Fully associative cache
Typical size is 4 to 16 cache lines
Residing between direct mapped L1 cache and the next level of
memory
Fully Associative Cache Organization
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Associative
Mapping
Example
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Associative Mapping Summary
Address length = (s + w) bits
Number of addressable units = 2s+w words or bytes
Block size = line size = 2w words or bytes
Number of blocks in main memory = 2s+ w/2w = 2s
Number of lines in cache = undetermined
Size of tag = s bits
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Set Associative Mapping
Compromise that exhibits the strengths of both the direct and
associative approaches while reducing their disadvantages
Cache consists of a number of sets
Each set contains a number of lines
A given block maps to any line in a given set
e.g. 2 lines per set
2 way associative mapping
A given block can be in one of 2 lines in only one set
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Mapping From Main
Memory
to Cache:
k-Way
Set Associative
k-Way
Set
Associative
Cache
Organization
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Set Associative Mapping Summary
Address length = (s + w) bits
Number of addressable units = 2s+w words or bytes
Block size = line size = 2w words or bytes
Number of blocks in main memory = 2s+w/2w=2s
Number of lines in set = k
Number of sets = v = 2d
Number of lines in cache = m=kv = k * 2 d
Size of cache = k * 2d+w words or bytes
Size of tag = (s – d) bits
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Varying Associativity Over Cache Size
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Replacement Algorithms
Once the cache has been filled, when a new block is brought into the
cache, one of the existing blocks must be replaced
For direct mapping there is only one possible line for any particular
block and no choice is possible
For the associative and set-associative techniques a replacement
algorithm is needed
To achieve high speed, an algorithm must be implemented in
hardware
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The four most common replacement
algorithms are:
Least recently used (LRU)
Most effective
Replace that block in the set that has been in the cache longest with no
reference to it
Because of its simplicity of implementation, LRU is the most popular
replacement algorithm
First-in-first-out (FIFO)
Replace that block in the set that has been in the cache longest
Easily implemented as a round-robin or circular buffer technique
Least frequently used (LFU)
Replace that block in the set that has experienced the fewest references
Could be implemented by associating a counter with each line
Write Policy
When a block that is resident in the
There are two problems to contend
cache is to be replaced there are two
with:
cases to consider:
If the old block in the cache has not been
More than one device may have access to main
altered then it may be overwritten with a new
memory
block without first writing out the old block
If at least one write operation has been A more complex problem occurs when
performed on a word in that line of the cache multiple processors are attached to the same
then main memory must be updated by writing bus and each processor has its own local cache
the line of cache out to the block of memory - if a word is altered in one cache it could
before bringing in the new block conceivably invalidate a word in other caches
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Write Through
and Write Back
Write through
Simplest technique
All write operations are made to main memory as well as to the cache
The main disadvantage of this technique is that it generates substantial memory
traffic and may create a bottleneck
Write back
Minimizes memory writes
Updates are made only in the cache
Portions of main memory are invalid and hence accesses by I/O modules can be
allowed only through the cache
This makes for complex circuitry and a potential bottleneck
Line Size
When a block of data
is retrieved and Two specific effects come
placed in the cache into play:
not only the desired As the block size • Larger blocks reduce the number
word but also some increases more useful of blocks that fit into a cache
• As a block becomes larger each
number of adjacent data are brought into additional word is farther from
words are retrieved the cache the requested word
As the block size The hit ratio will
increases the hit ratio begin to decrease as
will at first increase the block becomes
because of the bigger and the
principle of locality probability of using
the newly fetched
information becomes
less than the
probability of reusing
the information that
has to be replaced
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Multilevel Caches
As logic density has increased it has become possible to have a cache on the same
chip as the processor
The on-chip cache reduces the processor’s external bus activity and speeds up
execution time and increases overall system performance
When the requested instruction or data is found in the on-chip cache, the bus access is
eliminated
On-chip cache accesses will complete appreciably faster than would even zero-wait state
bus cycles
During this period the bus is free to support other transfers
Two-level cache:
Internal cache designated as level 1 (L1)
External cache designated as level 2 (L2)
Potential savings due to the use of an L2 cache depends on the hit rates in both the
L1 and L2 caches
The use of multilevel caches complicates all of the design issues related to caches,
including size, replacement algorithm, and write policy
Hit Ratio (L1 & L2)
For 8 Kbyte and 16 Kbyte L1
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Unified Versus Split Caches
Has become common to split cache:
One dedicated to instructions
One dedicated to data
Both exist at the same level, typically as two L1 caches
Advantages of unified cache:
Higher hit rate
Balances load of instruction and data fetches automatically
Only one cache needs to be designed and implemented
Trend is toward split caches at the L1 and unified caches for higher levels
Advantages of split cache:
Eliminates cache contention between instruction fetch/decode unit and execution
unit
Important in pipelining
Pentium
4
Cache
Table 4.4 Intel Cache Evolution
Pentium 4 Block Diagram
Pentium 4 Cache Operating Modes
Note: CD = 0; NW = 1 is an invalid combination.
Table 4.5 Pentium 4 Cache Operating Modes
ARM Cache Features
Table 4.6 ARM Cache Features
ARM Cache and Write Buffer Organization
+ Summary Cache
Memory
Chapter 4
Elements of cache design
Characteristics of Memory Cache addresses
Systems Cache size
Location
Mapping function
Capacity
Replacement algorithms
Unit of transfer
Write policy
Memory Hierarchy Line size
How much? Number of caches
How fast? Pentium 4 cache organization
How expensive?
Cache memory principles ARM cache organization
