Explicitly Parallel Platforms

Dichotomy of Parallel Computing Platforms

• An explicitly parallel program must specify concurrency and
interaction between concurrent subtasks.
• The former is sometimes also referred to as the control structure and
the latter as the communication model.
Control Structure of Parallel Programs
• Parallelism can be expressed at various levels of granularity - from
instruction level to processes.
• Between these extremes exist a range of models, along with
corresponding architectural support.
Control Structure of Parallel Programs
• Processing units in parallel computers either operate under the
centralized control of a single control unit or work independently.
• If there is a single control unit that dispatches the same instruction to
various processors (that work on different data), the model is referred
to as single instruction stream, multiple data stream (SIMD).
• If each processor has its own control control unit, each processor can
execute different instructions on different data items. This model is
called multiple instruction stream, multiple data stream (MIMD).
SIMD and MIMD Processors

A typical SIMD architecture (a) and a typical MIMD architecture (b).

SIMD Processors
• Some of the earliest parallel computers such as the Illiac IV,
MPP, DAP, CM-2, and MasPar MP-1 belonged to this class of
machines.
• Variants of this concept have found use in co-processing
units such as the MMX units in Intel processors and DSP
chips such as the Sharc.
• SIMD relies on the regular structure of computations (such
as those in image processing).
• It is often necessary to selectively turn off operations on
certain data items. For this reason, most SIMD programming
paradigms allow for an ``activity mask'', which determines if
a processor should participate in a computation or not.
Conditional Execution in SIMD
Processors

Executing a conditional statement on an SIMD computer with four

processors: (a) the conditional statement; (b) the execution of the
statement in two steps.
MIMD Processors
• In contrast to SIMD processors, MIMD processors can execute
different programs on different processors.
• A variant of this, called single program multiple data streams (SPMD)
executes the same program on different processors.
• It is easy to see that SPMD and MIMD are closely related in terms of
programming flexibility and underlying architectural support.
• Examples of such platforms include current generation Sun Ultra
Servers, SGI Origin Servers, multiprocessor PCs, workstation clusters,
and the IBM SP.
SIMD-MIMD Comparison
• SIMD computers require less hardware than MIMD computers (single
control unit).
• However, since SIMD processors ae specially designed, they tend to
be expensive and have long design cycles.
• Not all applications are naturally suited to SIMD processors.
• In contrast, platforms supporting the SPMD paradigm can be built
from inexpensive off-the-shelf components with relatively little effort
in a short amount of time.
Communication Model
of Parallel Platforms
• There are two primary forms of data exchange between parallel tasks
- accessing a shared data space and exchanging messages.
• Platforms that provide a shared data space are called shared-address-
space machines or multiprocessors.
• Platforms that support messaging are also called message passing
platforms or multicomputers.
Shared-Address-Space Platforms
• Part (or all) of the memory is accessible to all processors.
• Processors interact by modifying data objects stored in this shared-
address-space.
• If the time taken by a processor to access any memory word in the
system global or local is identical, the platform is classified as a
uniform memory access (UMA), else, a non-uniform memory access
(NUMA) machine.
NUMA and UMA Shared-Address-Space
Platforms

Typical shared-address-space architectures: (a) Uniform-memory

access shared-address-space computer; (b) Uniform-memory-
access shared-address-space computer with caches and
memories; (c) Non-uniform-memory-access shared-address-
space computer with local memory only.
NUMA and UMA
Shared-Address-Space Platforms
• The distinction between NUMA and UMA platforms is important from the point of view of
algorithm design. NUMA machines require locality from underlying algorithms for performance.
• Programming these platforms is easier since reads and writes are implicitly visible to other
processors.
• However, read-write data to shared data must be coordinated (this will be discussed in greater
detail when we talk about threads programming).
• Caches in such machines require coordinated access to multiple copies. This leads to the cache
coherence problem.
• A weaker model of these machines provides an address map, but not coordinated access. These
models are called non cache coherent shared address space machines.
Shared-Address-Space
vs.
Shared Memory Machines
• It is important to note the difference between the terms shared
address space and shared memory.
• We refer to the former as a programming abstraction and to the latter
as a physical machine attribute.
• It is possible to provide a shared address space using a physically
distributed memory.
Message-Passing Platforms
• These platforms comprise of a set of processors and their own
(exclusive) memory.
• Instances of such a view come naturally from clustered workstations
and non-shared-address-space multicomputers.
• These platforms are programmed using (variants of) send and receive
primitives.
• Libraries such as MPI and PVM provide such primitives.
Message Passing
vs.
Shared Address Space Platforms
• Message passing requires little hardware support, other than a
network.
• Shared address space platforms can easily emulate message passing.
The reverse is more difficult to do (in an efficient manner).
Physical Organization
of Parallel Platforms
We begin this discussion with an ideal parallel machine called Parallel
Random Access Machine, or PRAM.
Architecture of an
Ideal Parallel Computer
• A natural extension of the Random Access Machine (RAM) serial
architecture is the Parallel Random Access Machine, or PRAM.
• PRAMs consist of p processors and a global memory of unbounded
size that is uniformly accessible to all processors.
• Processors share a common clock but may execute different
instructions in each cycle.
Architecture of an
Ideal Parallel Computer
• Depending on how simultaneous memory accesses are handled,
PRAMs can be divided into four subclasses.
• Exclusive-read, exclusive-write (EREW) PRAM.
• Concurrent-read, exclusive-write (CREW) PRAM.
• Exclusive-read, concurrent-write (ERCW) PRAM.
• Concurrent-read, concurrent-write (CRCW) PRAM.
Architecture of an
Ideal Parallel Computer
• What does concurrent write mean, anyway?
• Common: write only if all values are identical.
• Arbitrary: write the data from a randomly selected processor.
• Priority: follow a predetermined priority order.
• Sum: Write the sum of all data items.
Physical Complexity of an
Ideal Parallel Computer
• Processors and memories are connected via switches.
• Since these switches must operate in O(1) time at the level of words,
for a system of p processors and m words, the switch complexity is
O(mp).
• Clearly, for meaningful values of p and m, a true PRAM is not
realizable.
Interconnection Networks
for Parallel Computers
• Interconnection networks carry data between processors and to
memory.
• Interconnects are made of switches and links (wires, fiber).
• Interconnects are classified as static or dynamic.
• Static networks consist of point-to-point communication links among
processing nodes and are also referred to as direct networks.
• Dynamic networks are built using switches and communication links.
Dynamic networks are also referred to as indirect networks.
Static and Dynamic
Interconnection Networks

Classification of interconnection networks: (a) a static

network; and (b) a dynamic network.
Interconnection Networks
• Switches map a fixed number of inputs to outputs.
• The total number of ports on a switch is the degree of the switch.
• The cost of a switch grows as the square of the degree of the switch,
the peripheral hardware linearly as the degree, and the packaging
costs linearly as the number of pins.
Interconnection Networks:
Network Interfaces
• Processors talk to the network via a network interface.
• The network interface may hang off the I/O bus or the memory bus.
• In a physical sense, this distinguishes a cluster from a tightly coupled
multicomputer.
• The relative speeds of the I/O and memory buses impact the
performance of the network.
Network Topologies
• A variety of network topologies have been proposed and
implemented.
• These topologies tradeoff performance for cost.
• Commercial machines often implement hybrids of multiple topologies
for reasons of packaging, cost, and available components.
Network Topologies: Buses
• Some of the simplest and earliest parallel machines used buses.
• All processors access a common bus for exchanging data.
• The distance between any two nodes is O(1) in a bus. The bus also
provides a convenient broadcast media.
• However, the bandwidth of the shared bus is a major bottleneck.
• Typical bus based machines are limited to dozens of nodes. Sun
Enterprise servers and Intel Pentium based shared-bus
multiprocessors are examples of such architectures.
Network Topologies: Buses

Bus-based interconnects (a) with no local caches; (b) with local

memory/caches.

Since much of the data accessed by processors is local

to the processor, a local memory can improve the
performance of bus-based machines.
Network Topologies: Crossbars
A crossbar network uses an p×m grid of switches to
connect p inputs to m outputs in a non-blocking manner.

A completely non-blocking crossbar network connecting p

processors to b memory banks.
Network Topologies: Crossbars
• The cost of a crossbar of p processors grows as O(p2).
• This is generally difficult to scale for large values of p.
• Examples of machines that employ crossbars include the Sun Ultra
HPC 10000 and the Fujitsu VPP500.
Network Topologies:
Multistage Networks
• Crossbars have excellent performance scalability but poor cost
scalability.
• Buses have excellent cost scalability, but poor performance scalability.
• Multistage interconnects strike a compromise between these
extremes.
Network Topologies:
Multistage Networks

The schematic of a typical multistage interconnection network.

Network Topologies: Multistage Omega Network

• One of the most commonly used multistage

interconnects is the Omega network.
• This network consists of log p stages, where p is
the number of inputs/outputs.
• At each stage, input i is connected to output j if:
Network Topologies:
Multistage Omega Network
Each stage of the Omega network implements a perfect
shuffle as follows:

A perfect shuffle interconnection for eight inputs and outputs.

Network Topologies:
Multistage Omega Network
• The perfect shuffle patterns are connected using
2×2 switches.
• The switches operate in two modes – crossover or
passthrough.

Two switching configurations of the 2 × 2 switch:

(a) Pass-through; (b) Cross-over.
Network Topologies:
Multistage Omega Network
A complete Omega network with the perfect shuffle
interconnects and switches can now be illustrated:

A complete omega network connecting eight inputs and eight outputs.

An omega network has p/2 × log p switching nodes,

and the cost of such a network grows as (p log p).
Network Topologies:
Multistage Omega Network – Routing
• Let s be the binary representation of the source and d be that of the
destination processor.
• The data traverses the link to the first switching node. If the most
significant bits of s and d are the same, then the data is routed in
pass-through mode by the switch else, it switches to crossover.
• This process is repeated for each of the log p switching stages.
• Note that this is not a non-blocking switch.
Network Topologies:
Multistage Omega Network – Routing

An example of blocking in omega network: one of the messages

(010 to 111 or 110 to 100) is blocked at link AB.
Network Topologies:
Completely Connected Network
• Each processor is connected to every other processor.
• The number of links in the network scales as O(p2).
• While the performance scales very well, the hardware complexity is
not realizable for large values of p.
• In this sense, these networks are static counterparts of crossbars.
Network Topologies: Completely Connected and Star
Connected Networks

Example of an 8-node completely connected network.

(a) A completely-connected network of eight nodes;

(b) a star connected network of nine nodes.
Network Topologies:
Star Connected Network

• Every node is connected only to a common node at the center.

• Distance between any pair of nodes is O(1). However, the central
node becomes a bottleneck.
• In this sense, star connected networks are static counterparts of
buses.
Network Topologies:
Linear Arrays, Meshes, and k-d Meshes

• In a linear array, each node has two neighbors, one to its left and one
to its right. If the nodes at either end are connected, we refer to it as
a 1-D torus or a ring.
• A generalization to 2 dimensions has nodes with 4 neighbors, to the
north, south, east, and west.
• A further generalization to d dimensions has nodes with 2d neighbors.
• A special case of a d-dimensional mesh is a hypercube. Here, d = log
p, where p is the total number of nodes.
Network Topologies: Linear Arrays

Linear arrays: (a) with no wraparound links; (b) with

wraparound link.
Network Topologies:
Two- and Three Dimensional Meshes

Two and three dimensional meshes: (a) 2-D mesh with no

wraparound; (b) 2-D mesh with wraparound link (2-D torus); and
(c) a 3-D mesh with no wraparound.
Network Topologies:
Hypercubes and their Construction

Construction of hypercubes from hypercubes of lower

dimension.
Network Topologies:
Properties of Hypercubes

• The distance between any two nodes is at most log p.

• Each node has log p neighbors.
• The distance between two nodes is given by the number of bit
positions at which the two nodes differ.
Network Topologies: Tree-Based Networks

Complete binary tree networks: (a) a static tree network; and (b)
a dynamic tree network.
Network Topologies: Tree Properties
• The distance between any two nodes is no more than 2logp.
• Links higher up the tree potentially carry more traffic than those at
the lower levels.
• For this reason, a variant called a fat-tree, fattens the links as we go
up the tree.
• Trees can be laid out in 2D with no wire crossings. This is an attractive
property of trees.
Network Topologies: Fat Trees

A fat tree network of 16 processing nodes.

Evaluating
Static Interconnection Networks
• Diameter: The distance between the farthest two nodes in the
network. The diameter of a linear array is p − 1, that of a mesh is 2(
− 1), that of a tree and hypercube is log p, and that of a completely
connected network is O(1).
• Bisection Width: The minimum number of wires you must cut to
divide the network into two equal parts. The bisection width of a
linear array and tree is 1, that of a mesh is , that of a hypercube is
p/2 and that of a completely connected network is p2/4.
• Cost: The number of links or switches (whichever is asymptotically
higher) is a meaningful measure of the cost. However, a number of
other factors, such as the ability to layout the network, the length of
wires, etc., also factor in to the cost.
Evaluating
Static Interconnection Networks
Bisection Arc Cost
Network Diameter
Width Connectivity (No. of links)

Completely-connected

Star

Complete binary tree

Linear array

2-D mesh, no wraparound

2-D wraparound mesh

Hypercube

Wraparound k-ary d-cube

Evaluating Dynamic Interconnection Networks

Bisection Arc Cost

Network Diameter
Width Connectivity (No. of links)

Crossbar

Omega Network

Dynamic Tree
Cache Coherence
in Multiprocessor Systems
• Interconnects provide basic mechanisms for data transfer.
• In the case of shared address space machines, additional hardware is
required to coordinate access to data that might have multiple copies
in the network.
• The underlying technique must provide some guarantees on the
semantics.
• This guarantee is generally one of serializability, i.e., there exists some
serial order of instruction execution that corresponds to the parallel
schedule.
Cache Coherence
in Multiprocessor Systems
When the value of a variable is changes, all its
copies must either be invalidated or updated.

Cache coherence in multiprocessor systems: (a) Invalidate protocol; (b)

Update protocol for shared variables.
Cache Coherence:
Update and Invalidate Protocols
• If a processor just reads a value once and does not need it again, an
update protocol may generate significant overhead.
• If two processors make interleaved test and updates to a variable, an
update protocol is better.
• Both protocols suffer from false sharing overheads (two words that
are not shared, however, they lie on the same cache line).
• Most current machines use invalidate protocols.
Maintaining Coherence
Using Invalidate Protocols
• Each copy of a data item is associated with a state.
• One example of such a set of states is, shared, invalid, or dirty.
• In shared state, there are multiple valid copies of the data item (and
therefore, an invalidate would have to be generated on an update).
• In dirty state, only one copy exists and therefore, no invalidates need
to be generated.
• In invalid state, the data copy is invalid, therefore, a read generates a
data request (and associated state changes).
Maintaining Coherence
Using Invalidate Protocols

State diagram of a simple three-state coherence protocol.

Maintaining Coherence
Using Invalidate Protocols

Example of parallel program execution with the simple

three-state coherence protocol.
Snoopy Cache Systems
How are invalidates sent to the right processors?

In snoopy caches, there is a broadcast media that

listens to all invalidates and read requests and performs
appropriate coherence operations locally.

A simple snoopy bus based cache coherence system.

Performance of Snoopy Caches
• Once copies of data are tagged dirty, all subsequent operations can be
performed locally on the cache without generating external traffic.
• If a data item is read by a number of processors, it transitions to the
shared state in the cache and all subsequent read operations become
local.
• If processors read and update data at the same time, they generate
coherence requests on the bus - which is ultimately bandwidth
limited.
Directory Based Systems
• In snoopy caches, each coherence operation is sent to all processors.
This is an inherent limitation.
• Why not send coherence requests to only those processors that need
to be notified?
• This is done using a directory, which maintains a presence vector for
each data item (cache line) along with its global state.
Directory Based Systems

Architecture of typical directory based systems: (a) a centralized

directory; and (b) a distributed directory.
Performance of
Directory Based Schemes
• The need for a broadcast media is replaced by the directory.
• The additional bits to store the directory may add significant
overhead.
• The underlying network must be able to carry all the coherence
requests.
• The directory is a point of contention, therefore, distributed directory
schemes must be used.
Communication Costs
in Parallel Machines
• Along with idling and contention, communication is a major overhead
in parallel programs.
• The cost of communication is dependent on a variety of features
including the programming model semantics, the network topology,
data handling and routing, and associated software protocols.
Message Passing Costs in
Parallel Computers
• The total time to transfer a message over a network comprises of the
following:
• Startup time (ts): Time spent at sending and receiving nodes (executing the
routing algorithm, programming routers, etc.).
• Per-hop time (th): This time is a function of number of hops and includes
factors such as switch latencies, network delays, etc.
• Per-word transfer time (tw): This time includes all overheads that are
determined by the length of the message. This includes bandwidth of links,
error checking and correction, etc.
Store-and-Forward Routing
• A message traversing multiple hops is completely
received at an intermediate hop before being
forwarded to the next hop.
• The total communication cost for a message of size
m words to traverse l communication links is

• In most platforms, th is small and the above

expression can be approximated by
Routing Techniques

Passing a message from node P0 to P3 (a) through a store-and-

forward communication network; (b) and (c) extending the concept
to cut-through routing. The shaded regions represent the time that
the message is in transit. The startup time associated with this
message transfer is assumed to be zero.
Packet Routing
• Store-and-forward makes poor use of communication
resources.
• Packet routing breaks messages into packets and pipelines
them through the network.
• Since packets may take different paths, each packet must
carry routing information, error checking, sequencing, and
other related header information.
• The total communication time for packet routing is
approximated by:

• The factor tw accounts for overheads in packet headers.

Cut-Through Routing
• Takes the concept of packet routing to an extreme by further dividing
messages into basic units called flits.
• Since flits are typically small, the header information must be
minimized.
• This is done by forcing all flits to take the same path, in sequence.
• A tracer message first programs all intermediate routers. All flits then
take the same route.
• Error checks are performed on the entire message, as opposed to flits.
• No sequence numbers are needed.
Cut-Through Routing
• The total communication time for cut-through
routing is approximated by:

• This is identical to packet routing, however, tw is

typically much smaller.
Simplified Cost Model for
Communicating Messages
• The cost of communicating a message between two
nodes l hops away using cut-through routing is given by

• In this expression, th is typically smaller than ts and tw.

For this reason, the second term in the RHS does not
show, particularly, when m is large.
• Furthermore, it is often not possible to control routing
and placement of tasks.
• For these reasons, we can approximate the cost of
message transfer by
Simplified Cost Model for Communicating
Messages
• It is important to note that the original expression for communication
time is valid for only uncongested networks.
• If a link takes multiple messages, the corresponding tw term must be
scaled up by the number of messages.
• Different communication patterns congest different networks to
varying extents.
• It is important to understand and account for this in the
communication time accordingly.
Cost Models for
Shared Address Space Machines
• While the basic messaging cost applies to these machines as well, a number
of other factors make accurate cost modeling more difficult.
• Memory layout is typically determined by the system.
• Finite cache sizes can result in cache thrashing.
• Overheads associated with invalidate and update operations are difficult to
quantify.
• Spatial locality is difficult to model.
• Prefetching can play a role in reducing the overhead associated with data
access.
• False sharing and contention are difficult to model.
Routing Mechanisms
for Interconnection Networks
• How does one compute the route that a message takes from source
to destination?
• Routing must prevent deadlocks - for this reason, we use dimension-ordered
or e-cube routing.
• Routing must avoid hot-spots - for this reason, two-step routing is often used.
In this case, a message from source s to destination d is first sent to a
randomly chosen intermediate processor i and then forwarded to destination
d.
Routing Mechanisms
for Interconnection Networks

Routing a message from node Ps (010) to node Pd (111) in a three-

dimensional hypercube using E-cube routing.
Mapping Techniques for Graphs
• Often, we need to embed a known communication pattern into a
given interconnection topology.
• We may have an algorithm designed for one network, which we are
porting to another topology.

For these reasons, it is useful to understand mapping between graphs.

Mapping Techniques for Graphs: Metrics
• When mapping a graph G(V,E) into G’(V’,E’), the following metrics are
important:
• The maximum number of edges mapped onto any edge in E’ is called
the congestion of the mapping.
• The maximum number of links in E’ that any edge in E is
• mapped onto is called the dilation of the mapping.
• The ratio of the number of nodes in the set V’ to that in set V is called
the expansion of the mapping.
Embedding a Linear Array
into a Hypercube
• A linear array (or a ring) composed of 2d nodes (labeled 0 through 2d −
1) can be embedded into a d-dimensional hypercube by mapping
node i of the linear array onto node
• G(i, d) of the hypercube. The function G(i, x) is defined as follows:

0
Embedding a Linear Array
into a Hypercube
The function G is called the binary reflected Gray code (RGC).

Since adjoining entries (G(i, d) and G(i + 1, d)) differ from each
other at only one bit position, corresponding processors are mapped
to neighbors in a hypercube. Therefore, the congestion, dilation, and
expansion of the mapping are all 1.
Embedding a Linear Array
into a Hypercube: Example

(a) A three-bit reflected Gray code ring; and (b) its embedding into
a three-dimensional hypercube.
Embedding a Mesh
into a Hypercube
• A 2r × 2s wraparound mesh can be mapped to a 2r+s-node hypercube
by mapping node (i, j) of the mesh onto node G(i, r− 1) || G(j, s − 1) of
the hypercube (where || denotes concatenation of the two Gray
codes).
Embedding a Mesh into a Hypercube

(a) A 4 × 4 mesh illustrating the mapping of mesh nodes to the nodes

in a four-dimensional hypercube; and (b) a 2 × 4 mesh embedded into
a three-dimensional hypercube.

Once again, the congestion, dilation, and expansion of

the mapping is 1.
Embedding a Mesh into a Linear Array
• Since a mesh has more edges than a linear array, we will not have an
optimal congestion/dilation mapping.
• We first examine the mapping of a linear array into a mesh and then
invert this mapping.
• This gives us an optimal mapping (in terms of congestion).
Embedding a Mesh into a Linear Array:
Example

(a) Embedding a 16 node linear array into a 2-D mesh; and (b) the
inverse of the mapping. Solid lines correspond to links in the linear
array and normal lines to links in the mesh.
Embedding a Hypercube into a 2-D Mesh
• Each node subcube of the hypercube is mapped
to a node row of the mesh.
• This is done by inverting the linear-array to
hypercube mapping.
• This can be shown to be an optimal mapping.
Embedding a Hypercube into a 2-D Mesh:
Example

Embedding a hypercube into a 2-D mesh.

Case Studies:
The IBM Blue-Gene Architecture

The hierarchical architecture of Blue Gene.

Case Studies:
The Cray T3E Architecture

Interconnection network of the Cray T3E:

(a) node architecture; (b) network topology.
Case Studies:
The SGI Origin 3000 Architecture

Architecture of the SGI Origin 3000 family of servers.

Case Studies:
The Sun HPC Server Architecture

Architecture of the Sun Enterprise family of servers.