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    Fundamentals of VLSI Chip Design

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    purush
    This document provides an overview of the topics that will be covered in the CSCE 613 fundamentals of VLSI chip design course, including semiconductor theory, MOSFET devices, transistor-level logic gates, integrated circuit fabrication processes, standard cell libraries, and VLSI design rules. The key concepts that will be discussed are the use of MOSFETs as switches to implement logic functions in CMOS circuits, the basic steps used in IC fabrication including photolithography and various deposition/etching processes, and the design rules that define feature sizes and spacing requirements for layout.

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    Fundamentals of VLSI Chip Design

    Uploaded by

    purush
    57 views26 pages
    This document provides an overview of the topics that will be covered in the CSCE 613 fundamentals of VLSI chip design course, including semiconductor theory, MOSFET devices, transistor-level logic gates, integrated circuit fabrication processes, standard cell libraries, and VLSI design rules. The key concepts that will be discussed are the use of MOSFETs as switches to implement logic functions in CMOS circuits, the basic steps used in IC fabrication including photolithography and various deposition/etching processes, and the design rules that define feature sizes and spacing requirements for layout.

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    This document provides an overview of the topics that will be covered in the CSCE 613 fundamentals of VLSI chip design course, including semiconductor theory, MOSFET devices, transistor-level logic gates, integrated circuit fabrication processes, standard cell libraries, and VLSI design rules. The key concepts that will be discussed are the use of MOSFETs as switches to implement logic functions in CMOS circuits, the basic steps used in IC fabrication including photolithography and various deposition/etching processes, and the design rules that define feature sizes and spacing requirements for layout.

    Copyright:

    © All Rights Reserved
    Download as PPT, PDF, TXT or read online from Scribd
    Download as ppt, pdf, or txt
    57 views26 pages

    Fundamentals of VLSI Chip Design

    Uploaded by

    purush
    This document provides an overview of the topics that will be covered in the CSCE 613 fundamentals of VLSI chip design course, including semiconductor theory, MOSFET devices, transistor-level logic gates, integrated circuit fabrication processes, standard cell libraries, and VLSI design rules. The key concepts that will be discussed are the use of MOSFETs as switches to implement logic functions in CMOS circuits, the basic steps used in IC fabrication including photolithography and various deposition/etching processes, and the design rules that define feature sizes and spacing requirements for layout.

    Copyright:

    © All Rights Reserved
    Download as PPT, PDF, TXT or read online from Scribd
    Download as ppt, pdf, or txt
    of 26

    CSCE 613: Fundamentals of VLSI Chip Design

    Instructor: Jason D. Bakos


    Topics for this Lecture
    • Semiconductor theory in a nutshell
    • MOSFET devices as switches
    • Transistor-level logic
    • Logic gates
    • IC fabrication
    • SCMOS design rules
    • Cell libraries

    Fund. of VLSI Chip Design 2


    Elements

    Fund. of VLSI Chip Design 3


    Semiconductors
    • Silicon is a group IV element (4 valence electrons, shells: 2, 8, 18, …)
    – Forms covalent bonds with four neighbor atoms (3D cubic crystal lattice)
    – Si is a poor conductor, but conduction characteristics may be altered
    – Add impurities/dopants (replaces silicon atom in lattice):
    • Makes a better conductor
    • Group V element (phosphorus/arsenic) => 5 valence electrons
    – Leaves an electron free => n-type semiconductor (electrons, negative carriers)
    • Group III element (boron) => 3 valence electrons
    – Borrows an electron from neighbor => p-type semiconductor (holes, positive carriers)

    +- +-
    + + ++ + + --- ---
    P-N junction + + ++ + + --- ---

    forward bias
    reverse bias

    Fund. of VLSI Chip Design 4


    MOSFETs
    • Diodes not very useful for building logic
    • Metal-oxide-semiconductor structures built onto substrate
    – Diffusion: Inject dopants into substrate
    – Oxidation: Form layer of SiO2 (glass)
    – Deposition and etching: Add aluminum/copper wires
    negative
    positive voltage voltage (rel.
    (Vdd) to body)
    (GND)

    NMOS/NFET ---
    PMOS/PFET
    +++
    --- +++
    current current

    body/bulk channel body/bulk


    shorter length,
    GROUND faster transistor HIGH
    (dist. for electrons) (S/D to body is
    reverse-biased)

    Fund. of VLSI Chip Design 5


    FETs as Switches
    • NFETs and PFETs can act as switches
    CMOS
    logic

    bulk
    node not
    shown

    pull-up pull-up
    OFF ON

    pull-down Z 1
    OFF (floating)

    pull-down 0 smokin’!
    ON

    CMOS: assuming PU and


    PN network are perfect
    switches and switch
    simultanously, no current flow
    “and structure” “or structure”
    and no power consumption!

    Fund. of VLSI Chip Design 6


    Logic Gates
    • CMOS: complimentary in form and function
    • NMOS devices (positive logic) form pull-down inv
    network
    • PMOS devices (negative logic) form pull-up YA
    network
    • Implication: CMOS transistor-level logic gates
    implement functions where may the inputs are
    inverted (inverting gates)
    • Add inverter at inputs/outputs to create non-
    inverting gate

    NOR2
    NAND2
    NAND3 Y  A B
    Y  A B Y  A B

    Y  A B
    DeMorgan’s Law

    A B  A  B

    Fund. of VLSI Chip Design 7


    Compound Gates
    • Combine parallel and series structures to form
    compound gates
      
    Y  A B C  D
    – Example:   
    Y  A B C  D

    – Use DeMorgan’s law to determine complement (pull- Y  A  B  C  D


    Y   A  B  C  D
    down network):

    C Y   A  B   C   D

    A B D
    Y
    A C

    Fund. of VLSI Chip Design 8


    Pass Transistors/Transmission Gates
    • NMOS passes strong 0 (pull-down)
    • PMOS passes strong 1 (pull-up)

    Pass transistor: Transmission gate:

    Fund. of VLSI Chip Design 9


    Tristates

    Fund. of VLSI Chip Design 10


    Multiplexer

    Transmission gate multiplexer

    Inverting multiplexer

    Fund. of VLSI Chip Design 11


    Multiplexer

    4-input multiplexer

    Fund. of VLSI Chip Design 12


    Latches

    Positive level-sensitive latch

    Fund. of VLSI Chip Design 13


    Latches

    Positive edge-sensitive latch

    Fund. of VLSI Chip Design 14


    IC Fabrication
    • Inverter cross-section

    field oxide

    Fund. of VLSI Chip Design 15


    IC Fabrication
    • Inverter cross-section with well and substrate contacts

    (ohmic contact)

    Fund. of VLSI Chip Design 16


    IC Fabrication
    • Chips are fabricated using set of masks
    – Photolithography
    • Inverter uses 6 layers:
    – n-well, poly, n+ diffusion, p+ diffusion,
    contact, metal

    • Basic steps
    – oxidize
    – apply photoresist
    – remove photoresist with mask
    – HF acid eats oxide but not photoresist
    – pirana acid eats photoresist

    – ion implantation (diffusion, wells)


    – vapor deposition (poly)
    – plasma etching (metal)

    Fund. of VLSI Chip Design 17


    IC Fabrication

    Furnace used to oxidize (900-1200 C)

    Mask exposes photoresist to light,


    allowing removal
    HF acid etch

    piranha acid etch

    diffusion (gas) or ion implantation


    (electric field)

    HF acid etch

    Fund. of VLSI Chip Design 18


    IC Fabrication
    Heavy doped poly is grown with gas in
    furnace (chemical vapor deposition)

    Masked used to pattern poly

    Poly is not affected by ion implantation

    Fund. of VLSI Chip Design 19


    IC Fabrication

    Metal is sputtered
    (with vapor) and
    plasma etched from
    mask

    Fund. of VLSI Chip Design 20


    Layout Design Rules
    • Design rules define ranges for features
    – Examples:
    • min. wire widths to avoid breaks
    • min. spacings to avoid shorts
    • minimum overlaps to ensure complete overlaps
    – Measured in microns
    – Required for resolution/tolerances of masks

    • Fabrication processes defined by minimum channel width


    – Also minimum width of poly traces
    – Defines “how fast” a fabrication process is

    • Lambda-based (scalable CMOS) design rules define scalable rules based on


     (which is half of the minimum channel length)
    – classes of MOSIS SCMOS rules: SUBMICRON, DEEP SUBMICRON

    Fund. of VLSI Chip Design 21


    Layout Design Rules

    Fund. of VLSI Chip Design 22


    Layout Design Rules
    • Transistor dimensions are in W/L ratio
    – NFETs are usually twice the width
    – PFETs are usually twice the width of NFETs
    • Holes move more slowly than electrons (must be wider to deliver same
    current)

    Fund. of VLSI Chip Design 23


    Layout

    3-input NAND

    Fund. of VLSI Chip Design 24


    Design Flow
    • Design flow is a sequence of steps for design and
    verification
    • In this course:
    – Describe behaviors with VHDL/Verilog code
    – Simulate behavioral designs
    – Synthesize behaviors into cell-level netlists
    – Simulate netlists with cell-delay models
    – Place-and-route netlists into a physical design
    – Simulate netlists with cell-delay models and wire-delay models
    • Need to define a cell library:
    – Function
    – Electrical characteristics of each cell
    – Layout

    Fund. of VLSI Chip Design 25


    Cell Library (Snap Together)

    Layout

    Fund. of VLSI Chip Design 26

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