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Cisc & Risc: Subject-ESD Semester - III Lab Instructor - Shilpa Marathe

The document provides information on CISC and RISC architectures. [1] CISC processors have complex instruction sets that are easier for compilers to use, while RISC processors have reduced instruction sets and operate at higher speeds. [2] CISC eliminates the need for lengthy machine instructions while RISC uses a fixed instruction format and register-based operations. [3] Key differences are that CISC has more instructions, complex decoding and variable formats while RISC has simpler decoding, pipelines better and executes one instruction per cycle.

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Shilpa Marathe
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116 views

Cisc & Risc: Subject-ESD Semester - III Lab Instructor - Shilpa Marathe

The document provides information on CISC and RISC architectures. [1] CISC processors have complex instruction sets that are easier for compilers to use, while RISC processors have reduced instruction sets and operate at higher speeds. [2] CISC eliminates the need for lengthy machine instructions while RISC uses a fixed instruction format and register-based operations. [3] Key differences are that CISC has more instructions, complex decoding and variable formats while RISC has simpler decoding, pipelines better and executes one instruction per cycle.

Uploaded by

Shilpa Marathe
Copyright
© © All Rights Reserved
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
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CISC & RISC

Subject- ESD
Semester- III
Lab Instructor- Shilpa Marathe
What is CISC?

 CISC was developed to make compiler development easier and simpler. The full
form of CISC is Complex Instruction Set Computer. They are chips that are easy
to program that makes efficient use of memory.

 CISC eliminates the need for generating machine instructions to the processor.
For example, instead of having to make a compiler, write lengthy machine
instructions to calculate a square-root distance, a CISC processor offers a built-
in ability to do this.
CISC Architecture
What is RISC?

 RISC is designed to perform a smaller number of types of computer


instruction. Hence, it can operate at a higher speed. The full form of RISC is
Reduced Instruction Set Computers. It is a microprocessor that is designed to
perform smaller number of computer instruction so that it can operate at a
higher speed.

 RISC instruction sets hold less than 100 instructions and use a fixed
instruction format. This method uses a few simple addressing modes that use a
register-based instruction. In this compiler development mechanism,
LOAD/STORE is the only individual instructions for accessing memory.
RISC Architecture
Characteristics of CISC
One instruction is needed to support multiple addressing modes.

 A large number of instructions.


 Instruction-decoding logic will be complex.
 Instructions for special tasks used infrequently.
 A large variety of addressing modes
 It offers variable-length instruction formats.
 Instruction are larger than one-word size.
 Instruction may take more than a single clock cycle to get executed.
 Less number of general-purpose registers as operation get performed in memory
itself.
 Various CISC designs are set up with two special registers for the stack pointer for
managing interrupts
Characteristics of RISC

Here, are an important characteristic of RICS:

 Simpler instruction decoding


 A number of general-purpose registers.
 Simple Addressing Modes
 Fewer Data types.
 A pipeline can be achieved
 One instruction per cycle
 Register-to-register operations
 Simple instruction format
 Instruction execution would be faster
 Smaller Programs
RISC

It has a microprogramming unit. It has a hard-wired unit of programming.

The instruction set has various different instructions that can be used for complex operations. The instruction set is reduced, and most of these instructions are very primitive.

Performance is optimized with emphasis on hardware. Performance is optimized which emphasis on software

Difference between Only single register set

They are mostly less or not pipelined


Multiple register sets are present

This type of processors are highly pipelined

CISC and RISC Execution time is very high Execution time is very less

Code expansion is not a problem. Code expansion may create a problem.

Decoding of instructions is complex. The decoding of instructions is simple.

It requires external memory for calculations It doesn’t require external memory for calculations

Examples of CISC processors are the System/360, VAX, AMD, and Intel x86 CPUs. Common RISC microprocessors are ARC, Alpha, ARC, ARM, AVR, PA-RISC, and SPARC.

Instructions can take several clock cycles Single-cycle for each instruction

More efficient use of RAM than RISC Heavy use of RAM (can cause bottlenecks if RAM is limited)

Simple, standardized instructions Complex and variable-length instructions

A small number of fixed-length instructions A large number of instructions

Limited addressing modes Compound addressing modes

Important applications are Security systems, Home automation. Important applications are : Smartphones, PDAs.

Varying formats (16-64 bits for each instruction). fixed (32-bit) format

Unified cache for instructions and data. Separate data and instruction cac
CISC Advantages
Here, are benefits of CISC

 In CISC it is easy to add new commands into the chip without need to change the
structure of the instruction set
 This architecture allows you to make efficient use of main memory
 The compiler should not be very complicated, as with the case of CISC. The
instruction sets can be written to match the structures of high-level languages.
RISC Advantages

Here, are benefits of RISC

 Complex and efficient machine instructions.


 It offers extensive addressing capabilities for memory management.
 Relatively few registers when compared with RISC processors
 It helps you to reduce the instruction set.
 Offers limited addressing schemes for memory operands
CISC Disadvantages

Here, are Drawbacks of CISC

 Earlier generations of a processor family mostly contained as a subset in every


new version. Hence, instruction set & chip hardware becomes complex with each
generation of computers.
 The performance of the machine slows down because of clock time taken by
different instructions will never be similar.
 They are larger as they require more transistors
RISC Disadvantages

Here, are Cons/Drawbacks of RISC

 The performance of the RISC processors depends on the programmer or


compiler. Compiler plays an important role while converting the CISC code to a
RISC code
 RISC processors have large memory caches on the chip itself.
 RISC architecture necessitates on-chip hardware to be continuously
reprogrammed.
THANK YOU

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