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Problem 1:

Crayon engineering: Debug and recreate a process and mask set

for a polysilicon surface micromachined cantilever

You are a young junior faculty member who has just hired your
first graduate student, Terry Ibelfabber. You have developed an
idea for using a polySi surface-micromachined cantilever that
you’re sure will make you famous and assure your tenure. You ask
Terry to design a process flow for creating this simple structure,
and Terry returns with the process flow detailed in Figure

1. Being a seasoned MEMS designer, you immediately notice

several critical errors with Terry’s process (things that won’t work
or won’t produce the result that Terry shows in his cross sections).
Please find the critical errors in this process flow and, where
possible, suggest alternate approaches. Do not worry about the
accumulation of errors, but rather treat each step assuming that
the structure up to that step could be created.

This structure is actually quite simple to make. Develop a simpler

process flow and associated masks to create the final structure. Be
sure to show cross-sectional and planar views of all key steps in
the process.
Process steps:

1. Start with a silicon wafer.

2. Deposit 1 μm of polysilicon.
3. Perform photolithography using positive photoresist
(not shown) and wet-etch the polySi using KOH.
4. Thermally grow 1 μm of thermal oxide.
5. Perform photolithography using positive photoresist
(not shown) and wet etch the oxide in 49% HF.
6. Deposit 1 μm of polysilicon.
7. Perform photolithography using positive photoresist
(not shown) amd dry etch the polysilicon using SF6
plasma.
8. Release the cantilever by etching the oxide with 49%
HF.
Figure 1. Process flow for a surface-micromachined cantilever.
Problem 2:

Crayon engineering: Create process and mask set for a thermal

bimorph cantilever

A thermal bimorph can be used as an actuator. In this problem,

you will use the principles of “crayon engineering” to design a
process and mask set that will produce a silicon-based cantilever
thermal bimorph with an integrated heater and an underlying
hole structure as shown below. (Silicon-based means that the
final structure is made of silicon, plus oxide, nitride, and metal as
needed. You don’t have to use a plain silicon wafer, but you can’t
make the whole thing out of a completely different material like
metal or SU8.) A description of the structure follows; a top view
is shown in Figure 2. Where a dimension is not specified (like the
lateral extent of the hole), you are free to choose a process that
you think makes sense. This may turn out to be an economic
trade-off (for example, cost of processes vs. wasted space on the
wafer).

Cantilever composition: The cantilever includes a silicon

structure, a metal layer on top of that (you can choose either Al
or Au), an integrated heater to actuate the bimorph, and either
nitride or oxide layer(s) to keep the heater from shorting out to
the bimorph. The order of the layers is not specified up front;
you can pick any order that is buildable.
Silicon cantilever: 100 microns long, 20 microns wide, and 1.5
micron thick

Metal layer: 0.5 microns thick and covers the whole top surface
of the cantilever, to within process biases.

Underlying hole: at least 10 microns deep.

Integrated heater: 0.5 microns thick, made of doped polysilicon.

Make sure that the heater has an accessible contact pad.

Figure 2: Top view of the thermal bimorph cantilever structure

showing the cantilever, metal layer, and polySi heater layers in
no particular order.
(a) When we do crayon engineering, it is useful to identify
the challenges of the process flow (those points where
we must be particularly careful to obey the laws of
physics) early on. Examples could include thermal
compatibility, chemical compatibility, and the ability to
pattern the device geometry. Identify what you see as the
major challenges for this process (a few words each). Pick
three, and explain why they are an issue.

(b) Brainstorm three different ways of approaching the

process, and explain them briefly. You don’t have to have
all of the details ironed out on these approaches.

(c) Choose one approach and flesh it out. You need to sketch
the mask set with key dimensional relations and write out
the steps of the process flow. Specify materials and the
proposed deposition and etch methods, and be sure to
include as steps in your process the required wafer
cleans, application of photoresist, and stripping of
photoresist. If a dimension on the mask affects the
success of the process, make sure you specify it. Be sure
to show cross-sectional and planar views of all key steps
in the process.

Problem 3 : Literature Treasure Hunt

The goal of this problem is to encourage you to learn to use the
library to find real information. You will be given a MEMS device
with certain specifications. Your job is to go to the literature and
find three distinct examples of that device, including the one that
you believe has the best value for the desired specification.

You will evaluate the devices along the following metrics:

Reference(s): Give at least one complete citation to the work that

you are citing, including authors, title, source, year, etc.

• Unpublished material found on the web is not acceptable.

• A combination of patent literature and product specifications is
acceptable for commercial devices.

Affiliation(s): List the affiliation(s) of the authors. Device

description: Describe the design and function of the device. Use
schematics when possible.

Fabrication techniques: Give a brief description of the overall

fabrication approach, use diagrams when possible. Highlight the
major fabrication techniques.

Pros of approach: When compared to the other two devices, what

advantages does this device have (e.g., simpler fab, lower noise,
greater reliability, etc.).

Cons of approach: When compared to the other two devices,

what disadvantages does this device have (e.g., harder fab, higher
noise, worse reliability, etc.).

Value of reported metric: For the specification that you need to

find, what is the value reported in the citation, including
measurement errors or any caveats. You can also report other
performance factors that you find important.

Measurement methods: How did they perform their

measurement?

Confidence in results (1-5), 5 is best, 1 is don’t believe and Why?:

Critically evaluate the results. Do you believe them? Were they
ever repeated? Did they do it right?

Comments: Comment on the device on the overall performance

by considering other performance factors as well. Which one
would you choose to buy among the three?

Three distinct examples typically means devices by different

research groups.
Three devices by the same group may be acceptable if they are
significantly different. Use your judgment.

You can download a word document worksheet from the

assignments section named treasurehunt.pdf. Fill in the
formatted table from the worksheet and submit it on paper with
your homework. Your assigned device and specification is
attached in the device treasure hunt assignments sheet. An
example of the device hunt with two devices is also attached (you
do need to fill all three devices out). This merely serves as an
example; the details you put in the table depend on your
knowledge on the subject as well as technical reading skills.

It is possible to spend a lot of time on this, and still not find the
best. Shrewd searching, using forward searches or review articles,
can save lots of time. However, please use judgment in allocating
a reasonable amount of effort for this problem
 Solutions
Solution 1:

Crayon engineering: Debug and recreate a process and mask set

for a polysilicon surface micromachined cantilever

Proposed process step Error

1. Start with a silicon wafer

2. Deposit 1 μm of polysilicon Must precede with RCA clean.

Also, must have some layer
(such as oxide or nitride)
separating poly from
substrate to serve as a
“stop” layer during etching.

3. Perform photolithography Can't perform KOH etch when

using positive photoresist PR mask is used; PR will lift
(not shown) and wet-etch off immediately. Also, this
the polySi using KOH. step must be followed by
PR removal .
4. Thermally grow 1 μm of Can't grow thermal oxide on
thermal oxide polysilion; the oxide will
eat much of the polysilicon
and the surface will not be
planar since the oxide will
grow much slower in-
between the poly plates.
Deposit oxide instead.
Also, must precede with
RCA clean of wafer.
5. Perform photolithography Can't use 49% HF with PR as a
using positive photoresist mask; the PR will lift off.
(not shown) and wet etch Use BOE instead. Also, this
the oxide in 49% HF. step must be followed by
PR removal. Also, we won’t
get perfect alignment
between the oxide
opening and right edge of
poly 1.
6. Deposit 1 μm of A wafer clean such as Piranha
polysilicon. should precede this
deposition to ensure a
quality deposition
7. Perform photolithography SF6 leads to isotropic etching
using positive photoresist and undercutting, which
(not shown) and dry etch might or might not be an
the polysilicon using SF6 issue depending on the
plasma. dimensions of the
cantilever. Also, we won’t
get perfect alignment
between the left edge of
poly level 2 and the left
edge of oxide cutout. Also,
this step must be followed
by PR removal.
8. Release the cantilever by Must be followed by some
etching the oxide with drying process, as wet
49% HF etching alone will lead to
stiction problems.
Simpler Process:

1. Start with a silicon wafer, perform RCA clean with HF dip.

2. PECVD 1 µm of sacrificial oxide.
3. Perform photolithography using positive photoresist (not
shown) and Mask 1; then wet-etch the oxide using BOE. Then
ash resist and perform RCA clean (without HF dip).
4. LPCVD 1 µm of polysilicon.
5. Perform photolithography using positive photoresist (not
shown) and Mask 2; then dry-etch the polysilicon using
reactive-ion etching. Then ash resist and perform RCA clean
(without HF dip).

6. Release the cantilever by etching the oxide with BOE

followed by super-critical freeze drying.
Figure 1: Simplified process flow & mask set for a surface
micromachined cantilever.
Solution 2:

Crayon engineering: Create a process and mask set for a thermal

bimorph cantilever

a) Some challenges:

1. Order of depositions: the polysilicon must go down before

the metal because of thermal compatibility (poly deposition
is carried at a high temperature)
2. Because of topography concerns, you have to pattern the
films on the cantilever before you etch the hole beneath it.
This requirement makes the organization of the process flow
a bit more challenging and involved. Additionally, the
cantilever, once released, won't be robust enough to tolerate
lithography.
3. A wet etch like KOH would undercut the cantilever effectively,
but you can’t mask it with resist. You must know what
materials will effectively mask the wet etch. A lack of
consideration here can cause inadvertent damage to
structural/functional parts of the device.
4. How do you define a cantilever that is precisely 1.5 microns
thick? You will need to incorporate a thickness-determining
layer into the structure of the wafer.
b) Three approaches:

1. Use an SOI wafer to set the thickness of the cantilever.

Deposit LPCVD nitride to provide electrical isolation between
the cantilever and the polySi heater. Deposit polySifor the
heater, dope it, then perform photolithography and dry etch the
poly, stopping on nitride, defining heater pattern. Strip the
resist, clean the wafer, and deposit LPCVD nitride everywhere to
isolate the heater from metal layer. Deposit aluminum, perform
photolithography, and etch it into the correct shape. Use thin
resist photolithography to mask around the etch hole. Dry etch
the nitride to expose the silicon and open contact pads, then
define the contour of the cantilever by dry etching to the buried
oxide. ( *) Use BOE to remove the exposed oxide. Flip the wafer
over, and dry etch several times to strip blanket films from the
back (nitride, then poly, then nitride). Pattern the back with
thick photoresist, then DRIE through to define cantilever.

2. This option is very similar to the preceding sequence, but it

omits the final DRIE step. Follow the process to point ( *) .
Repattern so that the resist sticks out a little beyond the
cantilever edges, and dry etch the exposed buried oxide. Strip
resist and recoat, patterning so that the resist extends beyond
the cantilever’s Si, covering it entirely (very important.) Use a
XeF2 isotropic dry etch to undercut the cantilever; the cantilever
itself is protected by resist and oxide, while the Si underneath
gets removed.
3. This listing is the approach we will use in part c. Briefly: Grow
doped, KOH resistant Si by epitaxy, deposit nitride, followed by
polysilicon. Dope the poly and then pattern it. Deposit another
layer of nitride and then pattern it to open contact pads. Deposit
a Ti-Au bilayer and use liftoff to define the metal layer. Dry etch
the nitride and the epitaxial silicon to define the cantilever. KOH
etch the substrate to release it. See part c.

c) Using the third approach from above1 , we detail the process

flow here. Key device cross sections, planar views, and the mask
set are shown in Figures 2-4. Note that the cross section taken
(A-A’) is not straight but rather bent around a corner to show the
different critical parts of the device during the fabrication
process.
 Step Description
Starting orientation
Material: Silicon 4” or 6”; (100); 500 µm or 650 µm thick
wafer
Clean Standard RCA.
Deposit nitride LPCVD, thickness = 0.1µm. Used to
electrically insulate the heater from the p+
Si. Will cover both sides of wafer.
Deposit LPCVD, thickness = 0.5 µm. Will act as the
polysilicon heater. Also covers both sides.

Deposit oxide LPCVD, thickness = 0.2 µm. Will act as a

protective shield to poly during the ion
implantation step. Also covers both sides
Dope polysilicon Using ion implantation of Boron. Follow with
and anneal annealing (at ~1000o C) to activate the
implant
Etch oxide BOE for ~ 2 minutes.
Photolithograph Spin cast 1 µm thick positive photoresist,
y prebake; expose MASK 1, develop,
postbake. Mask 1 defines the shape of the
polysilicon heater.
Dry etch Using HBr for example (used by AME5000 in
polysilicon MTL-ICL). HBr etches poly anisotropically. The
heater is now patterned.
Strip PR By ashing for example
Clean Standard RCA
Deposit nitride LPCVD, thickness = 0.1 µm. Used to
electrically insulate the heater from the
metal layer to be deposited next. Will cover
both sides of wafer.
Photolithograph Spin cast 1 µm thick positive photoresist,
y prebake; expose MASK 2, develop, postbake.
Mask 2 is used to open contact pads to the
poly heater.
Dry etch nitride Using CHF3/O2 plasma for example . This
patterns the contact pads into the heater
Strip resist By ashing, for example
Photolithograph Using image reversal resist and MASK 3.
y Thickness of resist about 2 µm (3 times that
of the layer to be lifted off, plus an extra 0.5
µm to counter the step coverage problem
due to the presence of the 0.6 µm poly-
nitride step ). Image reversal (negative) resist
necessary for lift off process later on.
Deposit Ti-Au E-beam evaporation (good for lift-off).
bilayer Thickness of titanium ~ 100 Å, thickness of
gold ~ 0.5 µm. Ti used as adhesion layer

Lift-off Ti-Au Acetone. Follow by water rinse. Now the

bilayer metal layer is patterned.
Clean Using Nanostrip
Photolithography Spin cast 1 µm thick positive photoresist,
prebake; expose MASK 4, develop, postbake.
Mask 4 defines the shape of the cantilever.

Dry etch nitride Using CHF3/O2 plasma for example.

Dry etch epitaxial Using HBr, for example.
Si
Strip resist By ashing, for example.
Etch silicon (from Using KOH and the top (patterned) and
top) bottom nitride layers and metal layer above
the contact pads as masks. Etch 30 µm deep
(etch rate and hence timing for this step
depend on the KOH temperature and
concentration). Since convex corners
become undercut, the cantilever will be
released. We are making the hole deeper
then required to make sure that the
cantilever doesn’t stick to its bottom
because of the wet etc.
Figure 2: Important cross-sectional views
Figure 3: Important planar views

Figure 3: Important planar views

Figure 4: The mask set used for this process along with some key
dimensional constraints