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Boundary Scan

Boundary scan/JTAG allows testing of connections between integrated circuits on a printed circuit board without using test probes. It works by implementing test architecture at the integrated circuit level according to the IEEE 1149.1 standard. The test architecture includes a test access port with signals for a test clock, test mode select, test data input and output, and optional test reset. It also defines instructions for testing interconnects externally and internally, bypassing chips, and controlling output states.

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Mukul Tanwar
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149 views12 pages

Boundary Scan

Boundary scan/JTAG allows testing of connections between integrated circuits on a printed circuit board without using test probes. It works by implementing test architecture at the integrated circuit level according to the IEEE 1149.1 standard. The test architecture includes a test access port with signals for a test clock, test mode select, test data input and output, and optional test reset. It also defines instructions for testing interconnects externally and internally, bypassing chips, and controlling output states.

Uploaded by

Mukul Tanwar
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PPTX, PDF, TXT or read online on Scribd
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BOUNDARY SCAN/JTAG

Boundary-scan, as defined by the IEEE Std.-1149.1 standard, is an integrated method for


testing interconnects on printed circuit boards (PCBs) that are implemented at the integrated
circuit (IC) level.
 The Joint Test Action Group (JTAG) developed a specification for boundary-scan testing that
was standardized as the IEEE Std. 1149.1
The boundary-scan test architecture provides a means to test interconnects between integrated
circuits on a board without using physical test probes
ARCHITECTURE
Test Access Port
• Test Access Port (TAP) includes these signals: ƒ

• Test Clock Input (TCK)


• Clock for test logic „ Can run at different rate from system clock

• ƒ Test Mode Select (TMS)


• Switches system from functional to test mode

• ƒ Test Data Input (TDI)


• Accepts serial test data and instructions -- used to shift in vectors or one of many test instructions

• ƒ Test Data Output (TDO)


• Serially shifts out test results captured in boundary scan chain (or device ID or other internal registers)

• ƒ Test Reset (TRST)


• Optional asynchronous TAP controller reset
JTAG Instructions
 EXTEST
 Test the interconnection between chips.
 INTEST
 Test the internal logic of selected chip.
 BYPASS
 Bypass onechip and forward the test data to next Chip.
 SAMPLE/PRELOAD
 The boundary-scan register is accessible through data scans while the device remains functional. This is also
useful for preloading data into the boundary-scan register without interrupting the device's functional
behavior, prior to executing the EXTEST instruction.
 RUNBIST
 To run comprehensive Built-in Self Test logic.
 CLAMP
 to clamp outputs to predefined logic levels  
 HIGHZ
 To set all outputs to the disabled (high impedance) state.
THANK YOU

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