Unit II

8086 SYSTEM
BUS STRUCTURE
Book :
Yu-Cheng Liu, Glenn A.Gibson, “Microcomputer
Systems: The 8086 / 8088 Family -
Architecture, Programming and Design”,
Second Edition, Prentice Hall of India, 2007.

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 PIN DEFINITIONS

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 Basic
configurations

Minimum and Maximum mode -

8086
Min and Max mode
MINIMIUM MODE -
SIGNALS
MINIMUM MODE INTERFACE
22
Minimum Mode
Signals
–
A Detailed
Description
When the Minimum mode operation is
selected, the 8086 provides all control signals
needed to implement the memory and I/O
interface.
• The minimum mode signal can be divided
into the following basic groups : address/data
bus, status, control, interrupt and DMA.

• Address/Data Bus : these lines serve two

functions. As
address bus is 20 bits long and consists of
signal lines A0 through A19. A19 represents
the MSB and A0 LSB. A 20bit address gives the
8086 a 1Mbyte memory address space. More
over it has an independent I/O address space
which is 64K bytes in length.
Status signal : The four most significant address
lines A19 through A16 are also multiplexed but in
this case with status signals S6 through S3. These
status bits are output on the bus at the same time
that data are transferred over the other bus lines.

• Bit S4 and S3 together from a 2 bit binary code

that
identifies which of the 8086 internal segment
registers are
used to generate the physical address that was
output on
the address bus during the current bus cycle.
 MINIMUM MODE SIGNALS
 Status line S5 reflects the status of another internal
characteristic of the 8086. It is the logic level of the
internal enable flag.

 The last status bit S6 is always at the logic 0 level.

Control Signals – min
mode
• The control signals are provided to support the
8086 memory I/O interfaces.
• They control functions such as when the bus is to
carry a valid address in which direction data are to be
transferred over the bus, when valid write data are on
the bus and when to put read data on the system bus.
 CONTROL SIGNALS - min mode
• ALE is a pulse to logic 1 that signals external
circuitry when a valid address word is on the bus.
This address must be latched in external circuitry
on the 1-to-0 edge of the pulse at ALE.

• • Another control signal that is produced during

the bus cycle is BHE bus high enable. Logic 0 on
this used as a memory enable signal for the most
significant byte half of the data bus D8 through
D1. These lines also serves a second function,
which is as the S7 status line

• Using the M/IO and DT/R lines, the 8086 signals

which type of bus cycle is in progress and in which
direction data are to be transferred over the bus.
Control Signals – min
mode
• The signal read RD and write WR indicates that a read
bus cycle or a write bus cycle is in progress.
• The 8086 switches WR to logic 0 to signal external
device that valid write or output data are on the bus.
• • On the other hand, RD indicates that the 8086 is
performing a read of data of the bus.
• During read operations, one other control signal is also
supplied. DEN ( data enable) and it signals external
devices when they should put data on the bus.
Control Signals – min mode
• READY signal is used to insert wait states into the bus
cycle such that it is extended by a number of clock
periods.
• This signal is provided by an external clock generator
device and can be supplied by the memory or I/O
subsystem to signal the 8086 when they are ready to
permit the data transfer to be completed.
 Interrupt signals – minimum mode
• Interrupt signals : The key interrupt interface
signals are interrupt request (INTR) and interrupt
acknowledge ( INTA).
• • INTR is an input to the 8086 that can be used by an
external device to signal that it need to be serviced
• Logic 1 at INTR represents an active interrupt request.
• When an interrupt request has been recognized by
8086, it indicates this fact to external circuit with pulse
to logic 0 at the INTA output.
 Interrupt signals – minimum mode
• The TEST input is also related to the external interrupt
interface.
• Execution of a WAIT instruction causes the 8086 to
check the logic level at the TEST input.
• • If the logic 1 is found, the MPU suspend operation
and goes into the idle state.
• The 8086 no longer executes instructions, instead it
repeatedly checks the logic level of the TEST input
waiting for its transition back to logic 0.
 Interrupt signals – minimum
• As TEST switches to 0, execution resume
mode
with the next instruction in the program.
This feature can be used to synchronize
the operation of the 8086 to an event in
external hardware.
• • There are two more inputs in the
interrupt interface: non maskable
interrupt NMI and reset interrupt RESET.
• On the 0-to-1 transition of NMI control is
passed to a nonmaskable interrupt service
routine.
• The RESET input is used to provide a hardware
reset for the 8086.RESET = logic 0 initializes the
internal register of the 8086 and initiates a reset
service routine
 DMA Interface signals

• direct memory access - DMA interface of 8086

minimum mode has HOLD and HLDA signals.
• When an external device wants to take control of the
system bus, it signals to the 8086 by switching HOLD
to the logic 1 level.
• At the completion of the current bus cycle, the 8086
enters the hold state. In the hold state, signal lines
AD0 through AD15, A16/S3 through A19/S6,BHE,
M/IO, DT/R, RD, WR, DEN and INTR are all in the high
Z state.
• The 8086 signals external device that it is in this state
by switching its HLDA output to logic 1
36
Type Of Data Transfer in Minimum Mode

M/ IO RD WR Type of
operation
0 0 1 I/O READ
0 1 0 I/O WRITE
1 0 1 MEMORY
READ
1 1 0 MEMORY
WRITE
Minimum Mode Configuration
Minimum Mode 8086 System
•In this mode, all the control signals are given out by
the microprocessor chip itself. There is a single
microprocessor in the minimum mode system.

•The remaining components in the system are latches,

transreceivers, clock generator, memory and I/O
devices.

Some type of chip selection logic may be required for

selecting memory or I/O devices, depending upon the
address map of the system.

Latches are generally buffered output D-type flip-flops

like 74LS373 or 8282. They are used for separating the
valid address from the multiplexed address/data
signals and are controlled by the ALE signal generated
by 8086.
APPLICATIONS OF 8282 LATCH Address should
be latched since
it is available
only during
first part of the
cycle

To signal that
the address is
ready to be
latched a 1 is
put on pin 25,
the address
latch enable
(ALE) pin.
 Minimum mode 8086 system
• • Transreceivers (8286)are the bidirectional buffers and
some times they are called as data amplifiers. They are
required to separate the valid data from the time
multiplexed address/data signals.
• • They are controlled by two signals namely, DEN and
DT/R.
8286 – transceiver(driver/receiver)
The 8286 contains 16
tristate elements, eight
receivers and eight
drivers.

two 8286 are required

in an 8086 system.
 Minimum mode 8086 system
• The DEN signal indicates the direction of data, i.e. from
or to the processor.
• The system contains memory for the monitor and users
program storage.
• • Usually, EPROM are used for monitor storage, while
RAM for users program storage. A system may contain
I/O devices
 Minimum mode 8086 system
• The clock generator generates the clock from the
crystal oscillator and then shapes it and divides to
make it more precise so that it can be used as an
accurate timing reference for the system.
• • The clock generator also synchronizes some external
signal with the system clock
• Ex: 8284 chip
8284 – clock generator
8086 –
maximum mode
• 8086 in maximum-mode configuration, provides signals
Maximumamode
for implementing -introduction
multiprocessor / coprocessor
system environment.
• By multiprocessor environment we mean that one
microprocessor exists in the system and that each
processor is executing its own program.
• • Usually in this type of system environment, there are
some system resources that are common to all
processors- global resources.
• other resources that are assigned to specific
processors. local or private resources.
 Maximum mode
• Coprocessor also means that there is a second
processor in the system. In this two processors do not
access the bus at the same time.
• • One passes the control of the system bus to the other
and then may suspend its operation.
• • In the maximum-mode 8086 system, facilities are
provided for implementing allocation of global
resources and passing bus control to other
microprocessor or coprocessor
Queue status
Maximum Mode Configuration
 S0,S1,S2 – receive
8288 bus controller corresponding
status bits from μP

CLK – i/p
synchronizes bus
controller activity
with μP

CEN,IOB AEN –
are for
multiprocessor
systems

In a single
processor
Pin OtherDefinition
pin definitions
INTA Interrupt acknowledgement
IORC I/O read command, instructs the I/O
interface to put data contained in the
addressed port on data bus

I/O Write command, instructs the I/O

IOWC interface to accept data on the data bus
and put data into the addressed port

Memory read command, instructs the

MRDC memory to put the contents of addressed
location on data bus
Memory write command, instructs the
MWTC memory to accept data on the data bus
and put data into the addressed memory
location
8086 – maximum mode
 System Bus
Timing
Unit II
8086 – SYSTEM BUS STRUCTURE

Book :
Yu-Cheng Liu, Glenn A.Gibson, “Microcomputer Systems: The 8086 / 8088
Family - Architecture, Programming and Design”, Second Edition, Prentice
Hall of India, 2007.
Typical system bus architecture
Timing Diagrams
 Typical sequence of bus cycles

Length of a bus cycle = 4 clock cycles + wait states

Set up & hold time
Wait State
8086 - read cycle
8086 - write cycle
Bus timing
8086 minimum mode bus timing diagrams -
input

• During T1 – ALE –high,DEN = 1,DT/R =0

• At trailing edge of ALE,8282 latches address
• During T2,address is dropped,s3 to s7 – output on
AD16/S3 to AD19/S6 and BHE/S7 ,DEN is lowered to
enable 8286 transceivers
• For input ,RD is activated low
• During T3,Data is put on bus
• After input data is accepted by µP, RD = 1
8086 minimum mode bus timing diagrams -
input
8086 minimum mode bus timing diagrams -
output
 INTA CYCLE – MINIMUM MODE
• If an interrupt request has been recognized during
previous cycle & an instruction has been completed,
then a –ve pulse is applied to INTA during current bus
cycle & next cycle

• Pulses extend from T2 to T4

• The I/F accepting the ACK,puts INTERRUPT TYPE on

AD7-AD0 which will be available from T2 to T4
INTA cycle
Bus request and bus grant timing on a
minimum mode system The HOLD pin is tested
at the leading edge of
each clock pulse.

If a HOLD signal is
received by the processor
before T4 or during a T1
state, then the CPU
activates HLDA and the
succeeding bus cycle will
be given to the requesting
master until that master
drops its request.

The lowered request is

detested at the rising edge
 8086 -maximum mode -bus timing diagrams
- input

• S0,S1,S2 – SET prior to beginning of bus cycle

• During T1 ,8288 Bus Controller- outputs a pulse on ALE
• During T2,8288 sets DEN=1,enables transceivers
• For i/p ,it activates MRDC or IORC.These signals are
maintained till T4
• S0,S1,S2 – ACTIVE until T3,passive during T3,T4
8086 -maximum mode bus timing diagrams -
input
8086 -maximum mode bus timing diagrams -
output

For O/p ,it activates MWTC or IOWC from T3 to T4

 Maximum mode – bus grant
RQ/GT is done in
sequence of 3 pulses
RQ/GT are examined
at the rising edge of
each clock pulse, if a
request is detected ,µP
will apply a grant
pulse to RQ/GT
Immediately following
next T4 or T1
RQ/GT0 has higher
priority
Bus grant – maximum mode

• REQUESTING MASTER gets the

bus control for one or more bus
cycles.It sends release pulse to µP
over the same line as it had sent
request

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 Multiprocessor
Configuration
UNIT 2

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MULTIPROCESSOR
• Multiprocessor Systems refer to the use of
multiple processors that executes
instructions simultaneously and
communicate with each other using mail
boxes and Semaphores.

5/4/22 75
Multiprocessor Configurations

• Maximum mode of 8086 is

designed to implement 3 basic
multiprocessor configurations:
• 1. Coprocessor (8087)
• 2. Closely coupled (8089)
• 3. Loosely coupled (Multibus)

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FEATURES

• Coprocessors and Closely

coupled configurations are
similar in that both the 8086 and
the external processor shares the:
• Memory
• I/O system
• Bus & bus control logic
• Clock generator

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Coprocessor / Closely Coupled
Configuration

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COPROCESSOR

• Ex: 8086 has no instructions

for performing floating point
arithmetic, so 8087 – Numeric
Data Processor can be its
coprocessor
• Both coprocessor and CPU execute
their instructions from the same
program, which is written in
superset of 8086 instruction set

5/4/22 79
TEST pin of 8086

• Used in conjunction with

WAIT instruction in
multiprocessing
environments.
• This is input from the
8087 Coprocessor.
• During execution of a wait
instruction, the CPU checks
this signal.
• If it is low, execution of
the signal will continue; if
5/4/22 80
1.Coprocessor Execution
Coprocessor cannot take control of the bus, it does
everything through the CPU

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 Interaction b/w CPU & COP
• ESC – instruction to be executed by COP is indicated when ESC
appears in PGM sequence
• Only HOST CPU can fetch instn
• Cop receives all instructions ,monitors instn seq of host
• ESC has external op code – tells what a COP has to do
• Esc – decoded by both CPU,COP

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Interaction b/w CPU & COP

• COP sends BUSY signal to host’s TEST pin

• Host CPU executes WAIT,until its TEST pin is
activated by COP
• COP must monitor host CPU status on
S2,S1,S0 & AD0-AD15 for fetched instn
• Instn stream should be monitored by
QS1,QS0
• COP maintains Instruction queue close to
CPU

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ESC INSTRUCTION

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5/4/22 85
 2.Closely Coupled Execution
• Closely Coupled processor – independent
processor
• To mimimize cost,independent processor can be
tied to CPU to form closely coupled system in
which both share same clock and bus control
logic independently

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Interprocessor communciation

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5/4/22 88
5/4/22 89
3.Loosely Coupled
Configuration
• has shared system bus, system memory, and
system I/O.
• each processor has its own clock as well as its
own memory (in addition to access to the
system resources).
• Used for medium to large multiprocessor
systems.

5/4/22 90
3.Loosely Coupled
Configuration
• Each module is capable of being
the bus master.
• Any module could be a processor
capable of being a bus master, a
coprocessor configuration or a
closely coupled configuration

5/4/22 91
 Loosely Coupled Configuration
• No direct connections between the
modules. Each share the system bus and
communicate through shared
resources.
• Processor in their separate modules can
simultaneously access their private
subsystems through their local busses,
and perform their local data references
and instruction fetches independently. This
results in improved degree of
concurrent processing.
5/4/22 92
Advantages of Multiprocessor

• 1. High system throughput can

be achieved by having more
than one CPU.
• 2. The system can be expanded
in modular form.
• Each bus master module is an
independent unit and normally
resides on a separate PC board.

5/4/22 93
 Advantages of Multiprocessor
• One can be added or removed without
affecting the others in the system.
• A failure in one module normally does
not affect the breakdown of the entire
system and the faulty module can be
easily detected and replaced
• Each bus master has its own local bus to
access dedicated memory or IO devices.
So a greater degree of parallel
processing can be achieved.

5/4/22 94
Loosely Coupled
Configurations
• In a loosely coupled multiprocessor
system, more than one bus master
module may have access to the
shared system bus.
• Since each master is running
independently, extra bus control logic
must be provided to resolve the bus
arbitration problem
• This extra logic is called bus access logic
and it is its responsibility to make sure
that only one bus master at a time has
control of the bus.
• Simultaneous bus requests are
resolved on a priority basis. There are
three schemes for establishing
priority:
5/4/22 95
5/4/22 96
5/4/22 97
 SUMMARY
• In summary, processing modules of different
configurations may be combined to form a complex,
loosely coupled multiprocessor system.Each module in
such a system may be:

1. A single 8086 or 8088 or an independent processor

such as an 8089.
2. A cluster of processors consisting of an 8086 or 8088
and a coprocessor (such as an 8087) and/or
independent processors.
3. A cluster of independent processors (such as two
8089s).

• In addition, each module may include a local bus or a

dedicated I/O bus.
5/4/22 98
5/4/22 99
 Introduction
to
Advanced Microprocessors

Unit II
8086/8088, 80186/80188, 80286,
80386, 80486, Pentium, Pentium Pro Processor,
Pentium Ⅱ, Pentium Ⅲ, Pentium 4
Architecture, Programming,
and Interfacing - 6 Ed. -
Barry B. Brey

100
Intel family of
microprocessor,s bus and
memory sizes

101
80186/80188
• High-Integration CPUs
• schematic diagram for IBM’s original PC
• 8088 microprocessor
• several additional chips are required
• 80186 = 8086 + several additional chips
• added 9 new instructions
• clock generator
• programmable timer
• programmable interrupt controller
• circuitry to select the I/O devices

102
103
80286 (1982)
• some instruction executed : 250ns(4.0MIPS) at 8MHz
• 24-bit address bus : 16M byte memory
• added 16 new instructions
• Real Mode: 1st powered on
• functions exactly like an 8086
• uses only its 20 least significant address lines(1M)
• Protected :
• A “Fatal Flaw” ?
• once switched to Protected mode, should not be able to
switch back to Real mode
• 286 chips are operated in Real mode and thus function only
as fast 8086s
• IBM AT(advanced technology) Computer :1984

104
105
 80386
• flexible 32-bit Microprocessor(1986) : data bus, registers
• very large address space : 32-bit address bus(4G byte
physical)
• 64 terabyte virtual
• 4G maximum segment size
• integrated memory management unit
• virtual memory support, optional on-chip paging
• 4 levels of protection
• added 16 new instructions
• Real Mode, Protected mode
• Virtual 8086 mode : in a protected and paged system
• 386SX : 16-bit external data bus, 24-bit address bus
• 386EX : 16-bit external data bus, 26-bit address bus
• 1995, called embedded PC
106
107
80486

• Intel released 80486 in 1989

• maintaining compatibility : standard(8086,286,386)
• polished & refined 386 : twice as fast as 386
• redesigned using RISC concept :
• frequently used instruction : a single clock cycle
• new 5-stage execution pipeline
• highly integrated
• 8K memory cache
• floating-point processor(equivalent of the external 387)
• added 6 new instructions : for used by OS

108
109
 80486

• 486SX :
• for low-end applications that do not require a coprocessor or
internal cache
• clock speed limited 33MHz
• 486DX2 & DX4 :
• internal clock rate is twice or 3 times external clock rate
• 486DX4 100 : internal 100MHz, external 33MHz
• Overdrive Processor:
• 486DX2 or DX4 chips with overdrive socket pin-outs
• to upgrade low-speed 486DX, SX with 486DX2, DX4

110
Pentium
• increasing the complexity of the IC: to scale the chip
down
• if every line could be shrunk in half, same circuit could be
built in one-forth the area
• Superscaler : support 2 instruction pipelines(5 stage)
• ALU, address generation circuit, data cache interface
• actually execute two different instruction simultaneously
• Pentium(1993) : originally labeled P5(80586)
• 60, 66MHz(110MIPS)
• 8K code cache, 8K data cache
• coprocessor : redesign(8-stage instruction pipeline)
• external data bus : 64 bit(higher data transfer rates)
• added 6 new instructions : for used by OS
111
112
113
114
Pentium pro
• codenamed P6 : 1995 ‘basic clock frequency : 150,
166MHz
• two chips in one : two separate silicon die
• processor(large chip), 256K level two cache
• Superscaler processor of degree three(12 stage)
• internal cache :
• level one(L1) : 8K instruction and data cache
• level two(L2) : 256K(or 512K)
• 36-bit address bus : 64G byte memory
• has been optimized to efficiently execute 32-bit code
• bundled with Windows NT : server market

115
PentiumⅡand PentiumⅡXeon Microprocessor
• PentiumⅡmicroprocessor released in 1997

• PentiumⅡ module : small circuit board

• Pentium pro with MMX : no internal L2 cache
• 512K L2 cache(operated at speed of 133MHz)
• main reason :
• L2 cache found main board of Pentium : 60, 66MHz
• not fast enough to justify a new microprocessor
• Pentium pro : not well yield
• 266~333MHz with 100MHz bus speed : in 1998
• bottleneck : external bus speed 66MHz
• use of 8ns SDRAM :
116
PentiumⅡand PentiumⅡXeon Microprocessor
• new version of PentiumⅡcalled Xeon : mid-1998
• for high-end workstation and server applications
• main difference from PentiumⅡ :
• L1 cache size : 32K bytes
• L2 cache size : 512K, 1M, 2M
• change in Intel’s strategy :
• professional version and home/business version of
PentiumⅡ microprocessor

117
Pentium Ⅲ Microprocessor
• 1. used faster core than PentiumⅡ
• is still P6 or Pentium pro processor
• 2. Two version :
• bus speed : 100MHz
• 1. slot 1 version mounted on a plastic cartridge
• 512K cache : one-half the clock speed
• 2. socket 370 version called flip-chip : looks like the
older Pentium package → Intel claim cost less
• 256K cache : clock speed
• 3. clock frequency : 1 GHz

118
Pentium 4 Microprocessor
• release in late 2000 : used Intel P6 architecture
• main difference :
• 1. clock speed : 1.3, 1.4, 1.5 GHz
• 2. support to use RAMBUS memory technology
• DDR(double-data-rate) SDRAM : both edge
• 3. interconnection : from aluminum to copper
• copper : is better conductor → increase clock frequency
• bus speed : from current max. of 133MHz to 200MHz or
higher

119
120
 Multiprocessor systems - 8087
 A system having two microprocessor will require only lesser time to complete
the task.

 The study of a system, involving several connected microprocessors, using a

certain topology to further enhance the speed of operation is called
Multimicroprocessor Architecture.

 Multimicroprocessor system consist of

• CPU
• Numeric Data Processor ( NDP ) Or / And
• Input / Output processor ( IOP )

121
 Multiprocessor Configurations

Numeric Data Processor :

 Independent Processing Unit.

 Perform complicated numeric calculation in

comparatively less time.

 Works in coherence with the main processor.

Input / Output Processor :

 Take care of I/O activities of the system.

122
Coprocessor
 A computer processor used to supplement the function of
primary processor.

 First seen on mainframe computers.

 Accelerate the system performance.

 Operation performed :

 Floating point arithmetic

 Graphic & Signal processing.
 String processing.
 Encryption

 They are Unable to fetch the code from the memory so they
work under the control of main processor .

 Both microprocessor and coprocessor can execute their

respective instructions simultaneously and concurrently.
123
Architecture
of 8087

124
Intel 8087
 Numeric Processor.
 Packed in 40 pin ceramic DIP package.
 Available in 5 MHz, 8MHz, 10MHz versions compatible with
8086, 8088, 80186, 80188.
 It adds 68 new instruction to the instruction set of 8086.

How it works :

 The 8087 instruction may lie interleaved in the 8086

program, but it is the task of 8086 to identify the 8087
instructions from the program, send it to 8087 for further
execution & after the completion of execution cycle the
result may be referred back to CPU.

 Operation of 8087 does not require any software support

from the system software or operating system.
125
Architecture of 8087

126
Two major sections:
1) Control unit
2) Numeric Execution unit

Control Unit :
Function :
 It interface the coprocessor to the
microprocessor – system data bus.
 Monitors the instruction stream.
 If the instruction is an ESCape (coprocessor)
instruction, the coprocessor executes it; if not
the microprocessor executes it.
 It receives , decodes instructions, read and
write memory operands and executes the 8087
instruction.
127
Numeric Execution Unit (NEU)
Functions :
 Execute all the numeric processor instructions.

 It has 8 register (80 bit) stack that holds the operands for
arithmetic instructions & the result.

 Instruction either address data in specific stack data –

register or uses push and pop mechanism to store and
retrieve data.

Programmable shifter :

 Responsible for shifting the operands during the execution

of instruction like FMUL and FDIV.

128
Microcode control unit :

 It generates the control signals required for the execution

of instruction.

The internal data bus is 84 bits wide including 68

bit fraction, 15 bit exponent and a sign bit.

129
Status word of 8087

130
1) B – busy bit
 Indicates the coprocessor is busy in executing a
task.
2) C3- C0 (Condition code bits)
 Indicates the condition of the coprocessor.
3) TOP ( Top-of-stack (ST))
 Indicates the current register addressed as the top-
of-the stack (ST). Normally register 0.
4) ES – error summary
 Bit is set if any unmasked error bit (PE,UE,OE, ZE,
DE or IE) is set.
5) PE – precision error
 Indicate the result or operand exceed the selected
precision. 131
6) UE – Underflow Error
 Indicates a non zero result that is too small to
represent with the current precision selected.
7) OE – Overflow Error
 Indicates a result is too large to be represented.
8) ZE – Zero Error
 Indicates the divisor was zero while the
dividend is a non-infinity or non zero number.
9) DE – Denormalized error
 Indicates that at least one of the operands is
denormalized.

10) IE – Invalid Error

 Flag indicates errors such as those produced by
taking the square root of negative number.

132
Control Word Register of 8087

133
 Control register

 FLDCW – instruction which is used to load a value into

the control register.
1) IC – Infinity Control
 Selects either affine ( allows positive and negative
infinity) or projective (assumes infinity is unsigned)

2) RC – Rounding Control

 Determines the type of rounding.

 00 - round to nearest even.
 01 - round down towards minus infinity.
 10 - round up towards plus infinity.
 11 - chop or truncate toward Zero.

134
3) PC – Precision Control
 Sets the precision of the result.
 00 -> Single precision (short)
 01 -> Reserved
 10 -> Double – precision (long)
 11 -> Extended precision (temporary)
4) Exception Masks
 Determine whether the error indicated by the
exception affects the error bit in the status flag.

5) Zero Divide
 If any non zero finite operand is divided by zero, this
exception is generated.
6) Denormalized Operand
 Exception is generated if at least one of the operand
or the result is denormalized.

135
Signal Description
of 8087

136
Pin Diagram of 8087

137
1) AD0 - AD15 :
 These are time multiplexed address / data lines.
 Lines carry address during T1 and data during T2 T3
Tw &T4 states.

2) A19/S6 – A16/S3 :
 These are time multiplexed address/ status lines.
 These function in a similar way to the
corresponding pins of 8086.
 S6 ,S4 & S3 are permanently high, while the S5 is
permanently low.

3) BHE / S7 :
 During t1 the BHE / S7 pin is used to enable data on
to the higher byte of the 8086 data bus.
 During T2 ,T3 , Tw and T4 this is a status line S7.
138
4) Qs1 , Qs0 :

 Qs1 , Qs0 are queue status input signals.

 These enable 8087 to keep track of the instruction

prefetch queue status of the CPU, to maintain
synchronism with it.

 Qs1 Qs0 Queue Status

0 0 No operation.
0 1 First byte of opcode from queue
1 0 Empty Queue
1 1 Subsequent byte from
queue.

139
5) INT

 Used to indicate that an unmasked exception has

been received during execution.
 This is usually handled by 8259A.

6) BUSY

 It will be set when 8087 is busy with the execution

of an allotted instruction.

7) READY

 Used to inform the coprocessor that the address device

will complete the data transfer from its side and the bus
is likely to be free for the next bus cycle.
 Usually this is synchronized by the clock generator 8284

140
8) RESET
 Used to abandon the internal activities of the
coprocessor and prepare it for further execution.

9) CLK
 It provide the basic timing for the processor
operation.

10) VCC
 A +5V supply

11) GND
 A return line for the power supply. 141
12) S2 ,S1 and S0
These can be either be 8087 driven (output) or
s2 externally
S1 driven (input)
S0 by theQueue
CPU status

0 X X unused

1 0 0 Unused

1 0 1 Memory read

1 1 0 Memory write

1 1 1 passive

142
13) RQ / GT0
 The request / grant pin is used to gain control of the
bus from the host (8086/ 8088) for operand transfer.

 An active low pulse of one clock duration is generated

by 8087 for the host to inform it that it wants to gain
control of the local bus either for itself or for other
coprocessor connected to RQ/ GT1 pin of 8087.

 The 8087 waits for the grant pulse from the host.

 When it is received, it either initiates a bus cycle if

the request is for itself or else, it passes the grant
pulse to RG/GT1, if the request is for the other
coprocessor. 143
14) RQ / GT1
 Bidirectional pin
 Used by other bus masters to convey their need of
the local bus access to 8087.

144
Interconnections of 8087 with 8086/ 8088

145
Interconnection of 8087 with CPU :

 8087 can be connected with 8086 /80188 only in

their maximum mode of operation, ie only when the
MN/ Mx pin of CPU is grounded.

 In maximum mode all the control signals are derived

using a separate chip known as a bus controller.

 For 8086 and 80188/ 80186 the compactable bus

controller are 8288 and 82188 respectively.

 The busy pin of 8087 is connected with the TEST pin

of the CPU.

 In 8086/8088 the QS0 &QS1 lines may be directly

connected to the corresponding pins. 146
Interconnection of 8087 with CPU :

 8087 can be connected with 8086 /80188 only in

their maximum mode of operation, ie only when the
MN/ Mx pin of CPU is grounded.

 In maximum mode all the control signals are derived

using a separate chip known as a bus controller.

 For 8086 and 80188/ 80186 the compactable bus

controller are 8288 and 82188 respectively.

 The busy pin of 8087 is connected with the TEST pin

of the CPU.

 In 8086/8088 the QS0 &QS1 lines may be directly

connected to the corresponding pins. 147
 In case of 8086 / 8088 based system the RQ/ GT0 of
8087 may be connected to RQ / GT1 of 8086/ 8088.

 The clock pin of 8087 may be connected with the CPU

8086/ 8088 clock input.

 The interrupt output of 8087 is routed to 8086/8088

via a programmable interrupt controller.

 The pins AD0 – AD15 , RESET , A19 /S6 - A16 /S3 , BHE / S7
are connected to the corresponding pin of 8086/8088.

 In case of 80186/ 80188 system the RQ/ GT lines of

8087 are connected with the corresponding RQ / GT
lines of 82188. 148
Instruction set of 8087

 The execution of 8087 instruction is

transparent to the programmer.

 The instructions are fetched by 8086 but are

executed by 8087.

 Whenever the 8086 comes across 8087

instruction, it executes the ESCAPE instruction
code to pass over the instruction op-code and
control of the local bus to 8087.

 After execution the result is referred back.

149
Categorization of Instruction set

1. Data transfer Instructions.

2. Arithmetic Instructions
3. Comparison Instructions
4. Transcendental Operations
5. Constant Operations.
6. Coprocessor Control Operations

150
1) Data Transfer Instruction

 Depending on the data type handled these are

further grouped into Three :
 Floating point Data Transfer
 Integer Data Transfer
 BCD Data Transfer

 Floating Point Data Transfer

1. FLD (Load real to top of Stack)

 This instruction loads a real operand to the
top of stack of the 80 bit register.

FLD ST (7) ; Stack top  [Reg 7]

FLD MEM ; Stack Top  [MEM]
151
 2) FST (Store Top of the Operand )
 This instruction stores current content of the top of stack
register to the specified operand.
 FST ST(7) ; Stack top  [ ST (7) ]
 FST MEM ; stack Top  [MEM]

3) FXCH (exchange with Top of Stack)

 This instruction exchanges the content of the top of stack
with the specified operand register.
 FXCH ST (6) ; stack top  ST (6)
Integer data transfer Instruction :
1) FILD (Load integer to stack top)
 This instruction loads the specified integer data operand to
the top of stack.
FILD ST(5) ; stack Top  ST (5)

152
 2) FIST/FISTP
 The instruction work in exact similar manner as FST/ FSTP
except the fact that the operand are integer operand.

BCD Data Transfer Instructions :

 FBLD & FBSTP
 Both work in an exactly similar manner as FLD and FSTP
except for the operand type BCD

153
Arithmetic Instructions

1. FADD
2. FSUB
3. MUL
4. FDIV
5. FSQRT
6. FABS

154
 Transcendental Instructions

The operand usually are ST(0) and ST(1) or only ST(0)

 FPTAN :
 Instruction calculates the tangent of an angle “O”, where
“O”, must be in range from 0<= “O” < 900 { ST/ST(1) }
 The value of “O” must be stored at the stack top.

 FPATAN :
 Instruction calculates the inverse tangent
 The result is stored on the top of the stack.
 The content of ST and ST(1) should follow the inequality.
0<=ST(1) < ST< infinity
 F2XMI :
 Instruction calculates the expression (2x - 1)
 Value of x is stored at the top of the stack.
 Result is stored back at the top of the stack.

155
 FLY2X
 It calculate ST(1) * Log2 ( ST)
 Result is stored back at the top of stack.
 ST must be in the range of 0 to +infinity.
 ST(1) must be in the range of -infinity to +infinity.

 FLY2XP1
 It calculate ST(1) * log2[ (ST)+1 ]
 Result is stored back on the stack top.
 |ST| must lie between 0 and (1- 21/2 /2).
 Value of ST(1) must lie between –infinity and +
infinity

156
Comparison Instruction

 All the comparison instructions compare the operands and modify

the condition code flags

Comparison C3 C0
Stack Top > Source
0 0
Stack Top < Source
0 1
Stack Top = Source
1 0
Not Comparable
1 1

157
1. FCOM
 The content of the top of stack is compared either
with the content of a memory location or with the
content of another stack register.

2. FIST
 Instruction test if the content of the stack top is
Zero.

158
 Constant Operation Instruction

1. FLDZ
 Load +0.0 to stack top

2. FLDPI
 Load pi(3.14) o stack top

3. FLDLG2
 Load the constant Log10 2 to the stack pointer.

159
 Coprocessor Control Instruction
I. FINIT
II. FENI
III. FDISI
IV. FLDCW
V. FSTSW
VI. FCLEX
VII. FFREE
VIII. FNOP
IX. FWAIT

160
Coprocessor Control
Instructions
FINIT/FNINIT
• Performs a reset (initialize) operation on the arithmetic
coprocessor.
• The coprocessor operates with a closure of projective
(unsigned infinity), rounds to the nearest or even, and
uses extended-precision when reset or initialized.
• also sets register 0 as the top of the stack
Coprocessor Control
Instructions
FSETPM
• Changes the coprocessor to the protected-addressing
mode.
• used when the microprocessor is protected mode
• Protected mode can only be exited by a hardware reset.
• or in 80386-Pentium 4, with a change to the control register
Coprocessor Control
Instructions
FLDCW
• Loads the control register with the
word addressed by the operand.

FSTCW
• Stores the control register into the
word-sized memory operand.
 Coprocessor Control
Instructions

FSTSW AX• Copies the contents of the control

register
to the AX register.
• not available to 8087

FCLEX
• Clears the error flags in the status register
and also the busy flag.
 Coprocessor Control
Instructions

FSAVE
• Writes the entire state of the machine to memory.

FRSTOR
• Restores the state of the machine from memory.
This instruction is used to restore the
information saved by FSAVE.
Figure 14–8  Memory format when the 80X87 registers are saved with the
FSAVE instruction.
Coprocessor Control
Instructions

FSTENV
• Stores the environment of the coprocessor.
• as shown in Figure 14–9

FLDENV
• Reloads the environment saved by FSTENV.

FINCSP
• Increments the stack pointer.
Figure 14–9  Memory format for the FSTENV instruction: (a) real mode
and (b) protected mode.
Coprocessor Control
Instructions
FDECSP
• Decrements the stack pointer.

FFREE
• Frees a register by changing the destination
register’s tag to empty.
– does not affect the contents of the register
 Coprocessor Control
Instructions

FNOP
• Floating-point coprocessor NOP.

FWAIT
• Causes the microprocessor to wait for the
coprocessor to finish an operation.
– should be used before the microprocessor accesses
memory data affected by the coprocessor
8089 I/O Processor
Unit 2
 The 8089 I/O
Processor
 Allows easy interface of
microprocessors with 8 bit or
16 bit peripherals
 Functions like an intelligent
DMAC ,removes I/O overhead,
 has 2 channels
 Operates in parallel with
8086,improves performance in
I/O intensive applications
 1.25 Mbps,at 5 MHz
 Enhance software
 The 8089 I/O
Processor
 It is designed to handle the
details involved in I/O
processing
 It fetches and execute is own
instructions
 Instruction offers
• I/O operations
• Data transfer operations
• Arithmetic and Logical
Operations
• Branching, searching and
8089
Applications
The 8089 I/O Processor
 CPU communicates with
memory based control blocks.
 CPU performs Control blocks
that describes the task to be
performed.
 Channel Program
• The IOP reads the control
blocks to locate a program
sequence called a channel
program which is written in
8089 instruction set.
I/O Handled by Microprocessor
I/O Handled by 8089
Remote Configuration
8089 Block diagram
8089 - pins
Block Diagram of 8089 IOP
IOP Architecture
 Two Channels can be operated
independently.
 Sharing common control logic and ALU.

CCP(Channel Control Pointer)

Cannot be manipulated by the user
Stores the Control Block address of
channel 1 (during initialization)
For channel 2 CB address=[CCP+8]
Signals

 To dispatch task to either channel

CPU uses channel attention
signal(CA) and SEL signals.
SEL=0(Low) Channel 1
SEL=1(High)Channel 2
 Channel reserves two consecutive
IO port Addresses the A0
connected with SEL bit.
Registers
 Pointer Group (20 Bits)
 Register Group (16 Bits)
8089 REGISTER MODEL
registers

 Task Pointer = PC
 PP –Parameter Pointer stores the
address of the parameter block
 PSW which denotes
Source and destination
address widths
Channel activity
Interrupt control and servicing
Bus load limit
Priority
CC format

Channel Control Register Format

 Function Control (Bits 15 and 14)
11-Memory to memory
10-IO port to Memory
01-Memory to IO port
00-IO port to IO port
 Translation Mode (bit 13)
1-Indicates data bytes are to be
translated through a 256 byte look
up table
CC FORMAT

 Synchronization control bits(Bit 12

and 11)
00- Unsynchronized Transfer
01 Source Synchronized transfer
10 Destination Synchronized
transfer
 Source Destination Indicator (bit
10)
0-GA used as source pointer
1-GA used as destination pointer
Communication b/w CPU& 8089
Communication
Structure
SCB
CB-CONTROL BLOCK
PB – PARAMETER BLOCK
TB- TASK BLOCK