Module III - Stack and Interrupts

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Vinod P R, Assistant Professor, College of Engineering, Chengannur

Programming for Stack

The memory bank of 8086/88 is organised according to segments

The 8086 has four segment registers, namely, CS,DS,SS and ES

Out of these segment registers, SS, i.e. 'stack segment register'
contains the segment value for stack while a special register called
SP contains the offset for the stack-top

The ASSUME directive directs the name of the stack segment to
the assembler.

The SS register and the SP register must be initialised in the
program suitably.

Vinod P R, Assistant Professor, College of Engineering, Chengannur

Programming for Stack

Write a program to calculate squares of BCD numbers O to 9 and store

them sequentially from 2000H offset onwards in the current data
segment. The numbers and their squares are in the BCD format. Write a
subroutine for the calculation of the square of a number.
The procedure of computing the square of a number is to be repeated for all the numbers. A
subroutine for calculating the square is written which is called repetitively from the main
program. The 8086/88 does not have single instruction for calculation of the square of a
number. Thus you may calculate the square of a number using ADD and DAA instructions. The
result of the ADD instruction is in hexadecimal format and it should be converted to decimal
form, before it is stored into the memory. Here, one may ask: why not to use the MUL instruction
for calculating the squares of the number? A point to be noted here is that, the MUL instruction
does not calculate the square of a decimal number and moreover, the DAA instruction is to be
used only after the ADD or ADC instructions.

Vinod P R, Assistant Professor, College of Engineering, Chengannur

Programming for Stack


One of the advantages of the subroutine is that, a recurring
sequence of instructions can be as­signed with a procedure name,
which may be called again and again whenever required, resulting
in a comparatively smaller sequence of instructions.

Vinod P R, Assistant Professor, College of Engineering, Chengannur

Programming for Stack

Vinod P R, Assistant Professor, College of Engineering, Chengannur

Vinod P R, Assistant Professor, College of Engineering, Chengannur
Programming for Stack

Write a program to change a sequence of sixteen 2-byte numbers from

ascending to descending order. The numbers are stored in the data segment.
Store the new series, at addresses starting from 6000 H. Use the LIFO
property of the stack.

Vinod P R, Assistant Professor, College of Engineering, Chengannur

Program
ASSUME CS: CODE, DS : DATA, SS : DATA
DATA SEGMENT
LIST DW 1OH
ORG6000H
RESULT DW 1OH
COUNT EQU 1OH
DATA ENDS
CODE SEGMENT
START: MOV AX, DATA Initialize data segment and stack
MOV DS, AX segment
MOV SS, AX
MOV SP, OFFSET LIST Initialize stack pointer
MOV CL, COUNT Initialize counter for word number
MOV BX, OFFSET RESULT+ COUNT Initialize BX at last address (stack) for destination series
NEXT: POP AX Get the first word from series
MOV DX, SP Save source stack pointer
MOV SP, BX Get destination stack pointer
PUSH AX Save AX to stack
MOV BX, SP Save destination stack pointer
MOV SP, DX Get source stack pointer for the next number
DCR CL Decrement count
JNZ NEXT If count is not zero, go to the next num
MOV AH, 4CH Else, return to DOS prompt
INT 21H
CODE ENDS
END START
Vinod P R, Assistant Professor, College of Engineering, Chengannur
INTERRUPTS AND INTERRUPT SERVICE
ROUTINES

The dictionary meaning of the word 'interrupt' is to break the sequence of
operation.

While the CPU is exe­cuting a program, an 'interrupt' breaks the normal
sequence of execution of instructions, diverts its execution to some other
program called Interrupt Service Routine (ISR).

After executing ISR, the control is transferred back again to the main
program which was being executed at the time of interruption.

Vinod P R, Assistant Professor, College of Engineering, Chengannur

INTERRUPTS AND INTERRUPT SERVICE
ROUTINES

Whenever a number of devices interrupt a CPU at a time, and if the
processor is able to handle them prop­erly, it is said to have multiple interrupt
processing capability.

In case of 8086, there are two interrupt pins, viz. NMI and INTR.

The NMI is a nonmaskable interrupt input pin which means that any interrupt
request at NMI input cannot be masked or disabled by any means.

The INTR interrupt, however, may be masked using the Interrupt Flag (IF).

The INTR, further, is of 256 types.

The INTR types may be from 00 to FFH (or 00 to 255).

If more than one type of INTR interrupt occurs at a time, then an external chip
called programmable interrupt controller is required to handle them.

Vinod P R, Assistant Professor, College of Engineering, Chengannur

INTERRUPTS AND INTERRUPT SERVICE
ROUTINES

Interrupt Service Routines (ISRs) are the programs to be executed by
interrupting the main program execution of the CPU, after an interrupt request
appears.

After the execution of ISR, the main program continues its execution further
from the point at which it was interrupted.

Vinod P R, Assistant Professor, College of Engineering, Chengannur

INTERRUPT CYCLE OF 8086/8088


Broadly, there are two types of interrupts.

The first out of them is external interrupt and the second is inter­nal interrupt.

In external interrupt, an external device or a signal interrupts the processor from
outside or, in other words, the interrupt is generated outside the processor, for
example, a keyboard interrupt.

The internal interrupt, on the other hand, is generated internally by the processor
circuit, or by the execution of an inter­rupt instruction. The examples of this type are
divide by zero interrupt, overflow interrupt, interrupts due to INT instructions, etc.

Vinod P R, Assistant Professor, College of Engineering, Chengannur

INTERRUPT CYCLE OF 8086/8088


Suppose an external device interrupts the CPU at the interrupt pin, either NMI or
INTR of the 8086, while the CPU is executing an instruction of a program.

The CPU first completes the execution of the current instruction.

The IP is then incremented to point to the next instruction.

The CPU then acknowledges the re­questing device on its INTA pin immediately if it is
a NMI, TRAP or Divide by Zero interrupt.

If it is an INT request, the CPU checks the IF flag. If the IF is set, the interrupt
request is acknowledged using the INTA pin. If the IF is not set, the interrupt
requests are ignored.

After an interrupt is acknowledged, the CPU computes the vector address from
the type of the interrupt that may be passed to the interrupt structure of the
CPU internally (in case of software interrupts, NMI, TRAP and Divide by Zero
interrupts) or externally, i.e. from an interrupt controller in case of external
interrupts.

Vinod P R, Assistant Professor, College of Engineering, Chengannur

INTERRUPT CYCLE OF 8086/8088


The Interrupt Flag (IF) is cleared. The TF is also cleared, after every response
to the single step interrupt.

The control is then transferred to the interrupt service routine for serving the
interrupting device.

The new address of ISR is found out from the interrupt vector table. The
execution of the ISR starts. If further interrupts are to be responded to during
the time the first interrupt is being serviced, the IF should again be set to 1 by
the ISR of the first interrupt.

If the interrupt flag is not set, the subsequent interrupt signals will not be
acknowledged by the processor, till the current one is completed.

The programmable interrupt controller is used for manag­i ng such multiple
interrupts based on their priorities.

At the end of ISR the last instruction should be IRET. When the CPU executes
IRET, the contents of flags, IP and CS which were saved at the start by the
CALL instruction are now retrieved to the respective registers. The execution
continues onwards from this address, received by IP and CS.

Vinod P R, Assistant Professor, College of Engineering, Chengannur

Address generation of an ISR

Every external and internal interrupt is assigned with a type (N), that is either
implicit (in case ofNMI, TRAP and divide by zero) or specified in the instruction INT
N (in case of internal interrupts).

In case of external interrupts, the type is passed to the processor by an external
hardware like programmable interrupt controller.

In the zeroth segment of physical address space, i.e. CS= 0000, Intel has reserved
1,024 locations for storing the interrupt vector table.

The 8086 supports a total of 256 types of the interrupts, i.e. from 00 to FFH. Each
interrupt requires 4 bytes, i.e. two bytes each for IP and CS of its ISR. Thus a total of
1,024 bytes are required for 256 interrupt types, hence the interrupt vector table
starts at location 0000:0000 and ends at 0000:03FFH.

The interrupt vector table contains the IP and CS of all the interrupt types stored
sequentially from address 0000:0000 to 0000:03FF H. The interrupt type N is
multiplied by 4 and the hexadecimal multiplication obtained gives the offset address
in the zeroeth code segment at which the IP and CS addresses of the interrupt service
routine (ISR) are stored. The execution automatically starts from the new CS:IP.

Vinod P R, Assistant Professor, College of Engineering, Chengannur

INTERRUPT RESPONSE SEQUENCE OF 8086

Vinod P R, Assistant Professor, College of Engineering, Chengannur

Structure of Interrupt vector table of 8086

Vinod P R, Assistant Professor, College of Engineering, Chengannur

NON MASKABLE INTERRUPT


The processor 8086/88 has a Non-Masksable Interrupt input pin (NMI), that has the
highest priority among the external interrupts.

TRAP(Single Step-Type 1) is an internal interrupt having the highest priority
amongst all the interrupts except the Divide By Zero (Type0) exception.

The NMI is activated on a positive transition (low to high voltage). The assertion of
the NMI interrupt is equivalent to an execution of instruction INT 02, i.e. Type 2
INTR interrupt.

The NMI pin should remain high for at least two clock cycles and need not
synchronized with the clock for being sensed.

When the NMI is activated, the current instruction being executed is completed and
then the NMI is served.

In case of string type instructions, this interrupt will be served only after the
complete string has been manipulated.

Another high going edge on the NMI pin of 8086, during the period in which the first
NMI is served, triggers another response. The signal on the NMI pin must be free
oflogical bounces to avoid erratic NMI responses.

Vinod P R, Assistant Professor, College of Engineering, Chengannur

MASKABLE INTERRUPT (INTR)


The processor 8086/88 also provides a pin INTR, that has lower priority as
compared to NMI.

The priorities within the INTR types are decided by the type of the INTR signall that
is to be passed to the pro­ cessor via data bus by some external device like the
programmable interrupt controller.

The INTR signal is level triggered and can be masked by resetting the interrupt flag.
It is internally synchronized with the high transition of the CLK.

For the INTR signal, to be responded to in the next instruction cycle, it must go high
in the last clock cycle of the current instruction or before that.

The INTR requests appearing after the last clock cycle of the current instruction will
be responded to after the execution of the next instruction.

The status of the pending interrupts is checked at the end of each instruction cycle.

Vinod P R, Assistant Professor, College of Engineering, Chengannur

MASKABLE INTERRUPT (INTR)


If the IF is set, the processor is ready to respond to any INTR interrupt and if the IF
is reset, the processor will not serve any interrupt appearing at this pin.

However, once the processor responds to an INTR signal, the IF is automatically
reset.

If one wants the processor to further respond to any type ofINTR signal, the IF
should again be set.

Vinod P R, Assistant Professor, College of Engineering, Chengannur

MASKABLE INTERRUPT (INTR)

Suppose an external signal interrupts the processor and the pin LOCK goes low at the trailing
edge of the first ALE pulse that appears after the interrupt signal preventing the use of bus for
any other purpose.

The pin LOCK remains low till the start of the next machine cycle.

With the trailing edge of LOCK, the INTA goes low and remains low for two clock states before
return­ing back to the high state.

It remains high till the start of the
next machine cycle, i.e. next
trailing edge of ALE.

Then INTA again goes low, remains
low for two states before returning
to the high state.The first trailing
edge of ALE floats the bus AD0-
AD7 , while the second trailing
edge prepares the bus to accept the
type of the interrupt. The type of
the interrupt remains on the bus for
a period of two cycles.

Vinod P R, Assistant Professor, College of Engineering, Chengannur

INTERRUPT PROGRAMMING


While programming for any type of interrupt, the programmer must, either externally
or through the program, set the interrupt vector table for that type preferrably with
the CS and IP addresses of the interrupt service routine.

The method of defining the interrupt service routine for software as well as hardware
interrupt is the same


Vinod P R, Assistant Professor, College of Engineering, Chengannur

INTERRUPT PROGRAMMING


Figure shows the execution
sequence in case of a software
interrupt. It is assumed that
the interrupt vector table is
initialised suitably to point to
the interrupt service routine.

Vinod P R, Assistant Professor, College of Engineering, Chengannur

INTERRUPT PROGRAMMING


Figure shows the transfer of control for the nested interrupts.

Vinod P R, Assistant Professor, College of Engineering, Chengannur

INTERRUPT PROGRAMMING

Suppose

Vinod P R, Assistant Professor, College of Engineering, Chengannur

INTERRUPT PROGRAMMING

Vinod P R, Assistant Professor, College of Engineering, Chengannur