Welcome

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 19EC1202
COMPUTER ORGANIZATION AND ARCHITECTURE

CO2

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 CPU Design

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 Introduction to CPU

The operation or task that must perform by CPU are:

•Fetch Instruction
•Interpret instruction
•Fetch Data
•Process data
•Write data
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Fetch Instruction: The CPU reads an instruction from memory.
Interprete Instruction: The instruction is decoded to determine what action
is required.
Fetch Data: The execution of an instruction may require reading data from
memory or I/O module.
Process data: The execution of an instruction may require performing some
arithmatic or logical operation on
data.
Write data: The result of an execution may require writing data to memory
or an I/O module.
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•The major components of the CPU are an arithmetic and
logic unit (ALU) and a control unit (CU).
•The ALU does the actual computation or processing of
data.
•The CU controls the movement of data and instruction into
and out of the CPU and controls the operation of the ALU.
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 CPU system Bus
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CPU System Bus

The system bus may have three components:

1. Data Bus
2. Address Bus
3. Control Bus

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Internal Structure of the CPU

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There are three basic components of CPU:
1. Register bank
2. ALU and
3. Control Unit.

•There are several data movements between these units and for
that an internal CPU bus is used.

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 Register Organization
The registers in the CPU can be categorized into two groups:
•User-visible registers
•Control and status registers
User-visible Registers:
•General Purpose Registers
•Data Registers
•Address Registers
•Condition Codes
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Address registers:

•Segment pointer
•Index registers
•Stack pointer

Four registers are essential to instruction execution:

1. Program Counter (PC)
2. Instruction Register (IR)
3. Memory Address Register (MAR)
4. Memory Buffer Register (MBR)

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Processor Status Word

1. Sign
2. Zero
3. Carry
4. Equal
5. Overflow
6. Interrupt enable/disable
7. Supervisor
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Concept of Program Execution

1. Fetch the contents of the memory location pointed at by the PC. The contents of this
location are interpreted as an instruction to be executed. Hence, they are stored in the
instruction register (IR). Symbolically this can be written as:

IR = [ [PC] ]

2. Increment the contents of the PC by 1.

PC = [PC] + 1
3. Carry out the actions specified by the instruction stored in the IR.

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 Concept of Program Execution
The first two steps are usually referred to as
the fetch phase and the step 3 is known as
the execution phase. Fetch cycle basically
involves read the next instruction from the
memory into the CPU and along with that
update the contents of the program
counter. In the execution phase, it
interprets the opcode and perform the
indicated operation. The instruction fetch
and execution phase together known as Basic Instruction cycle
instruction cycle.

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 Single bus organization of the data path inside
the CPU

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The processor interprets the instruction and performs the
required action. In general, the actions fall into four
categories:
•Processor-memory
•Processor-I/O
•Data processing
•Control
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Control Unit
To execute an instruction, the control unit of the CPU must generate the required
control signal in the proper sequence.

To generate the control signal in proper sequence, a wide variety of techniques exist.
Most of these techniques, however, fall into one of the two categories,

Hardwired Control :

Microprogrammed Control :

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Hardwired Control : In this hardwired control techniques, the control signals are generated by means
of hardwired circuit. The main objective of control unit is to generate the control signal in proper
sequence.

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Eg: Programmable Logic Array

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Microprogrammed Control
There is an alternative approach by which the control signals
required inside the CPU can be generated . This alternative
approach is known as microprogrammed control unit.

In microprogrammed control unit, the logic of the control unit is

specified by a microprogram.

A microprogrammed control unit is a relatively simple logic

circuit that is capable of (1) sequencing through
microinstructions and (2) generating control signals to execute
each microinstruction.

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 Microprogrammed Control
Control Word (CW) :
Control word is defined as a word whose individual bits
represent the various control signal. Therefore each of the
control steps in the control sequence of an instruction
defines a unique combination of 0s and 1s in the CW.
A sequence of control words (CWs) corresponding to the
control sequence of a machine instruction constitutes the
microprogram for that instruction.
The individual control words in this microprogram are
referred to as microinstructions.
The microprograms corresponding to the instruction set of
a computer are stored ina aspecial memory which will be
referred to as the microprogram memory. The control
Basic organization of a words related to an instructions are stored in
microprogrammed control microprogram
memory.

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 Microprogrammed Control
The control unit can generate the control signals for any instruction by sequentially reading the CWs of the
corresponding microprogram from the microprogram memory. To read the control word sequentially from
the microprogram memory a microprogram counter ( PC) is needed.

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 Common Micro-Ops
There are 4 types of Micro-Ops:

• Transfer: transfers data from one register to another

R0 <- R1
• Arithmetic: performs arithmetic on data in registers
R0 <- R1 + R2
• Logic/bit manipulation: performs bit (Boolean) operations on data
R0 <- R1 & R2 ; or R0 <- R1 | R2
• Shift: shift data in registers by one or more bit positions
R0 <- R1 << 3; or R0 <- R2 >> 2

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 Micro-Ops Transfer Memory
 Memory transfers are similar to register transfers, but…
 Memory to register transfers are called read operations, while
register to memory transfers are called write operations
 RTL expressions for a read operation, assuming the use of an address
registers:
AR <- address
DR <- M[AR]
 RTL expressions for a write operation, assuming use of a data register:
AR <- address
DR <- value
M[AR] <- DR

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 MAPPING OF INSTRUCTIONS
Direct Mapping Address
OP-codes of Instructions 0000 ADD Routine
AND Routine
ADD 0000 0001
. 0010 LDA Routine
AND 0001 . STA Routine
. 0011
LDA 0010 0100
BUN Routine
STA 0011 Control
BUN 0100 Storage
Mapping
10 xxxx 010
Bits Address
10 0000 010 ADD Routine
https://www.youtube.com/watch?
v=Vkc_K02vR9M
10 0001 010 AND Routine
10 0010 010 LDA Routine

10 0011 010 STA Routine

10 0100 010 BUN Routine

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MACHINE INSTRUCTION FORMAT

Machine instruction format

15 14 11 10 0
I Opcode Address

Micro-instruction Format
3 3 3 2 2 7
F1 F2 F3 CD BR AD
F1, F2, F3: Microoperation fields
CD: Condition for branching
BR: Branch field
AD: Address field
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I-Indirect Addressing

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DESIGN OF CONTROL UNIT

microoperation fields
F1 F2 F3

3 x 8 decoder 3 x 8 decoder 3 x 8 decoder

7 6 54 3 21 0 7 6 54 3 21 0 7 6 54 3 21 0

AND
ADD Arithmetic AC
DRTAC logic and
shift unit DR
PCTAR

DRTAR

From From
PC DR(0-10) Load
AC
Select 0 1
Multiplexers

Load AR Clock

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MICROINSTRUCTION FIELD DESCRIPTIONS -
F1,F2,F3

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Wednesday, April 6, 2022 31
Sample machine instructions
Symbol Opcode Description

ADD 0000 AC AC + M[EA]

BRANCH 0001 if (AC < 0) then (PC  EA)

STORE 0010 M[EA]  AC

EXCHANGE 0011 AC M[EA], M[EA]  AC

EA is the effective address

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Memory
1. Concept of Memory.
2. Cache Memory.
3. Memory Management
4. Virtual memory
The memory of computer is broadly categories into two categories:

•Internal Memory or Primary Memory

•External Memory or Secondary Memory

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Primary Memory
• RAM: Random Access Memories are volatile in nature. As
soon as the computer is switched off, the contents of
memory are also lost.
• Types: SRAM, DRAM

• ROM: Read only memories are non volatile in nature. The

storage is permanent, but it is read only memory. We can not
store new information in ROM.
• Types: PROM, EPROM, EEPROM, UVPROM

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Main Memory Organization
• 16X4 Means 16 Locations & 4 bits in each Location

• Read – Retrieve data from memory to CPU registers

• Write – Store data to memory from CPU registers

• To transfer data we require data bus

• To specify or to identify a particular memory location we require

address bus

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Semiconductor Memory Classification

Non-Volatile
Read-Write Memory Read-Write Read-Only Memory
Memory

Random Non-Random
EPROM Mask-Programmed
Access Access
2
E PROM Programmable (PROM)

SRAM FIFO FLASH

DRAM LIFO
Shift Register
Content
Addressable
Memory (CAM)

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RAM
• Random write and read operation for any cell
• Volatile data
• Most of computer memory
• DRAM
• Low Cost
• High Density
• Medium Speed
• SRAM
• High Speed
• Ease of use
• Medium Cost

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 ROM
• Non-volatile Data
• Method of Data Writing
• Mask ROM
• Data written during chip fabrication
• PROM
• Fuse ROM: Non-rewritable
• EPROM: Erase data by UV rays
• EEPROM: Erase and write through electrical means
• Speed 2-3 times slower than RAM
• Upper limit on write operations
• Flash Memory – High density, Low Cost

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 FLASH
• Extension of EEPROM
• Same floating gate principle
• Same write ability and storage permanence
• Fast erase
• Large blocks of memory erased at once, rather than one word at a time
• Blocks typically several thousand bytes large
• Writes to single words may be slower
• Entire block must be read, word updated, then entire block written back
• Used with embedded microcomputer systems storing large data items in nonvolatile
memory
• e.g., digital cameras, MP3, cell phones

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 CPU and Memory

• CPU can interact with main memory in two ways:

• It can write a byte/word to a given memory location.
• The previous bits that were in that location are destroyed
• The new bits are saved for future use.
• It can read a byte/word from a given memory location.
• The CPU copies the bits stored at that location and stores them in a CPU register
• The contents of the memory location are NOT changed.

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 Main Memory Characteristics
 Very closely connected to the CPU.

 Contents are quickly and easily changed.

 Holds the programs and data that the processor is actively working
with.

 Interacts with the processor millions of times per second.

 Nothing permanent is kept in main memory.

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Secondary Storage Characteristics

 Connected to main memory through a bus and a device controller.

 Contents are easily changed, but access is very slow compared to
main memory.
 Only occasionally interacts with CPU.
 Used for long-term storage of programs and data.
 Much larger than main memory (GBs vs. MBs).

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• CPU --- Memory Hi Lo
• 16-bit CPU Byte Organized
15-8 7-0 Lower order byte
• Data Size Hi
first or little endian
CPU
Lo

Higher order byte

first or Big endian
Lo CPU
Hi

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The data transfer between main memory and the CPU takes place through two
CPU registers.

MAR : Memory Address Register

MDR : Memory Data Register.

If the MAR is k-bit long, then the total addressable memory location will be 2k.

If the MDR is n-bit long, then the n bit of data is transferred in one memory cycle.

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 Binary Storage Cell

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Depending on the technology used to construct a RAM, there are two types of
RAM –

SRAM: Static Random Access Memory.

DRAM: Dynamic Random Access Memory

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 DRAM

SRAM & DRAM both are volatile

DRAM packing density is more & Less expensive

DRAM requires supporting refresh circuitry

SRAM is faster than DRAM

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Memory Management

Five State Process Model

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Memory Management
1. Uni- Program Memory
2. Multi –Program Operating System

Uni-Program: User Program

• Memory split into two

1. For operating system
2. For currently executing program
Uni-Program

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 Memory Management
Memory
Multi-Program:
Operating System

Memory split into multiple

User Program 1
1. For operating system
User Program 2
2. User part of memory is subdivided to
accommodate multiple processes. User Program 3

Multi-Program

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Partitionin
g
1) Fixed size partitions
2) Variable size partitions

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 Paging

The memory is partitioned into equal fixed size chunks that are relatively
small. This chunk of memory is known as frames or page frames.

Each process is also divided into small fixed chunks of same size. The
chunks of a program is known as pages.

At a given point of time some of the frames in memory are in use and
some are free. The list of free frame is maintained by the operating system.

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 Cache Memory
It is the fact that CPU is a faster device and memory is a relatively slower device.

Memory access is the main bottleneck for the performance efficiency. If a faster memory
device can be inserted between main memory and CPU, the efficiency can be increased.

The faster memory that is inserted between CPU and Main Memory is termed as Cache
memory.

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 Cache Memory
• High speed (towards CPU speed)  = 0.95 Cache + 0.05 Mem
Access
• Small size (power & cost)
Miss

Main
CPU Memory
Cache (Slow)
(Fast)  Mem
Hit Cache

95% hit ratio

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Cache Memory

CPU 30-bit Address

Main
Memory
Cache
1 Gword
1 Mword

Only 20 bits !!!

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Cache Mapping

1. Direct mapping

2. Associative mapping

3. Block-set-associative mapping

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Direct Mapping
• A particular block of main
memory can be brought to a
particular block of cache
memory.
• It is not flexible

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Associative Mapping
• In this mapping function, any
block of Main memory can
potentially reside in any cache
block position.
• This is much more flexible
mapping method.

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Block Set Associative Mapping
• In this method, blocks
of cache are grouped
into sets, and the
mapping allows a block
of main memory to
reside in any block of a
specific set. From the
flexibility point of view,
it is in between to the
other two methods

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Cache Replacement Policies

1. Least Recently Used (LRU) replacement policy

2. First In First Out (FIFO) replacement policy

3. Random replacement policy

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 Virtual Memory
The virtual address space is used to develop a process. The special hardware unit , called
Memory Management Unit (MMU) translates virtual address to physical address. When
the desired data is in the main memory, the CPU can work with these data. If the data are
not in the main memory, the MMU causes the operating system to bring into the memory
from the disk.

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 VIRTUAL MEMORY

Relation between memory space and address in a virtual

memory system
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 Memory table for mapping a virtual address

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Address space and memory space split into groups of lK words.
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 Memory Table in a paged system

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 An associative memory page table.
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