ZXG10 iBSC Structure and Principles

Course Objectives

 After learning this course, you will:

 Understand the functions, features and specifications of ZXG10 i
BSC
 Master the hardware structure of ZXG10 iBSC and the working p
rinciples of its shelves and boards
 Master the interface design and logical units of ZXG10 iBSC
 Master signal streams on the control plane and the user plane of
ZXG10 iBSC
 Master the internal cable connections of ZXG10 iBSC
Contents

 iBSC System Overview

 iBSC Hardware Structure
 iBSC Board Principles
 iBSC Interface Implementation and Logical Units
 Signal Flow on iBSC Control Plane and User Plane
 iBSC Internal Cable connection
Network Structure
MSC/VLR GMSC

Nc
A
BTS PSTN
Mc
BSC

BTS
Inter-PLMN
Gb Nb
Iur-g
MGW GMGW

IuCs
NodeB

RNC IuPs

NodeB
SGSN GGSN
What does "i" stand for?
i BS
C

intelligent integration
intelligent identification of wireless integrates multi-interfaces
access intelligent error E1/STM-1/IP integrates multi
self-correction transmission supported

immensity intensify
large capability intensified design
supports 3072 TRX and 15000 Erl supports FR/EFR/HR/AMR/WB-AMR,
with only two racks innovative NetSpeed wireless
enhanced technology

IP
All-IP platform
supports IP bearer
ZXG10 iBSC Product Features
 Based on V3 universal hardware platform
 All IP hardware architecture
 Large capacity and strong processing capabilities
 Modular design with good scalar
 Separation of control streams from media streams
 Coding scheme: FR/HR/EFR/FR-ARM/HR-AMR
 Transmission interface: E1/T1/FE/STM-1
 Easy and smooth upgrade
 Flexible networking modes
 High integration and low power consumption
Universal All IP Hardware Platform

GSM / WCDMA TD-SCDMA

Universal
Hardware Platform
Totally 16 boards

Smooth
All IP Upgrade
CDMA 2000 NGN Modularity
Modular Design
 Boards
 Different software can be used to define diffe
rent functions for the same board.
 AIU, BIU, PCU and TCU are logical units; All
interface units are in the resource shelf.

 Easy Scalability BGSN BGSN BGSN

 The system can be e BCTC BCTC BGSN

xpanded via adding R

BGSN BGSN
CBUs. BGSN

 3 RCBUs/2 racks. BPSN BPSN BGSN

RACK1 RACK1 RACK2

Multiple Access Modes and Smooth Evolution
 iBSC supports multiple access modes
 E1/T1
 STM-1
 FE/GE
 Evolution
Advantages
• Saves 20% space when 2G and 3G m
iBSC iBSC iBSC odules are integrated into the same site.
• Shares cabinets, spare parts, transmis
RNC RNC&BSC sion and OMM.
BSC RNC RNC&BSC • Saves power consumption
BSC BSC RNC&BSC • Saves engineering and network upgra
de cost
BSC BSC RNC&BSC
ZXG10 iBSC Interfaces

Logical Interfa
No. Link Object Interface Type
ce
1. A MSC STM-1, E1, FE/GE

2. Gb SGSN E1, FE/GE

3. Abis BTS E1, STM-1, FE/GE
4. Ater iTC STM-1, E1
 ZXG10 iBSC Interface Specifications
A-Interface E1(T1) A STM-1 A IP A

Number
Abis Interfac Number of Interface Capa Number of
e
Cabinet of Carri Interface Capacity Interface Capacity
Carriers city Carriers
ers
A Single Cabi Abis:208 E1(T1) Abis:208 E1(T1) Abis:208 E1(T1)
1024 1024 1024
net A:188E1(T1) A:4 pairs of STM-1 A:1 pair of GE
E1(T1) Abis
Abis:624 E1(T1) Abis:624 E1(T1) Abis:624 E1(T1)
Dual Cabinets 3072 3072 3072
A:700E1(T1) A:11 pairs of STM-1 A:2 pairs of GE
Abis:3 pairs of ST
A Single Cabi Abis:3 pairs of STM-1 Abis:3 pairs of STM-1
1024 M-1 1024 1024
net
A:188E1(T1) A:4 pairs of STM-1 A:1 pair of GE
STM_1 Abis
Abis:9 pairs of ST
Abis:9 pairs of STM-1 Abis:9 pairs of STM-1
Dual Cabinets 3072 M-1 1024 3072
A:700E1(T1) A:11 pairs of STM-1 A:2 pairs of GE

A Single Cabi Abis:1 pair of GE Abis:1 pairs of GE Abis:1 pair of GE

1024 1024 2048
net A:252E1(T1) A:4 pairs of STM-1 A:1 pair of GE
IP Abis Abis :2 pairs of G
Abis:2 pairs of GE Abis:2 pairs of GE
Dual Cabinets 3072 E 3072 3072
A:700E1(T1) A:11 pairs of STM-1 A:2 pairs of GE

A Single Cabi Abis:160 E1(T1) Abis:160 E1(T1) Abis:160 E1(T1)

1024 1024 1024
net A:188E1(T1) A:4 pairs of STM-1 A:1 pair of GE
IPoE Abis (EI
PI+DTB) Abis:480 E1(T1) Abis:480 E1(T1) Abis:480 E1(T1)
Dual Cabinets 3072 3072 3072
A:700E1(T1) A:11 pairs of STM-1 A:2 pairs of GE

A Single Cabi \ Abis:3 pairs of STM-1 Abis:3 pairs of STM-1

IPoE Abis (EI \ 1024 1024
net \ A:4 pairs of STM-1 A:1 pair of GE
PI+SDTB2)
Dual Cabinets \ \ 3072 11 pairs of STM-1 3072 A:2 pairs of GE
ZXG10 iBSC Physical Specifications
Item Specification
Dimensions (H*D*W) (mm) 2,000 * 800 * 600
<270Kg(1 rack)
Weight
<540Kg(2 rack)
All E1:
2,558W per rack, 6,368W/2 rac
ks
Power Consumption
All IP:
2,542W per rack, 3,808W/2 rac
ks
Power Source Requirements -48V DC (-40V DC to -57V DC)
Long-term temperature: 0°C–
40°C.
Operating Temperature
Short-term temperature: -5°C–
45°C.

Long-term humidity: 20–90%.

Operating Humidity:
Short-term humidity: 5%–95%.
ZXG10 iBSC Performance Specifications
Item Specification
BHCA 4,200K

Maximum traffic 15000 Erl

Maximum throughput over Gb interfa E1 Gb: 256Mbps

ce IP Gb: 600Mbps
One Rack: 1,024
Maximum TRXs supported
Two Rack: 3,072

 The all-IP architecture conforms to the trend towards an IP-

based network
 Large capacity and strong processing capabilities
 Supports E1, T1, STM-1 and IP interfaces and flexible netw
orking modes
Contents

 iBSC System Overview

 iBSC Hardware Structure
 iBSC Board Principles
 iBSC Interface Implementation and Logical Units
 Signal Flow on iBSC Control Plane and User Plane
 iBSC Internal Cable connection
Hardware Architecture Introduction
 Work Planes
 Control Plane & User Plane

 Major Interfaces
 Abis – IP over E1, E1, IP
 A – TDM (E1, STM-1), IP
 Gb – TDM (E1), IP
 (Ater)

 Levels of Shelves Shelf Types

 Control shelf (BCTC), resource shelf (BGSN), switch shelf (BPS
N)

 Boards
ZXG10 iBSC Shelves
Control Shelf (BCTC)
System control and management
(BGSN)
Resource Shelf Clock capture and distribution

Processing of control plane signaling

(BCTC)
System operation and maintenance
Control Shelf

Resource Shelf (BGSN)

(BGSN) System external access
Resource Shelf
Processing of universal services

(BPSN)
Switch Shelf
Switch Shelf (BPSN)
Large-capacity IP switch platform on the user plane
ZXG10 iBSC Boards
Shelf Board Full Name Functions
Universal Interface Module for Contr
UIMC Level 2 switch of control plane signaling
ol plane
Control and management of CS and PS services, processing of BS
CMP Control Main Processor SAP and BSSGP protocols, and resource management of the syst
em
CHUB Control HUB Switch and convergence of control plane signaling
BCTC
Operation and maintenance, system control, management and mo
OMP Operation Main Processor
nitoring
SBCX X86 Single Board Computer O&M server
CLKG Clock Generation Clock generation and distribution
ICM Integrated Clock Module Clock generation and distribution (with GPS)
GLI Gigabit Line Interface Level 1 switch, interface with the resource shelf
BPSN Provides bi-directional user plane data switch with a capacity of 40
PSN Packet Switch Network
Gbps on each direction
Signaling processing, interface board (16 E1 lines for A/Gb, ei
SPB2 Signaling Processing Board
ght E1 lines for Abis)
Level 2 switch between the control plane and the user plane, resou
GUIM Giga bit User Interface Module
rce shelf management
GUP2 GSM Universal Processing Processing of user plane protocols, such as TC, PCU and RTP
BGSN
DTB Digital Trunk Board Provides 32 E1/T1 trunk interfaces
SDTB2 Sonet Digital Trunk Board 2 Provides two STM-1 interfaces
GIPI GE IP Interface Provides four FE interfaces or one GE interfaces for Abis/A/Gb
EIPI E1 IP Interface provides E1 or T1 based IP connection
Physical and Logical Boards of ZXG10 iBSC
Physical Bo
Logical Board Functions
ard
Completes IP access over the Abis interface, and sever the control
IPBB
plane from the user plane
Completes IP access over the A interface, and sever the control plan
GIPI IPI
e from the user plane (signaling from service)
Completes IP access over the Gb interface, and sever the control pl
IPGB
ane from the user plane
Search 20 ms TRU frames according to the channels and form IP pa
BIPB2 ckets
For IP access over the Abis interface, it also processes RTP.

GUP2 AIPB It processes RTP and forms IP packets

UPPB2 User plane protocol processing in the PS field

Completes the transcoding and rate adaptation of TRAU frames, and
DRTB2
provides FR, EFR, AMR and TFO functions

LAPD2 LAPD signaling processing

SPB2 SPB2 MTP2 protocol processing

Provides Gb interface functions, and processes the FR, NS and parti

GIPB2
al BSSGP of GPRS.
Introduction to BCTC
 Completes the global operation Control Shelf

and maintenance of the system, 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17

provides the global system clo

Rear Board
R R R R R R R R R R
U U M M C C C C
S S
ck, manages the control plane, V V
I I P
M M B
P
B
K K
G G
H
B
H
B
B B
and responsible for the switch b 2 3 1 2 1 2

etween the control plane and th BCTC

e Ethernet 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17

Front Board
U U C C
 Each iBSC must be configured C C
M M
C C
M M
S
B
S
B I I O
O
M M
I I
C C
H H
C C M M P P U U
with one control shelf, which is l P P P P
X X C C
M M B B

ocated in Shelf 2 in Rack 1

No. Board Name Number Slot No. Backup
1 OMP 2 11–12 1+1
2 CMP 2~6 1~8 1+1
3 CHUB 2 15~16 1+1
4 ICM 2 13~14 1+1
5 UIMC 2 9~10 1+1
6 SBCX 2 5，7 1+1
BCTC Working Principles
 The clock generation board (IC BPSN BGSN

M) distributes clock signals to th UIMC GUIM

e switch shelf and resource shel
ves through cables. 8K/16M
 OMP and SBCX boards are con CHUB UIMC ICM
nected to the iOMCR through th
e hub to sever intranet segment
Ethernet
s from Internet segments.
 The CHUB acts as the control st CMP OMP SBCX
ream convergence center for th BCTC
e control streams from the switc
h shelf, the resource shelf and t
he control shelf.
HUB HUB

Outside
network
Introduction to BGSN
Gigabit Resource Shelf
 Provides system external inter 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
faces. R R R

Rear Board
R R R R
S D S G G D
 Processes universal services. P T P U U T
S
P
B B B M M B B
1 2
 Acts as the Level 2 switch cen
BGSN
ter.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
 The BGSN is configured in Sh

Front Board
G S S G G G D E G S
D
elf 1 and Shelf 3 of the main r U
P
P
B T
B
P
B
U U U
P I I
T
B
I
P
U
P
P
B
2 2 2 2 M M I 2 2
ack. When a single shelf cons
titutes an office, it is configure
d in Shelf 2.
No. Board Name Number Slot No. Backup
1 GUIM 2 9~10 1+1
2 GIPI - 1-8,11-17 1+1
3 GUP2 - 2-8,11-16 -
4 DTB 0-8 1-8,11-14,17 -
5 SDTB2 - 1-8,11-16 1+1
6 SPB2 - 1-8,11-17 -
7 EIPI - 1-8,11-17 -
BGSN Working Principles
 The GUIM board is the convergence
and switch center for various data in BPSN BCTC
the resource shelf. It completes the i
nformation exchange between mod GLI CHUB ICM
ules.
 The GUIM board interconnects with
the GLI board in the packet switch s
BGSN
helf to carry out level 1 switch betwe GUP2 GUP2 GUIM
en different resource shelves.
 DTBs and SPBs provide E1 interfac
es, and SDTBs provide STM-1 acce
ss.
 GIPI boards provide FE and GE acc SDTB2 DTB SPB2 GIPI
ess.
 Processes universal services (conv STM-1 E1 E1 FE GE
ersion from TC and TDM to IP pack
ets, processing of user plane protoc
ols).
Introduction to BPSN
 Interconnects BGSNs and Lev Packet Switching Shelf

el 1 switch centers on the use 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17

r plane.

Rear Board
R R
U U
I I
 Each iBSC should have one B M M
2 3
PSN, which is configured in S
BPSN
helf 4.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
 If the iBSC has two BGSNs, t

Front Board
G C C C U U
hen the BPSN is not mandato G
L
G
L
G
L
G G
L L L
P
S
P
S
C
M M M M
I
M
I
M
I I I I I I N N P P P P
ry. However, this can affect th C C

e capacity expansion of the sy

stem.
No. Board Name Number Slot No. Backup

1 PSN 2 7~8 Load sharing

2 GLI 2~6 1~6 Load sharing
3 CMP 0~2 11~14 1+1

4 UIMC 2 15~16 1+1

BPSN Working Principles

 The GLI board receives user BPSN BCTC

FE
plane data from the GUIM b PSN UIMC CHUB
oard.
 The PSN provides 40Gbps LVDS
data switch capacity. GLI ...... GLI ICM
 The UIMC receives clock an
d control signals from the co fiber
ntrol shelf and distributes co
ntrol & management interfac GUIM GUIM
es and clock signals in the s
helf. BGSN BGSN
Shelf Configuration (1)
PWRD PWRD
1 2 3 4 5 6 7 8
9 10 11 12 13 14 15 16 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
FAN FAN
BIU S S R R R R
S G D D D G D D G G PG PG D D G S S R R R R R R G G SR S R
R R R R
P U T U U U I I D D
T T T T I I BP BP T T U P P S D D D D D U U G G
PE PE S S
B P T T
AIU B B B
P
B B M M 2I 2I B B P B B P T T T T T M M B B P P
2 2 2 2 2 2 B B B B B B 1 2 R R B B B B
/ / / /
PCU
R R R R R R R R
Abis Interface E1
C C C C S S U U O O I I C C R R
B I I H H S S U U M M C C C C
M M M M B I I P P K K
TCU C C M M M M C C U U V V H H
P P P P P P M M M M G G B B
X X C C B B B B 2 3 B B 1 2 1 2
FAN FAN
R R
S G G D D G D D G G D G D D G G S R R R R R R R R R
P U U U U U T U T T U U P S D D D D G G D D D S
B P P T T P T T I I P P P B P T T T T U U T T T P
B B B M M
2 2 2 B B 2 B B M M 2 2 2 2 B B B B B B B B B

G G G G G G P P C C U U
1 2
R R A-Interface E1
I I U U
L L L L L L S S M M
M M I I
I I I I I I N N P P M M
C C 2 3
FAN FAN

PWRD PWRD
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
FAN FAN
G G R R R R
S G D D D G D D S S S G S R R R R R R G G R R R
P U T T T U T U U D P P P U P S D D D D D D S S S S
T I
B P P I T B B B P B P T T T T
U U
T M M T P P P P
B B B B B M M B
2 2 2 2 2 2 2 2 B B B B B B 1 2 B B B B B
R R
D G G D D G D D G G D G D D G G D R R R R R G G R R R R
U U U U U U U U D D D D D U U D D D D
T P P T T P T T I I T P T T P P T T T T T T M M T T T T
B 2 2 B B 2 B B M M B 2 B B 2 2 B B B B B B 1 2 B B B B
FAN FAN
R R
S G D D D G D D G G D S S G S R R R R R R R R R R
P U U U U P P U P S D D D D D G G D S S S
B P T T T P T T I I T B B P B P T T T T T U U T P P P
2 2 B B B 2 B B M M B 2 2 2 2 B B B B B B M M B B B B
1 2
R R
D G G D D G D D G G D G D D G G D R R R R R G G R R R R
U U U U U U U U D D D D D U D D D D
T U
P P T T P T T I I T P T T P P T T T T T T
M M
T T T T
B 2 2 B B 2 B B M M B 2 B B 2 2 B B B B B B
1 2
B B B B
FAN FAN
Cabinet Configuration (2)
PWRD PWRD
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
FAN FAN
G G G G G G R R R R
G G G G G G G R R G G
BIU I I U U U U U U U I I U U G G M M
P P P P P P I I P P P P P E U U I I
E
2 2 2 2 M M 2 M M N N
I I I I 2 2 R R
AIU 1 2 C C

S U U O O I C C R R R R R R R R R R
C C C C S I U U C C C C
PCU
M M M M
P P P P
B
C
X
B
C
X
I I
M M M M C
C C P P M
C
M
H
U
B
H
U
B
S
V
B
S
V
B
I
M
I
M
M
P
B
M
P
B
K
G
K
G
H H
B B Abis Interface IP
TCU 2 3 1 2 1 2
FAN FAN
R R
G G G G G G G G G G G G G G R R R R R R
I G G G
I I U I U U U U U I I U U G G G G U G
P P P P P P I I P P P P P P E E E E U E E
M M
I I 2 I I 2 M M 2 2 I I 2 2 R R R R R R
1 2

G G G G P P C C U U
I I
R
U
R
U
A-Interface IP
L L L L S S M M
M M I I
I I I I N N P P M M
C C 2 3
FAN FAN

PWRD PWRD
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
FAN FAN
G G R R
G G G G G G G R R
I I U U U U U U G G G G
U
P P P P P I I P P E E U U
I I 2 2 M M 2 2 R R M M
2
1 2

FAN FAN

FAN FAN
Cabinet Configuration (3)
PWRD PWRD
1 2 3 4 5 6 7 8
9 10 11 12 13 14 15 16 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
FAN FAN
S S R R R R
E D D E D D G D G G PG P G S G G G R R R R R G G SR S R R
I U U I I P U U D D D G G S
BIU P T T I T T U T I I B P BP U D D U U PE PE
B P P P T T T P
B B P B B P B M M2I 2I T T M M B R BR
I I 2 / / 2 2 2 2 B B B B B B
AIU 1 2 / /
R R R R R R R R
Abis Interface IPoE
C C C C S S U U O O I I C C R R
PCU B I I H H S S U U M M C C C C
M M M M B
C C M M M M C C U U V V I I P P K K H H
P P P P P P M M M M G G B B
TCU X X C C B B B B 2 3 B B 1 2 1 2
FAN FAN
G G G G G R R R R R R R R
G G G G G G G G G G
I I I I U U G G G G G G G G
U U U U I I U U U
P P P P I I E E E E U U E E
P P P P P P P P P M M
I I I I 2 2 2 2 M M I I 2 2 2 R R R R R R

G G G G G G P P C C U U
1 2
R R A-Interface IP
I I U U
L L L L L L S S M M I I
I I I I I I N N M M
P P M M
C C 2 3
FAN FAN

PWRD PWRD
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
FAN FAN
G G R R R R
E D D E D D G D S S S G G G R R R R R G G R
U U P P P U U U D D D S S S
I T T I T T U T I I B
D D U U
P
B B P P P T T T T T M M P P
P B B P B B P B M M 2
I I 2 2 2 2 2 2 B B B B B 1 2 B B B

E D D E D D G D S S G G G R R
G G R R R R R R R
I T T I T T U T U U P P U U U D D D D D G G S S
P B B P B B P B I I B B P P P T T T T T U U P P
2 2 2 2 M M
I I 2 M M 2 B B B B B B B
1 2
FAN FAN

FAN FAN
Contents

 iBSC System Overview

 iBSC Hardware Structure
 iBSC Board Principles
 iBSC Interface Implementation and Logical Units
 Signal Flow on iBSC Control Plane and User Plane
 iBSC Internal Cable connection
OMP
 The OMP board processes the global procedure, perfo
rms O&M related control of the entire system (includin
g O&M proxy), and connects to the OMM through the
100M Ethernet.
 As the processing core of iBSC operation & maintenan
ce, the OMP board can directly or indirect monitor and
manage all boards in the system. It provides two links (
Ethernet interface and RS485) for configuration manag
ement of system boards.
 OMP
 CPU A is responsible for global operation & maintenance.
 CPU B is the Router Processing Unit (RPU).
 The HD Disk is a 2G hard disk to store system data, for example,
board software version files, configuration files and logs.
CPU B
RS485,RS232
RS232 DEBUG2- 232
RS485

CP FE

What are the fu CPU Core Ethernet OMC2

nctions of the R
Back Board
PU? Logic Unit
Power
Management

RS485,RS232 GPS485
PD 485
RS232
RS232
CPU Core RS485 DEBUG1- 232
1. Enables intranet addresses withi
n the BSC to communicate with each HD Disk
OMC1
Ethernet
other. CP FE

2. Provides routes for the operatio CPU A

n and maintenance of the BTS.
CMP
 The CMP board controls and manages service call
s in the PS and CS fields, and manages the resou
rces of BSSAP, BSSGP and the system.
 Its physical board is MPx86/2, the same as the O
MP, but the memory capacity is slightly different: 1
GB/CPU for the OMP, and 2GB/CPU for the CMP,
and the OMP has a hard disk).
UIMC
 The UIMC is responsible for Ethernet Level 2 switch withi
n the BCTC and the BPSN and the management of the B
CTC.
 The UIMC provides the clock drive function inside the BC
TC and the BPSN. It inputs 8K and 16M signals, which ar
e sent to different slots in the BGSN after phase lockup to
provide 16M and 8K clocks for the boards.
 The UIMC provides management interfaces for the BCTC
and the BPSN; it also provides board resetting and resetti
ng signal collection functions for the BCTC and the BPSN
.
UIMC
 The UIMC provides one internal GE interface that is connected to the
CHUB.
Inner Bus

RS485
DEBUG 232
Logic Unit Clock Unit CPU DEBUG FE

Inner Bus
Back Board

CP FE, CP GE CLKIN

User Plane Control Plane CP FE 1~10

Switch Switch

Ethernet
Switch Unit
CHUB
 The CHUB works together with the UIMC/GUIM to be res
ponsible for control plane data stream exchange and conv
ergence in the system.
 The control plane data from each shelf is sent to the Ether
net switching unit of CHUB board through the Ethernet ca
bles on the control plane.
 The data is then sent to UIMC board of the BCTC throug
h GE for level-2 switch, and then distributed to each CMP
board for processing.
CHUB
 The RCHB1 board has three FE buses, on which FE interfaces are grouped as F
E1–8, FE9–16 and FE17–24.
 The RCHB2 board has three FE buses, on which FE interfaces are grouped as F
E25–32, FE33–40 and FE41–46.

DEBUG FE/232
Logic Unit CPU

Inner Bus
Back Board

CP GE
Ethernet Ethernet
Switch Switch

Ethernet
Switch Unit

FE1 FE1 FE1 FEn

ICM
 Responsible for system clock supply and external synchroniz
ation. The board extracts clock reference via the A interface
and drives multiple channels of clock reference signals for us
e by each interface unit.
 It receives GPS satellite signals and extract 1PPS signals an
d related TOD messages. The 1PPS signals are used as ref
erence for phase lockup in order to create PP2S,19.6608MH
z and 8 K clock references for iBSC.
 Supports background or manual selection of clock reference
s, including BITS, line (8 K), GPS, local (Level 2 or Level 3);
supports software shielding of manual switchover.
 Supports four work modes: CATCH, TRACE, HOLD and FR
EE.
ICM
 8 K reference input ， when DTB/SDTB2 provides the clock reference, it con
nects with the 8KOUT/DEBUG-232 interface of RGIM1.When SPB2 provides
the clock reference, it connects with the 8KOUT/CPU1-RS232 interface of R
SPB.
 One CLKOUT interfaces outputs a one-to-six cable; one shelf has two UIM/G
UIM boards with two clock sockets, so one CLKOUT interface can connect wi
th three shelves. The RCKG1 board has two CLKOUT interfaces providing si
x clock output lines, that is , it can connect with six shelves.
GPS
8KIN
Reference GPS Unit
2Mbps/2MHz Selection Unit
PP2S/16CHIP
8K ,16M, 32M , 64M
PLL Unit
CLKOUT
Oscillastor

RS232
CPU
RS485

Inner Bus
SBCX
 The SBCX board is the server board. It mounts the server on
the rack.
 It provides the keyboard, the mouse and the VGA interface.
 Uses Sossaman dual-path dual-core CPU with a frequency of
2G Hz.
 Supports multiple operating systems, including Windows XP/
2000/2003, Linux and Solaris.
 Provides three FE interfaces, two GE interfaces and one RS2
32 serial port.
 Provides four universal USB interfaces.
 Supports boot from hard disk and boot from USB drive.
SBCX
 OMC1(eth3) is set to an external network address to communicate wit
h NetNumen M31 server.
 OMP1(eth6) is set to an intranet address to communicate with the OM
P.
VGA
USB
CPU Outside Mouse( MS)
Dual Core Interface
KeyBoard(KB)

OMC1
OMC2
Outside OMP1
Interface
RS232
USB

SAS HD1
SAS
Controller
SAS HD2
DTB
 Provides 32 E1/T1 links for external connections.
 Supports extraction of 8K synchronization clock from the li
nes, which is transferred to the CLKG/ICM board through
the cable as clock reference.
 Supports 120/75 Ω impedance selection for E1 cables, an
d supports coaxial cables and twisted-pair cables.
 Supports 100 Ω twisted-pair T1 cables.
DTB
8KOUT/DEBUG-232
CP FE，RS232，RS485
CPU

Clock
Clock Unit

Back Board
Logic Unit

E1/T1 1~32

Circuit Switch HW
Interface Unit
Unit
DTB DIP Switches

S1
ON
S2
ON
S3
ON
S4
ON
S5
ON
ON S6
S7
ON ON
S8
ON S9
S10
ON ON
S11
S12
ON

X23
DTB DIP Switches
Switch Configuration Default Location
DIP Swit
Purpose
ch Mode 1 2 3 4 1 2 3 4

Used to set the resi 75 Ω ON ON ON ON

S1~S6 stances that match t
S9 he impedances of di ON ON ON ON
S12 fferent E1 paths to 7 120 Ω OFF OFF OFF OFF
5 Ω or 120 Ω.

Used for indicating t 75 Ω ON ON ON ON

he receiving matchi
S7
ng impedance of cor ON ON ON ON
S8
responding E1 chip
120 Ω OFF OFF OFF OFF
to the CPU.

SHORT
Used for reporting t ON ON ON ON
HAUL
S10 he long/short wire st
ON ON ON ON
S11 atus of each E1 chi
LONG
p to the CPU. OFF OFF OFF OFF
HAUL
RDTB Jumpers
 On the RDTB, the E1 cable work
s in the 75 Ω unbalanced coaxial
transmission mode by default.
 If the E1 line uses 120 Ω balance
d transmission mode, the short-ci
rcuit block at X9–X16 on the RDT
B needs to be removed.
 The sending end is grounded thr
ough the jumper. The receiving e
nd is connected to a capacitor an
d then grounded through the jum
per. Jumpers X9–X16 are used t
o complete such settings.
RDTP Jumpers
X9-X16 Pin Connection Definitions

1-2 Connect E1_TX （ N ） -R to the protection ground (Path N)

3-4 Connect E1_RX （ N ） -R to the protection ground (Path N)

Connect E1_TX （ N+1 ） -R to the protection ground (Path N

5-6
+1)
Connect E1_RX （ N+1 ） -R to the protection ground (Path
7-8
N+1)
Connect E1_TX （ N+2 ） -R to the protection ground (Path N
9-10
+2)
Connect E1_RX （ N+2 ） -R to the protection ground (Path
11-12
N+2)
Connect E1_TX （ N+3 ） -R to the protection ground (Path N
13-14
+3)
Connect E1_RX （ N+3 ） -R to the protection ground (Path
15-16
N+3)
SDTB2
 The SDTB2 acts as the digital trunk interface board. It pro
vides two 155M STM-1 standard interfaces.
 Supports CAS and CCS, and provides an access process
ing capacity equal to 126 E1 lines or 168 T1 lines.
 Outputs one path of differential 8 K synchronous clock sig
nals for the reference of the clock board
SDTB2

8KOUT/DEBUG-232
CP FE，RS232，RS485
CPU

Clock
Clock Unit

Back Board
Logic Unit

STM-1
Circuit Switch HW
STM-1 Interface Unit
Unit
SPB2
 According to its functions, the SPB2 board can be classified into the LAP
D processing board (LAPD2), the signaling processing board (SPB2) an
d the Gb interface processing board (GIPB2).
 The LAPD2 board processes LAPD signaling. LAPD signaling data from
the BTS are received by the DTB/SPB/SPB2 board, and then switched t
o the LAPD2 board through the circuit switching net on the UIM board in
the local resource shelf or the GUIM board in the local Gigabit resource
shelf. The LAPD2 completes the processing of LAPD signaling data.
 The SPB2 board processes MTP2 and X.25 protocols. It supports extrac
tion of 8 K synchronization clock from the lines, which is transferred to th
e CLKG board through the cable as clock reference.
 The GIPB2 board processes the FR, NS and partial BSSGP protocols fo
r the GPRS, and provides Gb interfaces.
SPB2
CPU4-RS232
CPU 4

CPU3-RS232 CP FE
CPU 3
Ethernet
Switch Unit UP FE
CPU2-RS232 CPU 2

8KOUT/CPU1-RS232
CPU 1

Back Board
RS232，RS485

Clock
Clock Unit
Logic Unit

E1/T1 1~16

Circuit Switch HW
Interface Unit
Unit
SPB2
 Interface unit, which connects with the switching unit and
provides E1 interfaces.
 Circuit switch unit, which implements the switching betwe
en interface unit circuits and backplane circuits.
 CPU, which implements signaling processing, board man
agement and internal connection control.
 Ethernet Switch Unit, which implements control plane and
user plane data switch and provides FE interfaces.
 Clock Unit, which extracts line clock signals and sends th
em to the ICM board.
 Each SPB2 board contains four CPUs.
 Each SPBs board provides 16 E1/T1 interfaces.
GIPI
 The GIPI board provides IP interfaces between iBSC and the B
TS, the SGSN and the MSC/MGW.
 Implements Layer 3 protocol interface processing, separates c
ontrol plane data from user plane data, and sends the data res
pectively to the Ethernet interfaces on the internal control plane
and user plane.
 According to functions, GIPI can be classified into four function
al boards:
Abis interface Gigabit IP interface board(IPBB)
A interface Gigabit IP interface board IPAB(Signaling)
A interface Gigabit IP interface board IPI （ signaling and service ）
Gb interface Gigabit IP interface board(IPGB)
GIPI
 The Interface Unit receives data and sends it to the service processing unit, wh
ich separates user plane data from control plane data. User plane data is then
sent to the GUP2 through the user plane switch network, and control plane dat
a is sent to the CMP through the control plane switch network.
 The GIPI board can choose RGER (providing one GE interface) or RMNIC (pro
viding four FE interfaces) as its rear board.

Processing Unit GE1

GE2

RS232 DEBUG1-232
Back Board

CPU Interface
Unit DEBUG2-232

Logic Unit

CP FE, UP GE
EIPI
 The EIPI board provides E1 or T1 based IP connection and
works together with the DTB. It has no external interface a
nd no rear board. One EIPI works together with two DTBs t
o provide up to 64 E1 or T1 ports.
EIPI
 The interface unit receives HW data and sends it to the HPS daughter
card. The data is then processed according to the HDLC protocol and t
hen sent to the service processing unit. It sends user plane data throu
gh the user plane switch network to the GUP2 for processing, and sen
ds control plane data through the control plane switch network to the C
MP for processing.
HW
HPS Subcard

Processing Unit

Interface
Back Board

Unit
RS 232
CPU

Logic Unit

CP FE , UP GE , HW
GUIM
 The GUIM performs Ethernet Level 2 switching between the control p
lane and the user plane in the Gigabit resource shelf, the CS field tim
eslot multiplexing slot switching and Gigabit resource shelf managem
ent. It also provides external interfaces for the Gigabit resource shelf.
 It has the capability of 16 K circuit switching, and provides an internal
circuit switching network for the GE resource shelf.
 It provides the clock drive in the resource shelf. It inputsPP2S, 8K an
d 16M signals, which are sent to different slots in the resource shelf a
fter phase lockup to provide 16M, 8 K and PP2S clocks for resource
modules in this shelf.
 The UGIM board performs Gigabit resource shelf management and p
rovides RS485 management interfaces in the Gigabit resource shelf;
It also provides board resetting and in-slot signal collection functions.
GUIM
Circuit
Switch Unit

HW

Inner Bus

RS485
DEBUG 232
Logic Unit Clock Unit CPU

Inner Bus
Back Board

CP FE

CLKIN
UP GE

Ethernet 4*1 Gbps optical for UP

Switch Unit

CP FE 1~6
User Plane Control Plane
Switch Switch
GUP2
 According to functions, GUP2 boards are classified into five functional boards: Abis
interface processing board BIPB2, A interface processing board AIPB, user plane p
rocessing board UPPB2, dual rate transfer board DRTB2 and Ater interface proces
sing board TIPB2.
Over the STM-1 or E1 Abis interface, CS and PS services from the BTS are switch
ed to the BIPB2 board through the UIM board in the local resource shelf or the
GUIM board in the local Gigabit resource shelf. The BIPB2 board searches 20m
s TRU frames or PCU frames and form them into IP packets, which are sent to t
he TCU or the UPU for processing. Over the IP Abis interface, the BIPB2 board
is also used to process RTP.
The DRTB2 implements code conversion, finishes TRAU frame conversion and rat
e adaptation, and provides FR/EFR/HR/AMR/TFO function.
The AIPB board processes RTP and forms data into IP packets over the A interfac
e.
The UPPB2 processes user plane protocols such as BSSGP, PDCP and GTP_U u
nder the A/Gb mode.
GUP2
 Each GUP2 board has 15 DSPs.

HW

Circuit Switch Logic Unit Clock Unit

Unit

DSP Unit

Back Board
DSP
CPU P UP GE
Ethernet
Switch Unit
…

DSP
P

CP FE
GUP2
 CPU: responsible for board management, and provides c
ontrol plane FE interfaces for external connection.
 DSP: processes universal services, including functions of
BIPB2, AIPB, DRTB2, UPPB2 and TIPB2.
 Circuit Switch Unit: connects the serial ports of multiple-c
hip DSP with the circuit switching network.
 Ethernet Switch Unit: implements the Ethernet connection
s for multiple-chip DSP and provides the user plane FE int
erface for external devices.
 Clock Unit: provides necessary clock signals for the units
on the board.
GLI
 The GB Line Interface (GLI) board is located at level 1 swi
tching subsystem of iBSC. It finishes physical layer adapt
ation, IP package query, segmentation, forwarding, and fl
ow management functions, processes bi-directional 2.5G
bps forwarding, and implements the interfaces to different
resource shelves and external interface functions.
GLI
 Interface Unit: provides GE optical interface and supports physical ba
ckup. SD1–SD2, SD3–SD4, SD5–SD6 and SD7–SD8 are backup gro
ups.
 Processing Unit: implements bi-directional IP packet table look-up, fra
gmenting, forwarding and traffic management.
 Queue Management Unit: implements bi-directional queue managem
ent.
 The GE optical interface receives user plane data from the GUIM and
sends it through the backplane to the PSN board for user plane data
exchange.
SD1~SD8 (GE Optical)

Back Board
Optical&Ethernet Queue Management
Processing Unit
Interface Unit Unit

CP FE
Logic Unit CPU
PSN
 Provides bi-directional us Inner bus
er plane data switch with CP FE
CPU
a capacity of 40 Gbps on
each direction
 The data from each GLI b

Back Board
LVDS
oard is sent to the Matrix
Switching Unit through th
e high-speed serial links
on the backplane. It is swi
tched and then sent to th Logic Unit
e destination GLI board.

Matrix Switch Unit

Peripheral Monitor Unit (PMU)

 Includes the PWRD board and the alarm box

 PWRD is responsible for collecting some peripheral and envir
onment board information within the cabinet, including the po
wer distributor and fan status as well as some environment al
arms like temperature/humidity, smog, water and infrared ala
rms. Each cabinet has one PWRD board.
 The Alarm Box (ALB) can report system alarms at different le
vels according to system fault grades to facilitate timely interf
erence and handling by equipment management personnel.
Board Summary 1
Board Summary 2
Board Summary 3
Control Plane and User Plane Interconnection
BPSN BCTC
SBCX
PSN UIMC UIMC OMP HUB

GLI GLI CHUB CMP

BGSN BGSN
GUIM GUIM
UIMU(UIM_2) UIMU(UIM_2)
User Control User Control
Circuit Circuit
plane plane plane plane

DTB
GUP2 SPB2 GUP2 GIPI
SDTB2

E1 STM-1 IP

Abis/A /Gb iOMCR Client

Active/Standby Board Design
 Key boards have 1+1 backup.
 Key interface boards such as GIPI and SDTB can have 1+
1 backup if necessary.
 GLI and PSN boards work in the load sharing mode.
BGSN BCTC
OMP/CMP OMP/CMP
GUIM (Main) (Standby) (Main)

Control Plane

CHUB UIMC
User Plane
CHUB UIMC

GUIM (Standby) BPSN

Control Plane UIMC

GLI/PSN

User Plane GLI/PSN UIMC

General Description of Boards
 Front board and rear board
Rear boards are passive boards that provides cablin
g from the backplane (such as E1 and network cable
s) in order to work together with corresponding front
boards.
Front boards are physical boards that process resou
rces. All system optical cables are led from the front
board panels.
 All front boards have four indicators on their panels (
RUN, ENUM, ACT, ALM) to indicate board status.
Indicators on Board Panels
Indicator Color Meaning Description

Running ind Flashing at 1 Hz: the board is running normally

RUN Green
icator Flashing at 5 Hz: version downloading is in process.
Flashing at 5 Hz: version download fails; board self test fail
Alarm indic
ALM Red s because of inconsistency between board and configurati
ator
on
Solid on: the microswitch is opened; the board is not in po
sition; or version files are not downloaded.
Flashing at 5 Hz (quickly): the microswitch generates an al
Board extra arm because it is opened when the board is still running.
ENUM Yellow ction indicat
or Flashing at 1 Hz (slowly): the board can be extracted. The
microswitch is opened when the board is running, and the
board is in standby mode or release the resource.
Solid off: the microswitch is normal.
Active/stand On: the board is active.
ACT Green by status in
dicator Off: the board is standby.
Contents

 iBSC System Overview

 iBSC Hardware Structure
 iBSC Board Principles
 iBSC Interface Implementation and Logical Units
 Signal Flow on iBSC Control Plane and User Plane
 iBSC Internal Cable connection
iBSC Logical View
ZXG10 iBSC

CMPU

UPU
Access Switch
TC Unit
BTS Unit Unit

O& M Unit

MSC PMU

Power and Fans

SGSN
iBSC External Physical Interfaces
FE

E1
MSC / MGW SGSN
STM -- 1

A Gb

DTB/SDTB2/GIPI SPB2/ GIPI

iBSC

DTB /SDTB2/GIPI DTB /SDTB2 SBCX GIPI

Abis Ater

BTS iTC NetNumen OMCB MR

Access Unit–Abis Interface Unit (BIU)
 E1 Abis
 E1 borne TDM link
 IP Abis
 FE/GE borne IP link
 IPoE Abis
 E1 borne IP link
BIU - E1 Abis
The interface board can be the DTB or SDTB2 board. The access c
apacity of SDTB2 is four times that of the DTB.

E 1 Abis
to TCU or UPU
BIPB2
BIU
User Plane

GUP2
Switching
1 Network
GUIM
DT B

2
T to CMP
32
SPB2

Control Plane Switching Network

LAPD2

Internal
E1/T1 Ethernet HW
BIU - IP Abis
IP Abis
BIU
IPBB BIPB2

TCU

GUP2
GIPI

GUP2
UDP

User Plane
Switching
SCTP
Network

GUP2
to CMP UPU

Control Plane Switching Network

网

External Internal
Ethernet Ethernet HW
BIU - IPoE Abis
IPoE Abis

BIU
BIPB2
1 TCU
2

GUP2
DTB

EIPI
32 RTP RTP

GUP2
c UDP c UDP
ML/ MC - PPP
PPP UDP
HDLC
User Plane
SCTP Switching
IP Network

GUP2
UDP

to CMP
UPU
Control Plane Switching Network

Internal
E1/ T1 Ethernet HW
Access Unit- A Interface Unit (AIU)
 E1 A
 E1 borne TDM link
 IP A
 FE/GE borne IP link
AIU - E1 A
E 1A

AIU

1
TCU 2

DTB
User Plane 32
GUP2

GUIM
Switching
Network
1

SPB2
2

16
Control Plane Switching Network MTP2

Internal
E1/T 1 Ethernet HW STM -1
AIU - IP A
IP A
AIU
IPI AIPB

GUP2
GIPI

RTP RTP
UDP UDP

BIPB2

User Plane UDP

Switching

GUP2
SCTP Network

to CMP

Control Plane Switching Network

External Internal
Ethernet Ethernet HW
Access Unit–Gb Interface Unit (GIU)
 E1 Gb
 E1 borne TDM link
 IP Gb
 FE/GE borne IP link
GIU - E1 Gb
E 1 Gb

UPPB2 GIU

GUP2
1
2

SPB2
User Plane 16
Switching
UDP
Network 1
2

SPB2
16
Control Plane Switching Network

to CMP

Internal
E1/ T1 Ethernet
GIU - IP Gb
IP Gb

GIU
IPGB UPPB2

GUP2
GIPI
UDP UDP

BIPB2

User Plane UDP

GUP2
Switching
Network

to CMP
Control Plane Switching Network

External Internal
Ethernet Ethernet HW
O&M Unit
 OMP Board
System operation and maintenance;
Connects to the iOMCR;
System management and monitoring

OMPP
Switching Unit

HH
OMP UU LMT -R
OMP
BB
SBCX
SVB

100 M Ethernet
Operation and Maintenance Networking
 The networking mode of SBCX is as follows: iBSC and SBCX(OM
P1) form a subnetwork, and SBCX(OMC1)+NetNumen for a subn
etwork. The local OMM usually consists of the SBCX and the SB
CX client (LMT).Usually, LMT and the OMM client are installed on
the same PC. The PC is then put in a different equipment room. T
he network interfaces of SBCX are connected to the switches of e
ach iBSC, and then connected to the router. Then the cables are
connected to the remote NetNument using WAN connection.
 When the iBSC needs to manage SDR BTSs, the OMCB server
manages all SDR configurations (physical, transmission and radio
configurations), links, alarms and versions. The OMCB program is
installed on the SBCX and a pair of GIPI boards must be configur
ed.
Operation and Maintenance Networking
Processing Units & Monitoring Units
 Processing Unit - CMPU
 CMP Board
 PS/CS Service Call and Control Management
 BSSAP, BSSGP and System Resource Management
 Monitoring Unit - PMU
 PWRD board
 The PWRD board collects the environment monitoring i
nformation of peripheral devices, including temperature
and humidity, smoke, water and infrared alarms.
UPU & TCU
 Processing Unit – UPU
 UPPB2: Processes PS protocols
 TransCoder Unit – TCU
 DRTB2: code transfer and rate adaptation
IP Switch Unit (PSU)
 Level 1 switch: GLI and PSN, 40G large-capacity user plane data switch.
 Level 2 switch: UIMU,GUIM, UIMC, and CHUB, responsible for the switch an
d convergence of control plane and user plane data in the system.

Switch Control
st nd
1 Switch Subsystem 2 Switch Subsystem

2*GE FE

nd nd
2 Switch Subsystem 2 Switch Subsystem

GE
FE

BGSN 1 BGSN N
IP Switch Unit (PSU)
 If there are only two resource shelves, the Level-1 switch subsystem is not n
eeded on the user plane. The two resource shelves can be directly interconn
ected using Gigabit optical interfaces.
Control
nd
2 Switch Subsystem

FE

nd nd
2 Switch Subsystem 2 Switch Subsystem
2*GE

GE
FE

BGSN 1 BGSN 2
Contents

 iBSC System Overview

 iBSC Hardware Structure
 iBSC Board Principles
 iBSC Interface Implementation and Logical Units
 Signal Flow on iBSC Control Plane and User Plane
 iBSC Internal Cable connection
User Plane Signal Flow in the CS Domain
 The BIU severs user plane data from control plane data, and then
sends user plane data to the TCU, which processes such data an
d then sends it to the AIU. Signal flow 1→2.

UPU TCU

User plane A Interface

Abis Interface AIU
1 switch network
BIU

Gb Interface
Control plane GIU
switch network

CMP OMP
User Plane Signal Flow in the PS Domain
 The BIU severs CPU frames from all frames and sends them to th
e UPU(UPPB2) through the user plane switching network. The U
PU then separates PS field user plane data from CPU frames rec
eived for further processing. After data processing is complete, th
e data is sent to the GUI through the user plane switching network.

UPU TCU

1 User plane 2 A Interface

Switching network AIU
Abis Interface
BIU

Control plane Gb Interface

Switching network GIU

CMP OMP
Control Plane Signal Flow in the CS Domain
 Abis interface signal flow Abis interface unit (BIU) sends signaling in the L
APD channel to the CMP board as control plane data. The CMP process
es such data and sends some of it directly back to the BIU (flow direction:
1→1). Some signaling data will be sent to the AIU in the form of A-interfa
ce signaling flow (flow direction: 1→2).
 A-interface signal flow: The AIU processes the MTP2 part of A-interface s
ignaling, and then sends it to the CMP to complete the processing of MT
P3 and layers above. Some global processes need the participation of th
e OMP. The data flow direction is 2→3→3→2 or 2→2.
UPU TCU
User plane A Interface
Abis Interface Switching network AIU
2
BIU

Gb Interface
1 Control plane GIU
Switching network

CMP OMP
Control Plane Signal Flow in the PS Domain
 For some control plane signaling in the PS field, the system requests res
ources from the CMP board, and then sends the signaling to the UPPB2 f
or processing.
 When the MS is processing PS services, control plane signaling should b
e separated from UPPB2 and then sent to the CMP for processing.

UPU TCU

User plane A Interface

2
Switching network AIU
Abis Interface
BIU
3
5 Gb Interface
1 Control plane GIU
Switching network

CMP OMP
Control Plane Signal Flow in the PS Domain
 Abis interface signaling flow
 The Abis interface unit (BIU) sends control plane data in the LAPD chann
el to the CMP board. The CMP processes such data and sends some of i
t directly back to the BIU (flow direction: 1→1). Some data, such as pack
et assignment messages, is sent to the UPU, which processes the data a
nd then sends it to the BIU through the user plane switch network (flow di
rection: 1→3→2).
 Data from the Abis interface unit is sent to the UPU through the user plan
e switch network. The UPU processes the data and separates control sig
naling packets, which are sent to the control plane processing board (CM
P).The data flow direction is: 2→3→3→2.
Control Plane Signal Flow in the PS Domain
 Gb interface signaling flow
 The GIU sends BVC channel data as control plane data to the active CM
P. The CMP processes the data and sends some of it (such as PTP BVC
restart) to other CMPs and some (such as signaling BVC restart) to the O
MP. The CMP or the OMP processes the data and some signaling gener
ates the Abis signaling traffic, such as paging messages in the PS or CS f
ield, whose data flow is 5→1 or 5→3→2; other signaling, such as PTP B
VC restart acknowledgement and signaling BVC restart acknowledgemen
t, is sent to the Gb interface through the GUI, with the data flow as 5→5 o
r 6→6.
 The GUI routes data from other BVC channels to the user plane processi
ng unit, which separates control plane data and sends it to the CMP. The
CMP processes the data and some signaling, such as PTP paging messa
ges, is sent to the Gb interface through the GIU with the data flow as 4→
3→5; some signaling generates the Abis signaling flow, such as location
messages, with the data flow as 4→3→1.
User Plane Board Signal Flow in the CS Domain
BPSN BCTC
 E1 Abis, E1 A SBCX

PSN UIMC UIMC OMP HUB

 The BIU severs user pla
ne data from control pla CHUB CMP
GLI GLI
ne data, and then sends
user plane data to the T
BGSN BGSN
CU, which processes su
GUIM GUIM
ch data and then sends i UIMU( UIM_ 2 ) UIMU( UIM_ 2)

t to the AIU. UP CP Circuit UP CP Circuit

 Signal flow 1→2.

BIPB2 LAPD2 DTB DRTB2 SPB2 DTB

E1 Abis E1 A

A iOMCR Client
Control Plane Board Signal Flow in the CS Domain
 E1 Abis, E1 A

 The Abis interface unit BPSN BCTC

SBCX
(BIU) sends signaling in UIMC
PSN UIMC OMP HUB
the LAPD channel to the
CMP board as control pl
ane data. The CMP proc GLI GLI CHUB CMP

esses such data and se

nds some of it generate BGSN BGSN
s the A interface signalin GUIM GUIM
UIMU( UIM_ 2 ) UIMU( UIM_ 2)
g flow to the AIU. UP CP UP CP
Circuit Circuit
 Signal flow 1→2.

BIPB2 LAPD2 DTB DRTB2 SPB2 DTB

E1 Abis E1 A

iOMCR Clien
User Plane Board Signal Flow in the CS Domain
 IP Abis, IP A

 The BIU severs user pla BPSN BCTC

SBCX
ne data from control pla PSN UIMC UIMC OMP HUB
ne data, and then sends
user plane data to the T
CU, which processes su GLI GLI CHUB CMP

ch data and then sends i

t to the AIU. BGSN BGSN

 Signal flow 1→2. GUIM

UIMU( UIM_ 2 )
GUIM
UIMU( UIM_ 2)
UP CP Circuit UP CP Circuit

BIPB2 IPBB AIPB IPI

IP Abis IP A

iOMCR Client
Control Plane Board Signal Flow in the CS Domain
 IP Abis, IP A

 The Abis interface unit BPSN BCTC

SBCX
(BIU) sends signaling in PSN UIMC UIMC OMP HUB
the LAPD channel to the
CMP board as control pl
ane data. The CMP proc GLI GLI CHUB CMP

esses such data and se

nds some of it generate BGSN BGSN
s the A interface signalin GUIM
UIMU ( UIM _ 2 )
GUIM
UIMU ( UIM_ 2)
g flow to the AIU. UP CP Circuit UP CP Circuit
 Signal flow 1→2.

BIPB2 IPBB AIPB IPI

IP Abis IP A

iOMCR Client
User Plane Board Signal Flow in the PS Domain
 E1 Abis, E1 Gb

 The BIU severs CPU fra BPSN BCTC

SBCX
mes from all frames and PSN UIMC UIMC OMP HUB
sends them to the UPU
(UPPB) through the use
r plane switching networ GLI GLI CHUB CMP

k. The UPU then separa

tes PS field user plane d BGSN BGSN

ata from CPU frames re GUIM

UIMU( UIM_ 2 )
GUIM
UIMU( UIM_ 2)
ceived for further proces UP CP Circuit UP CP Circuit
sing. After data processi
ng is complete, the data
is sent to the GUI throug BIPB2 LAPD2 DTB UPPB2 GIPB2
h the user plane switchi
ng network.
E1 Abis E1 Gb
 Signal flow 1→2.
iOMCR Client
Control Plane Board Signal Flow in the PS Domain
 E1 Abis, E1 Gb

 The Abis interface unit BPSN BCTC

SBCX
(BIU) sends control plan UIMC
PSN UIMC OMP HUB
e data in the LAPD chan
nel to the CMP board. T
he CMP processes such GLI GLI CHUB CMP

data and sends some of

it to the UPU (such as p BGSN BGSN
acket assignment mess GUIM GUIM
UIMU ( UIM _ 2 ) UIMU ( UIM_ 2)
age). The UPU process
UP CP Circuit UP CP Circuit
es such data and then s
ends it to the BIU throug
h the user plane switch DTB GIPB2
BIPB2 LAPD2 UPPB2
network.
 Signal flow 1→3→2.
E1 Abis E1 Gb

iOMCR Client
Control Plane Board Signal Flow in the PS Domain
 E1 Abis ， E1 Gb

 The GIU sends BVC ch BPSN BCTC

SBCX
annel data as control pla UIMC
PSN UIMC OMP HUB
ne data to the main CM
P. The CMP processes t
he data and some signal GLI GLI CHUB CMP
ing generates the Abis s
ignaling flow, such as pa BGSN BGSN
ging messages in the C GUIM GUIM
UIMU ( UIM _ 2 ) UIMU ( UIM _ 2)
S field
UP CP Circuit UP CP Circuit
 Signal flow 5→3→2.

BIPB2 LAPD2 DTB UPPB2 GIPB2

E1 Abis E1 Gb

iOMCR Client
User Plane Board Signal Flow in the PS Domain
 IP Abis, IP Gb

 The BIU severs CPU fra BPSN BCTC

SBCX
mes from all frames and PSN UIMC UIMC OMP HUB
sends them to the UPU
(UPPB) through the use
r plane switching networ GLI GLI CHUB CMP

k. The UPU then separa

tes PS field user plane d BGSN BGSN

ata from CPU frames re GUIM

UIMU( UIM _ 2 )
GUIM
UIMU( UIM _ 2)
ceived for further proces UP CP Circuit UP CP Circuit
sing. After data processi
ng is complete, the data
is sent to the GUI throug BIPB2 IPBB UPPB2 IPGB

h the user plane switchi

ng network. IP Abis IP Gb
 Signal flow 1→2.
iOMCR Client
Control Plane Board Signal Flow in the PS Domain
 IP Abis, IP Gb

 The Abis interface unit BPSN BCTC

SBCX
(BIU) sends control plan PSN UIMC UIMC OMP HUB
e data in the LAPD chan
nel to the CMP board. T
CMP
he CMP processes such GLI GLI CHUB

data and sends some of

it to the UPU (such as p BGSN BGSN

acket assignment mess GUIM

UIMU( UIM _ 2 )
GUIM
UIMU( UIM _ 2)
age). The UPU process UP CP Circuit UP CP Circuit

es such data and then s

ends it to the BIU throug
h the user plane switch BIPB2 IPBB UPPB2 IPGB

network.
 Signal flow 1→3→2. IP Abis IP Gb

iOMCR Client
Control Plane Board Signal Flow in the PS Domain
 IP Abis, IP Gb

 The GIU sends BVC ch BPSN BCTC

SBCX
annel data as control pla PSN UIMC UIMC OMP HUB
ne data to the main CM
P. The CMP processes t
CMP
he data and some signal GLI GLI CHUB

ing generates the Abis s

ignaling flow, such as pa BGSN BGSN

ging messages in the P GUIM

UIMU( UIM _ 2 )
GUIM
UIMU( UIM _ 2)
S or CS field UP CP Circuit UP CP Circuit

 Signal flow 5→3→2.

BIPB2 IPBB UPPB2 IPGB

IP Abis IP Gb

iOMCR Client
IP over E1 Signal Flow
 IPoE User Plane Signal Flow  IPoE Control Plane Signal Flow

BGSN BGSN
GUIM GUIM
UIMU ( UIM _ 2 ) UIMU ( UIM _ 2 )
UP CP Circuit UP CP Circuit

BIPB2 EUIP DTB BIPB2 EUIP DTB

IPoE Abis IPoE Abis

Contents

 iBSC System Overview

 iBSC Hardware Structure
 iBSC Board Principles
 iBSC Interface Implementation and Logical Units
 Signal Flow on iBSC Control Plane and User Plane
 iBSC Internal Cable connection
System Interconnection Modes
 Most boards are managed by the OMP via the internal control plane.
 The CLKG/ICM board are connected to the UIMC via the RS485 bus, and
then managed by the OMP.
 The PWRD board is directly managed by the OMP via the RS485 bus.

OMP OMC-R

P C S M D V S G C C G P U
W L P N T T D U M H L S I
R K B I B C T I P U I N M
D G C D B M B C

RS485 Ethernet
Internal Communications Management
BPSN BCTC in 1# Rack

UIMC OMP
Signal
GLI UIMC CHUB CLKG

PWRD
in Each
User
Control Rack
Plane GUIM
Ethernet Plane CLKG
Ethernet
BGSN1
User Plane Ethernet UIMC
GUIM

Circuit Switch
BGSN2 Shelf
System Clock Capture and Distribution Princi
ples
 The CLK board is responsible for s
upplying clock signals and external
BITS interface，Line 8K reference GPS reference
synchronization functions.
 Clock level: Level 3 clock BCTC

 The board extracts clock reference ICM/CLKG

via A Iu interface and drives multipl
e channels of timing reference sign 8K reference 8K， 16M 8K， 16M
als for use by each interface shelf a Differential signals Differential signals Differential signals
fter intra-board synchronization.
BGSN BPSN
 Level 2 forwarding of the UIM boar
d GUIM UIMC
 DTB, SDTB2 and SPB2 can be use
d to extract line reference DTB SPB2 SDTB2 GLI GLI
 The BPSN does not need a clock r
eference
E1 STM-1
Intra-shelf Cable Connection
 Clock extraction and distribution cables;
 Control plane and Ethernet interconnection cables;
 User plane optical cable connection;
 Monitoring cable.
Clock Extraction and Distribution Cables
 The clock extraction cable c
onnects the 8KOUT interfac Power distributionsubrack
e on the DTB rear board to t
Fan subrack
he 8KIN interface on the IC G
M. BGSN
U
I
M
 The ICM can also extract G
C
PS signals as the clock refer BCTC
U
I
O
M
I
C H
M U
ence. C P M
B

 The clock distribution cables G

U
connect the CLKOUT interfa BGSN I
M
ce on the ICM rear board to t
U
he CLKIN interfaces on UIM BPSN I
M
boards in each shelf. C
Control Plane and Ethernet Interconnection C
ables
 The FE interfaces of the CH
UB rear boards connect to th Power distribution subrack
e FE interfaces of the UIM b Fan subrack
oards in each shelf. G
U
BGSN
 Internal GE connection is us I
M
ed inside the BCTC. U C
O I
I H
BCTC M M C U
C P M B
G
U
BGSN I
M
U
I
BPSN M
C
User Plane Optical Cable Connection
 The optical interface on the
GUIM front panel in the BGS Power distribution subrack
N connects to the optical int Fan subrack
erface on the GLI front panel. G
U
BGSN I
M

U C
O I
I H
BCTC M C
M U
P M
C B

G
U
BGSN I
M
U
G
I
BPSN L
M
I
C
Monitoring Cables
 The cables between fans to PWRD Sensor
boards are usually 120 ohm twiste
d-pair cables that are connected to t Cabinet-top fan
he FANBOX interfaces to monitor fa
n running status. Power distribution subrack
Fan subrack
 The environment monitoring sensor
G
is connected to the SENSORS inter BGSN
U
I
face on the PWRD board to collect M

environment alarms. U
I O I C
H
BCTC M
M C
U
 The door access sensor is connect C
P M
B

ed to the DOOR interface on the P Fan subrack

WRD board to monitor door access G

U
BGSN I
status. M

 The PWRD board reports monitorin G U

I
BPSN L
M
g information to the OMP board via I
C

RS485 cables. Fan subrack