Dpu4f
Dpu4f
Dpu4f
IDE BUS
NET B
I/O BACKPLANE
ETHERNET
CON’TR CONTROLLER PCI BUS
PCI
INTERFACE SHARED SHARED
CHIP RAM FPGA RAM
ETHERNET
BACK CONTROLL
UP
ER
CON’TR
CONTROL IOM
PROCESSOR PROCESSOR
(CP) (IOM)
NETWORK STATUS LEDs REPORT THE STATUS OF THE maxNET NETA & NETB
LINKS.
BACKUP PORT A 100MBPS ETHERNET INTERFACE IS PROVIDED TO
PASS DATABASE INFORMATION TO A HOT STANDBY
DPU
BACKUP LED INDICATES REDUNDANY STATUS OF DPUS
CONFIGURED AS A BACKUP PAIR.
IOM STATUS LED INDICATES OPERATIONAL STATE OF THE IOM
PROCESSOR.
I/O STATUS LED INDICATES STATUS OF THE I/O BUS TRANSACTIONS
RESET BUTTON PRESSING THIS BUTTON WILL CAUSE THE DPU TO STOP
CONTROLLING & GO THROUGH A RESET CYCLE.
TAKEOVER BUTTON PRESSING THIS BUTTON WILL CAUSE A PREVIOUSLY
INACTIVE DPU TO GO ACTIVE.
SERIAL PORT (OPTIONAL) OPTIONAL RS232 SERIAL PORT WITH RJ45 CONNECTOR
FOR INTERFACING WITH EXTERNAL PLC TYPE DEVICES.
IRIG-B PORT (OPTIONAL) BNC CONNECTOR WHICH SUPPORTS AN INTERFACE TO A
GPS RECIEVER. THIS OPTION ALLOWS TIME
SYNCHRINISATION TO GLOBAL TIME.
DPU4F –MODE SWITCH DEFINITIONS
DPU4F –MODE SWITCH DEFINITIONS (cont…)
LED STATUS DURING NORMAL DPU OPERATION
DPU4F- COMPACT FLASH MEMORY
THE DPU 4F USES A COMPACT FLASH FOR STORING ALL SOFTWARE &
CONFIGURATION INFORMATION. IT IS NON-VOLATILE & CAN BE
MOVED FROM ONE DPU TO ANOTHER.
THE COMPACT FLASH CONTAINS WIN CE .NET OS., IOM FIRMARE ,
FIRMWARE FOR SHARED MEMORY FPGA , FIRMEARE FOR IOM
FPGA, IOM DIAGNOSTIC CODE ,BIOS FIRMWARE & THE DPU
INITIALIZATION FILE.
THE DPU INITIALIZATION FILE CONTAINS THE DPU NAME ,IP ADDRESS
& OTHER CONFIGURATION INFORMATION.
CHANGING THE IP ADDRESS & DPU NAME IN THE INITIALIZATION
FILE CAN BE ACCOMPLISHED THRO THE DPU4F SETUP UTILITY
WITH THE DPU IN MODE ‘C’.
REDUNDANT DPU OPERATION
• IN REDUNDANT OPERATION TWO DPUS ARE CONNECTED TO FORM A
BACKUP PAIR.
• ONE DPU IS DESIGNATED AS THE PRIMARY AND THE OTHER DPU , THE
SECONDARY.
• THE IP ADDRESS OF THE SECONDARY DPU IS ONE NUMBER GREATER
THAN THE ADDRESS OF THE PRIMARY DPU.
• THE PRIMARY IS ALWAYS AN EVEN ADDRESS WHILE THE SECONDARY IS
AN ODD ADDRESS.
• INFORMATION BETWEEN THE BACKUP PAIR IS EXCHANGED BY MEANS OF
A 100MBPS ETHERNET INTERFACE. A CAT5e ETHERNET CABLE IS USED TO
CONNECT THE TWO DPUS TOGETHER.
• PROCESS CONTROL CAN BE TRANSFERRED AUTOMATICALLY(FAILOVER)
OR MANUALLY BETWEEN PRIMARY & SECONDARY.
• AUTOMATIC FAILOVER CAN OCCUR FROM EITHER THE PRIMARY DPU TO
THE SECONDARY DPU OR FROM THE SECONDARY TO THE PRIMARY
BASED ON THE HEALTH OF BOTH.
• ALSO DPU CAN BE COMMANDED TO TAKEOVER MANUALLY BY PRESSING
THE TAKEOVER BUTTON ON THE FRONT PANEL OF THE MODULE.
DPU4F-module
OPERATOR INTERFACE