Platform Based Design Group

Outline
• Introduction to hardware description language (HDL)
– Why it is better than schematic entry
• Verilog 語法
– Lexical convention of Verilog
– Data types
– Structural Verilog
– Functional Verilog
• One language, many coding styles
• Continuous v.s. procedural assignments
• Blocking vs NonBlocking
VLSI Signal Processing Lab.

• Control statements
• For loop and parameterized design
• SystemVerilog
• Gotchas 正確的使用方法 <= ( 會踩到的陷阱 )

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VERILOG 語法
VLSI Signal Processing Lab.

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 Platform Based Design Group

LEXICAL CONVENTION OF VERILOG

VLSI Signal Processing Lab.

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 Platform Based Design Group

Lexical Convention: Identifier

• Verilog is a case sensitive language - keywords are lower case
• Terminate lines with semicolon ;
• Identifiers:
– Starts only with a letter or an _(underscore), can be any sequence of letters (a-z,
A-Z), digits (0-9), $, _
– Case-sensitive abc != Abc
• Example
– shiftreg_a, _bus3, n$657
VLSI Signal Processing Lab.

和 C 一樣，大小寫有差
只能字母 _ 開頭
後接字母數字 $_ ，
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Reserved keywords

and always assign attribute begin buf bufif0 bufif1

case cmos deassign default defparam disable else endattribute
end endcase endfunction endprimitive endmodule endtable endtask event
for force forever fork function highz0 highz1 if
initial inout input integer join large medium module
nand negedge nor not notif0 notif1 nmos or
output parameter pmos posedge primitive pulldown pullup pull0
pull1 rcmos reg release repeat rnmos rpmos rtran
rtranif0 rtranif1 scalared small specify specparam strong0 strong1
VLSI Signal Processing Lab.

supply0 supply1 table task tran tranif0 tranif1 time

tri triand trior trireg tri0 tri1 vectored wait
wand weak0 weak1 while wire wor

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• Escaped identifiers (\)

– Permit non alphanumeric characters in Verilog name
– The escaped name includes all the characters following the backslash
until the first white space character

wire \fo+o=a ; // Declare the varaible

fo+o=a=a
VLSI Signal Processing Lab.

wire \fo+o =a ; // Assign a to wire fo+o

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Find the bug

• Illegal identifier
– 12_reg, $abc, a*b_net, n@238

• Answer: Error part

– 12_reg, $abc, a*b_net, n@238
– illegal, cannot start with digits, or $
VLSI Signal Processing Lab.

– Cannot contain special character like *, @

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Lexical Convention: White Space and Comments

• white space: ignored, used for readability
• Single-line comments begin with // and end with a new-line character.
• Multiple-line comments start with /* and end with */ .

module MUX2_1 (out,a,b,sel);

// Port declarations, this is a single line comment
output out; 註解寫法和 C 一樣
input sel, // control input
b, /* data inputs */
a; /* The netlist logic selects input ”a”
when sel = 0 and it selects ”b” when sel = 1. */
VLSI Signal Processing Lab.

not (sel_, sel);

and (a1, a, sel_), (b1, b,sel); // What does this line do?
or (out, a1, b1);
endmodule

9
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Coding Style: Naming Conventions

• Consistent naming convention for the design

命名建議規則
• Lowercase letters for signal names: valid 讓三個月後的自己也可看的懂
• Uppercase letters for constants: MAX
• clk sub-string for clocks: in_clk
• rst sub-string for resets: g_rst
• Suffix
– _n for active-low, _z for tri-state, _a for async , …: rst_n, out_z
VLSI Signal Processing Lab.

• [name]_cs for current state, [name]_ns for next state

• Identical(similar) names for connected signals and ports
• Consistency within group, division and corporation

copyright © 2004 10
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 Platform Based Design Group

Special Language Tokens: $

For System Tasks and Functions

$<identifier>
• The ‘$’ sign denotes Verilog system tasks and functions.
• A number of system tasks and functions are available to perform different operations, such
as:
– Finding the current simulation time ($time))
– Displaying/monitoring the values of the signal ($display, $monitor)
VLSI Signal Processing Lab.

– Stopping the simulation ($stop)

– Finishing the simulation ($finish)
$monitor ($time, “a = %b, b = %h”, a, b);

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 Platform Based Design Group

Special Language Tokens: #

Delay Specification

The pound sign (#) character denotes the delay specification for
procedural statements, and for gate instances but not module
instances.
• The # delay for gate instances is referred to by many names, including gate delay, propagation delay, intrinsic
delay, and intra-object delay.
module MUX2_1 (out, a, b, sel) ;
output out ;
input a, b, sel;
VLSI Signal Processing Lab.

not #1 not1(sel_,sel);
and #2 and1(a1,a,sel_);
and #2 and2(b1,b,sel);
or #1 or1(out,a1,b1);
endmodule
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Compiler directives
• The directives start with a grave
accent ( ` ) followed by some `include “file1.v”
keyword // Used as `WORD_SIZE in code
`define WORD_SIZE 32
`define
Text-macro substitution module test ();
`ifdef TEST
`ifdef, `ifndef, `else, // A implementation
`else
`endif
// B implementation
Conditional compilation
VLSI Signal Processing Lab.

`endif
assign out = `WORD_SIZE{1’b1};
`include endmodule

File inclusion

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 Platform Based Design Group

Basic lexical conventions in Verilog

• Comments
– Single line: //
– Multi line: /* */
• Case sensitive
– Verilog keywords: lower case
– Others: lower case != upper case 和 C 一樣，大小寫有差
• AaBb != aabb
• 建議
VLSI Signal Processing Lab.

– 變數都用小寫
– 常數都用大寫
– clk sub-string for clocks
– rst sub-string for resets
14
– _n for active-low N C T U . E E , Hsinchu, Taiwan
 Platform Based Design Group

Outline
• Introduction to hardware description language (HDL)
– Why it is better than schematic entry
• Quick overview of Verilog
• Verilog 語法
– Lexical convention of Verilog
– Data types
– Structural Verilog
– Functional Verilog
• One language, many coding styles
• Continuous v.s. procedural assignments
VLSI Signal Processing Lab.

• Blocking vs NonBlocking
• Control statements
• For loop and parameterized design
• SystemVerilog
• Gotchas 正確的使用方法 <= ( 會踩到的陷阱 )

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 Platform Based Design Group

DATA TYPE REPRESENTATION

VLSI Signal Processing Lab.

了解 VERILOG 資料型態

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4-Value Logic System in Verilog

Verilog data type is a bit-vector where bits can take on one of four values Hardware meaning

Value Meaning
0 Logic zero (false)
1 Logic one (True)
X Unknown logic value or conflict
Z High impedance, floating
(unconnected input are set to z)
VLSI Signal Processing Lab.

unconnected

An X bit might be a 0, 1, Z, or in transition. We can set bits to be

X in situations where we don’t care what the value is. This can
help catch bugs and improve synthesis quality.

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 Platform Based Design Group

Logic Values
• Logic with multilevel (0,1,X,Z) logic values
– NAND anything with 0 is 1
– NAND with X/Z get an X
• True tables define the how outputs are compute
• Z is treated as X
& 0 1 X Z | 0 1 X Z
VLSI Signal Processing Lab.

0 0 0 0 0 0 0 1 X X
1 0 1 X X 1 1 1 1 1
X 0 X X X X X 1 X X
Z 0 X X X Z X 1 X X

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 Platform Based Design Group

Verilog includes ways to specify

Number in various bases
• Binary literals
– 8’b0000_0000
4’b10_11 – 8’b0xx0_1xx1
• Hexadecimal literals
Underscores
are ignored
– 32’h0a34_def1
– 16’haxxx
Base format
(d,b,o,h) • Decimal literals
– 32’d42
VLSI Signal Processing Lab.

Decimal number
representing size in bits
We’ll learn how to
actually assign literals to
nets a little later

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 Platform Based Design Group

Number Representation
Size: number of bits (optional)
• Integer
– Syntax: <size>’<base format><value>
• Decimal: 8’d79
• Binary: 8’b0100_1111 Underscore _ is ignored, for easy to read
• Octal: 8’o117
• Hexadecimal: 8’h4f = 8’h4F
– Negative value stored by 2’d complement
– Bit value
• 1, 0: logic high and low
VLSI Signal Processing Lab.

• Z: high impedance
• X: unknown
• ?: don’t care
– Default size is 32-bits decimal number
• When no base is specified 20
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 Platform Based Design Group

More examples
• Example
4’b0 // 4-bit 0000
4’b1001 // 4-bit 1001
8’b1111_1111// 8-bit 1111 1111, ‘_’ underscore can be use for readability
16’hfe12 // 16-bit 1111 1110 0001 0010
9’o457 // 9-bit 100 101 111
8’d220 // 8-bit decimal 220
-8’d12 // 8-bit decimal -12
8’d-12 // illegal
VLSI Signal Processing Lab.

12’h12x // 12-bit 0001 0010 xxxx

12’h12z // 12-bit 0001 0010 zzzz

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 Platform Based Design Group

Numbers: Extended Number

<size>’<base><value>
• Rule if <size> and <value> does not match
• Smaller: <size> < <value>
– left-most bits of <value> are truncated
6’hca: 6-bit, store as 6’b00_1010 (truncated, not 1100_1010)

• Larger: <size> > <value>

– If MSB is 0, X or Z number is extended to fill MSBs with 0, X, Z respectively
VLSI Signal Processing Lab.

– If MSB is 1 number is extend to fill MSBs with 0/1, depending on the sign
6’ha: 6-bit, store as 6’b00_1010 (a => 1010, filled with 2-bit ‘0’ on left)
-3’b1=-3’b01=3’b111, (negative number, extended with 1)
3’b1 = 3’b001, (positive number, extended with 0)
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 Platform Based Design Group

More examples
• Example
//Unsized numbers (at least 32 bit)
123 // default: decimal radix, 32-bit width
‘d123 // decimal 123
‘h7B // hexdecimal 7B
`hxx // xxxx xxxx
//Sized numbers
16’d5 // 16-bit constant ‘b0000_0000_0000_0101
11’h1X? // 11-bit constant ‘b001_XXXX_ZZZZ
VLSI Signal Processing Lab.

//signed numbers
8’shFF // 8-bit signed constant,2’s complement -1
-8’d12 // -12
To be absolutely clear in your intent it’s usually best to explicitly specify the width and base
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 Platform Based Design Group

Data type
• Net
– Structural connection between components
wire, tri Interconnecting wire - no special resolution function
wor, trior Wired outputs OR together (models ECL)
wand, triand Wired outputs AND together (models open-collector)
tri0, tri1 Net pulls-down or pulls-up when not driven
supply0, supply1 Net has a constant logic 0 or logic 1 (supply strength)
trireg Retains last value, when driven by z (tristate).
• Register
– Variable to store data
VLSI Signal Processing Lab.

reg Unsigned variable

integer Signed variable - 32 bits
time Unsigned integer - 64 bits
real Double precision floating point variable
string e.g. “internal error”, \n, \t

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 Platform Based Design Group

Data types (Nets): wire

• Nets (wire) correspond to physical wires that connect
instances
– Nets do not store values
– Have to be continuously driven
– The default range is one bit
– By default are unsigned
– Use in assign or structural Verilog
VLSI Signal Processing Lab.

• The wire declaration is used most frequently, other net types

are wand, wor, tri, triand, trior, etc.
wire c, d; // 1-bit wire c and 1-bit wire d
wire [7:0] a; // 8-bit wire a with msb=a[7] and lsb=a[0]
wire [0:7] a; // 8-bit wire a with msb=a[0] and lsb=a[7], avoid this
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 Platform Based Design Group

Data Types: reg

• A reg (reg) stores its value from one assignment to the next
(model data storage elements)
– Don’t confuse reg with register (DFF)
– synthesized to a register (DFF) or a physical wire (interconnection) according its
behavior.
– Default value is X (unknown)
– Default range is one bit
– By default are unsigned, but can be declare signed, using keyword
VLSI Signal Processing Lab.

signed
– Used for RHS variables in always/initial procedural statements
reg c, d; // 1-bit c and 1-bit d
reg [7:0] a; // 8-bit a with msb=a[7] and lsb=a[0]
reg [0:7] a; // 8-bit a with msb=a[0] and lsb=a[7], avoid this
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 Note. reg wire 傻傻分不清
• wire: Verilog 的預設資料型態 ( 用在 structural Verilog ouput)
– assign 的輸出，用 wire
– structure 連接，也用 wire
• Reg ( 用在 behavioral Verilog output)
– 和 register (DFF) 沒半點關係，純粹是歷史原因
– Procedural block 的 輸出，都要用 reg
• always, initial, fork join

• 好麻煩，有簡單一點的嗎 ?
• logic
VLSI Signal Processing Lab.

– 全部都可以改用 logic 取代，用法一樣 (SystemVerilog)

– logic [7:0] a;
– input logic [7:0] a;
– output logic [7:0] a;
logic
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Verilog vectors
Known as BUS in hardware
• Declare by a range following the type
<data type> [left range : right range] <Variable name>
• Single element that is n-bits wide
reg [0:7] a, b; //Two 8-bit reg with MSB as the 0th bit
wire [3:0] data; //4-bit wide wire MSB as the 4th bit
• Vector part select (access)
a[5] // bit # 5 of vector a
VLSI Signal Processing Lab.

data[2:0] // Three LSB of vector Data

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 Platform Based Design Group

Bit extraction and combination

• Bit-selecting
a = b[0]; 7 6 5 4 3 2 1 0 a
• Part-selecting
3 2 1 0 b
a = b[3:0];
c = b[7:4];
7 6 5 4 3 2 1 0 3 2 1 0 c
• Concatenation
c = { a, b }; 7 6 5 4 3 2 1 0 d
VLSI Signal Processing Lab.

d = { a[7:2], b[1:0] };
7 6 5 4 1 0 0 1 e
e = { a[7:4], 4’b1001 };
f = { 2{a[7:4] }}; 7 6 5 4 7 6 5 4 f
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 Platform Based Design Group

The Verilog keyword wire is used to denote a

standard hardware net
wire [15:0] instruction; Absolutely no type safety
wire [15:0] memory_req; when connecting nets!
wire [ 7:0] small_net;
assign memory_req = instruction; assign small_net = instruction;

?
memory_req

instruction
instruction

small_net
VLSI Signal Processing Lab.

Only the lowest instruction[7:0] is assigned.

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 Platform Based Design Group

Verilog arrays
• Array: range follows the name
<datatype> <array name> [<array indices>]
reg B [15:0]; // array of 16 reg elements
• Array of vectors
<data type> [<vector indices>]<array name>[<array indices>]
reg [15:0] C [1023:0]; // vector with 1024 elements, each 16b
• Memory access
VLSI Signal Processing Lab.

<var name>[<array indices>] [<vector indices>]

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 Platform Based Design Group

Data storage and Verilog arrays

• Simple RAM model
module RAM (output [7:0] Obus,
input [7:0] Ibus,
input [3:0] Adr,
input Clk, Read
);
reg [7:0] mem[255:0];
reg [7:0] ObusReg;

assign Obus =
ObusReg;
VLSI Signal Processing Lab.

always @(posedge
Clk)
if (Read==1’b0)
mem[Adr]

= Ibus;
else
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 Platform Based Design Group

More Than 2-D Arrays

• Multi-dimensional array support in Verilog-2001
reg [7:0] ram [0:127] [0:3] ; //4 Bank RAM
$display(“ram[124][3] =%3h”, ram[124][3]); //ram[124][3] = 05a

...
Vector
VLSI Signal Processing Lab.

Memory
(Array)

Memory bank

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 Platform Based Design Group
VLSI Signal Processing Lab.

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 Platform Based Design Group

Exercise
https://hdlbits.01xz.net/wiki/Vector2 https://hdlbits.01xz.net/wiki/Vector3
• reverse the byte ordering of the 4-byte
word.

• AaaaaaaaBbbbbbbbCcccccccDdddddd
d =>
DdddddddCcccccccBbbbbbbbAaaaaaa
a
VLSI Signal Processing Lab.

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 Platform Based Design Group

BOOLEAN AND LOGIC OPERATORS

VLSI Signal Processing Lab.

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 Platform Based Design Group

Boolean operators
• Bitwise operators perform bit-oriented operations on vectors
~(4’b0101) = {~0,~1,~0,~1} = 4’b1010
4’b0101 & 4’b0011 = {0&0, 1&0, 0&1, 1&1} = 4’b0001
• Reduction operators act on each bit of a single input vector
&(4’b0101) = 0 & 1 & 0 & 1 = 1’b0
• Logical operators return one-bit (true/false) results
!(4’b0101) = 1’b0
VLSI Signal Processing Lab.

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 Platform Based Design Group

Verilog RTL includes many operators

in addition to basic boolean logic
// Four input multiplexer
module mux4( input a, b, c, d
input [1:0] sel,
output out );
assign out = ( sel == 0 ) ? a : If input is undefined we
( sel == 1 ) ? b : want to propagate that
( sel == 2 ) ? c : information.
( sel == 3 ) ? d : 1’bx;
endmodule
VLSI Signal Processing Lab.

// Simple four bit adder

module adder( input [3:0] op1, op2,
output [3:0] sum );
assign sum = op1 + op2;
endmodule

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 Platform Based Design Group

Verilog RTL operators

Arithmetic + - * / % ** Reduction & ~& | ~| ^ ^~
Logical ! && || Shift >> << >>> <<<
Relational > < >= <= Concatenation { }
Equality == != === !=== Conditional ?:
Bitwise ~ & | ^ ^~

wire [ 3:0] net1 = 4’b00xx;

wire [ 3:0] net2 = 4’b1110;
wire [11:0] net3 = { 4’b0, net1, net2 };
VLSI Signal Processing Lab.

wire equal = ( net3 === 12’b0000_1110_00xx );

Avoid ( / % ** ) since the usually synthesize poorly

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 Platform Based Design Group

Operators Precedence
Operator Property
Arithmetic +, -, *
/, % Be careful to use these
Relational <, >, <=, >=
Equality ===, !== Including x, z comparison, for test
bench only
==, !=
Logic !, &&, ||
Bitwise ~, &, |, ^, ~^, ^~
Reduction &, ~&, |, ~|, ^, ~^, ^~ Multiple bit to 1 bit
Shift <<, >> Can be replaced by connection
<<<, >>> With signed extension, not used
Replication {n{m}} Duplicate m by n times
VLSI Signal Processing Lab.

Conditional A ? B : C;

41
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 Platform Based Design Group

Operator Examples
VLSI Signal Processing Lab.

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 Platform Based Design Group

Exercise
• https://hdlbits.01xz.net/wiki/Vectorgates

Bitwise vs. Logical Operators

VLSI Signal Processing Lab.

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 Platform Based Design Group

Outline
• Introduction to hardware description language (HDL)
– Why it is better than schematic entry
• Lexical convention of Verilog
• Data types
• Structural Verilog
• Functional Verilog
– One language, many coding styles
– Continuous v.s. procedural assignments
– Blocking vs NonBlocking
VLSI Signal Processing Lab.

– Control statements
– For loop and parameterized design
• SystemVerilog
• Gotchas

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 Platform Based Design Group

STRUCTURAL VERILOG
VLSI Signal Processing Lab.

VERILOG MODULES
STRUCTURES AND HIERARCHY
了解 VERILOG 模組與階層的寫法
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 Platform Based Design Group

Parameters
• Parameters are means of giving names to constant values
• The values can be overridden when the design is compiled
• Parameters cannot be used as variables
• Syntax:
parameter <name> = <constant expression>;
VLSI Signal Processing Lab.

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 Platform Based Design Group

Parameter declaration
• Default value need to be set at declaration time
• 32 bit wide by default, but may be declared of any width

parameter [2:0] IDLE = 3’d0;

• 2 declaration flavors:
Inside a module In module header
module test (... I/O’s ...) module test
VLSI Signal Processing Lab.

parameter ASIZE = 32, BSIZE =16; #(parameter ASIZE = 32, BSIZE =16)
//… (... I/O’s ...);
reg [ASIZE -1:0] Abus, //…
Zbus; wire [BSIZE-1:0] reg [ASIZE -1:0] Abus,
Bwire; Zbus; wire [BSIZE-1:0]
//… Bwire;
endmodule //…
endmodule
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 Platform Based Design Group

Example
module Adder (A, B, Cin, S,
A[N-1:0]
Cout, Clk); Adder S[N-1:0]
parameter N=8; B[N-1:0]
N-
input [N-1:0]A, B;
input Cin; Cin bits Cout
input Clk; (8 by default)
output [N-1:0] S; reg-ouputs
output Cout;
reg [N-1:0] S; Clk
reg Cout;
//module module Adder #(parameter N=8)
internals (input [N-1:0]A, B,
endmodule input Cin,
VLSI Signal Processing Lab.

input
Clk,
output reg
ANSI C style [N-1:0] S,
output reg
Cout Combine port and variable
); declaration
//module internals N C T U . E E , Hsinchu, Taiwan
 Platform Based Design Group

Structures and Hierarchy

• Instance of a module
– Instantiation is the process of “calling” a module
– Create objects from a module template
　 <module name> #(<param list>)
　 <instance name> (<port list>);
•Where:
<module name> Module to be instantiated
VLSI Signal Processing Lab.

<param list> Parameters values passed to the instance

<instance name> Identifies the instance of the module
<port list> Port list connection

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 Platform Based Design Group

Outline
• Introduction to hardware description language (HDL)
– Why it is better than schematic entry
• Quick overview of Verilog
• Verilog 語法
– Lexical convention of Verilog
– Data types
– Structural Verilog
– Functional Verilog
• One language, many coding styles
• Continuous v.s. procedural assignments
VLSI Signal Processing Lab.

• Blocking vs NonBlocking
• Control statements
• For loop and parameterized design
• SystemVerilog
• Gotchas 正確的使用方法 <= ( 會踩到的陷阱 )

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 Platform Based Design Group

FUNCTIONAL VERILOG
VLSI Signal Processing Lab.

用功能性 VERILOG 描述硬體設計

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 Platform Based Design Group

Levels of Abstraction
• One design, many coding styles to describe hardware functions

Faster simulation C / matlab /

systemC …
(Less detailed)

Behavior style Verilog: always

Dataflow style Verilog: assign
VLSI Signal Processing Lab.

Structural or gate level Verilog

Slower simulation
(More detailed)
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 Platform Based Design Group

Review: Gate-level Verilog uses structural

Verilog to connect primitive gates
module mux4( input a, b, c, d, input [1:0] sel, output out );
wire [1:0] sel_b; b d a c sel[1] sel[0]
not not0( sel_b[0], sel[0] );
not not1( sel_b[1], sel[1] );
wire n0, n1, n2, n3;
and and0( n0, c, sel[1] );
and and1( n1, a, sel_b[1] );
and and2( n2, d, sel[1] );
and and3( n3, b, sel_b[1] );
wire x0, x1;
nor nor0( x0, n0, n1 );
nor nor1( x1, n2, n3 );
VLSI Signal Processing Lab.

wire y0, y1;

or or0( y0, x0, sel[0] );
or or1( y1, x1, sel_b[0] );
nand nand0( out, y0, y1 );
endmodule
out

6.375 Complex Digital Systems N C T U . E E , Hsinchu, Taiwan

 Platform Based Design Group

One language, Many Coding Styles

AND2
A OR2
E
g1
B 1
3
g3 X Model combinational logic
NOT
C Y
2 g2

“Structural style” Dataflow style “Behavioral style”

Continuous assignment Procedural assignment
wire E; wire E; reg E, X, Y;
and g1(E,A,B); assign E = A & B; always @ (A or B or C)
not g2(Y,C); assign Y = ~C; begin
VLSI Signal Processing Lab.

or g3(X,E,Y); assign X = E | Y; E = A & B;

Same as schematic Y = ~C;
Similar to logic equations X = E | Y;
Use “assign” end
Similar to high level language
Difficult to synthesize
Use “always”
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 Platform Based Design Group

One language, Many Coding Styles

A
AND2
OR2
Model seq. logic
E
g1
B 1 g3 X
3

NOT
C Y
2 g2

“Structural style” Dataflow style “Behavioral style”

Continuous assignment Procedural assignment
wire E; wire E; reg E, X, Y;
and g1(E,A,B); assign E = A & B; always @ (A or B or C)
not g2(Y,C); assign Y = ~C; begin
VLSI Signal Processing Lab.

or g3(X,E,Y); assign X = E | Y; E = A & B;

Y = ~C; reg q;
Same as schematic Similar to logic equations always @ (posedge clk)
X = E | Y;
Use “assign” end q <= d;
wire q;
dff d1(.d(d), Similar to high level language
.clk (clk)) Difficult to synthesize
Use “always”
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 Platform Based Design Group

One language, Many Coding Styles

• Model combinational logic
– Structural style
– Continuous assignment
– Procedural assignment

• Model sequential logic

– Structural style
VLSI Signal Processing Lab.

– Procedural assignment

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 Platform Based Design Group

Continuous vs. Procedural Assignment

• Continuous assignment • Procedural assignment
– Like logic equations – a separate activity flow in Verilog
• Single line Verilog statement – For combinational logic or
• For simple logic • Single or multiple blocking Verilog
• Each assignment statement is executed statements
in parallel • Easy to describe complex logic
• Order does not matter • Order matters
– For combinational logic only – sequential logic
• Nonblocking Verilog statements
VLSI Signal Processing Lab.

• Executed in parallel
• Order does not matter
• Different procedural executed in
parallel

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 Platform Based Design Group

Concurrent blocks
• Blocks of code with no well-defined order relative to one
another
– Module instance is the most important concurrent block
– Continuous assignments, and procedural blocks are concurrent
within a module
– Note. Hardware is concurrently executed
VLSI Signal Processing Lab.

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 Platform Based Design Group

Continuous assignment statements assign one

net to another or to a literal
Explicit continuous assignment

wire [15:0] netA;

wire [15:0] netB;

assign netA = 16’h3333;

assign netB = netA;

Implicit continuous assignment • Implicit net declaration (not recommended)

– If a signal name is used to the left of a continuous
VLSI Signal Processing Lab.

wire [15:0] netA = 16’h3333; assignment, a implicit net declaration will be inferred
wire [15:0] netB = netA;

6.375 Complex Digital Systems N C T U . E E , Hsinchu, Taiwan

 Platform Based Design Group

Using continuous assignments to implement an

RTL four input multiplexer
Circuit topology
module mux4( input a, b, c, d
input [1:0] sel, t0
output out ); out
wire out, t0, t1; t1
assign t0 = ~( (sel[1] & c) | (~sel[1] & a) );
assign t1 = ~( (sel[1] & d) | (~sel[1] & b) );
assign out = ~( (t0 | sel[0]) & (t1 | ~sel[0]) );

endmodule 先後順序不重要
Same result if you write like this
VLSI Signal Processing Lab.

The order of these continuous assign out = ~( (t0 | sel[0]) & (t1 | ~sel[0]) );
assign t1 = ~( (sel[1] & d) | (~sel[1] & b) );
assignment statements does not matter.
assign t0 = ~( (sel[1] & c) | (~sel[1] & a) );
They essentially happen in parallel!
But better to follow the circuit topological order

6.375 Complex Digital Systems N C T U . E E , Hsinchu, Taiwan

 Platform Based Design Group

Exercise
• https://hdlbits.01xz.net/wiki/Conditional
VLSI Signal Processing Lab.

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 Platform Based Design Group

PROCEDURAL BLOCKS
VLSI Signal Processing Lab.

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 Platform Based Design Group

Procedural blocks
• Each procedural block represent a separate activity flow in
Verilog
• Procedural blocks
– always blocks
• To model a block of activity that is repeated continuously
– initial blocks simulation only
• To model a block of activity that is executed at the beginning
VLSI Signal Processing Lab.

• Multiple behavioral statements can be grouped using keywords

begin and end

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 Platform Based Design Group

Procedural assignments
• Procedural assignment changes the state of a reg
• Used for both combinational and sequential logic inference
• All procedural statements must be within always (or initial) block
Feel confusing?
reg A; Use logic
always @ (B or C)
Sensitivity list
begin Signal changes triggers
logic A;
A = ~(B & C); actions in the body always @ (B or C)
VLSI Signal Processing Lab.

end begin
A = ~(B & C);
end
Output should use reg declaration for variable

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 Platform Based Design Group

Always blocks have parallel inter-block and

sequential intra-block semantics
module mux4( input a, b, c, d
input [1:0] sel,
output out );

reg out, t0, t1;

always @( a or b or c or d or sel )
begin
t0 = ~( (sel[1] & c) | (~sel[1] & a) ); ORDER MATTERS in procedural blocks
t1 = ~( (sel[1] & d) | (~sel[1] & b) ); Executed sequentially from top to bottom
out = ~( (t0 | sel[0]) & (t1 | ~sel[0]) ); 對 blocking assignment 順序很重要
VLSI Signal Processing Lab.

end
The always block run once
endmodule
whenever a signal in its
sensitivity list changes

6.375 Complex Digital Systems N C T U . E E , Hsinchu, Taiwan

 Platform Based Design Group

Sensitivity List in always

module mux4( input a, b, c, d
input [1:0] sel,
output out );

reg out, t0, t1;

always @( a or b or c or d or sel )
begin
t0 = ~( (sel[1] & c) | (~sel[1] & a) );
t1 = ~( (sel[1] & d) | (~sel[1] & b) );
out = ~( (t0 | sel[0]) & (t1 | ~sel[0]) );
VLSI Signal Processing Lab.

end
What happens if we accidentally
endmodule
forget a signal on the sensitivity list?
Simulation will miss, but synthesis will ignore the sensitivity list
=> Simulation synthesis mismatch
6.375 Complex Digital Systems N C T U . E E , Hsinchu, Taiwan
 Platform Based Design Group

Auto sensitivity list in always

module mux4( input a, b, c, d
input [1:0] sel, Feel confusing?
output out ); Use always_comb
reg out, t0, t1; always_comb
begin
always @( * ) t0 = ~( (sel[1] & c) | (~
begin t1 = ~( (sel[1] & d) | (~
t0 = ~( (sel[1] & c) | (~sel[1] & a) ); out = ~( (t0 | sel[0]) & (
t1 = ~( (sel[1] & d) | (~sel[1] & b) ); end
out = ~( (t0 | sel[0]) & (t1 | ~sel[0]) );
VLSI Signal Processing Lab.

end
Verilog-2001 provides special syntax to
endmodule
automatically create a sensitivity list for
all signals read in the always block

6.375 Complex Digital Systems N C T U . E E , Hsinchu, Taiwan

 Platform Based Design Group

Always block – Event control @

• Always blocks model an activity that is repeated
continuously
• @ can control the execution
– posedge or negedge make sensitive to edge
– @* / @(*), are sensitive to any signal that may be read in the
statement group
– Use “,”/or for multiple signals
VLSI Signal Processing Lab.

Logic specific always in SystemVerilog

always_comb
always_ff
always_latch

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 Platform Based Design Group

Always block – Event control @

module M1 (input B, C, clk, rst, output reg X, Y,Z);
// controlled by any value change in B or C
always @ (B or C)
X = B & C;
Blocking assignment
// Controlled by
positive edge of
clk
always @(posedge clk)
Y <= B & C;
VLSI Signal Processing Lab.

// Controlled by
negative edge of clk or
rst NonBlocking assignment
always @(negedge clk,
negedge rst)
if (!rst) Z <= B & C;
else Z <= B & N C T U . E E , Hsinchu, Taiwan
 Platform Based Design Group

How to Specify a Sequential Circuit?

VLSI Signal Processing Lab.

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 Platform Based Design Group

Common patterns for

latch and flip-flop inference
always @( clk ) latch
begin • Verilog uses idioms to describe
next_X D Q X
if ( clk ) latches, flip-flops and FSMs
clk •
D <= Q; Other coding styles may simulate
end correctly but produce incorrect
DFF hardware
always @( posedge clk ) next_X D Q X
begin
D <= Q; clk
end
DFF with enable
VLSI Signal Processing Lab.

always @( posedge clk )

begin
next_X D Q X
if ( enable ) clk
D <= Q;
end enable

6.375 Complex Digital Systems N C T U . E E , Hsinchu, Taiwan

 Platform Based Design Group

Procedural blocks (summary)

• Blocks of code within a concurrent block which are read
(simulated, executed) in order
• Procedural blocks may contain:
– Blocking assignments
– Nonblocking assignments
– Procedural control statements (if, for, case)
– function, or task calls
VLSI Signal Processing Lab.

– Event control (‘@’)

– procedural blocks enclosed in begin … end

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 Platform Based Design Group

CONTROL STATEMENTS
VLSI Signal Processing Lab.

IF-ELSE, CASE, LOOP

(ONLY WITHIN PROCEDURAL BLOCKS)
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 Platform Based Design Group

Isn’t this just

logic A;
always @ (B or C) logic A;
begin assign A = ~(B & C);
A = ~(B & C);
end
VLSI Signal Processing Lab.

Why bother?

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 Platform Based Design Group

Always blocks can contain

more advanced control constructs
module mux4( input a, b, c, d module mux4( input a, b, c, d
input [1:0] sel, input [1:0] sel,
output out ); output out );
reg out; reg out; a
always @( * ) always @( * ) b
begin begin
if ( sel == 2’d0 ) case ( sel ) 4-to-1
out
out = a; 2’d0 : out = a; c d multiple
else if ( sel == 2’d1 ) 2’d1 : out = b; xer
out = b 2’d2 : out = c;
else if ( sel == 2’d2 ) 2’d3 : out = d;
out = c default : out = 1’bx;
else if ( sel == 2’d3 ) endcase
VLSI Signal Processing Lab.

out = d end
else endmodule sel[0] sel[1]
out = 1’bx;
end
endmodule

Nested if-else case

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 Platform Based Design Group

Conditional statements (if … else)

• The statement occurs if the expressions controlling the if statement
evaluates to true
– True: 1 or non-zero value
– False: 0 or ambiguous (X) always_comb
begin
• Explicit priority if (!WRITE)
begin
out = oldvalue;
end
if (<expression>)
else if (!
// statement1
VLSI Signal Processing Lab.

STATUS)
else if (<expression>)
begin
// statement2
q = newstatus;
else
// statement3 end Something wrong here
end

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Conditional statements (case)

• case, casex, casez: case statements are used for switching between
multiple selections
– If there are multiple matches only the first is evaluated
– Breaks automatically
• casez treats Z as don’t care
Help logic simplification
• casex treats Z and X as don’t care

case (<expression>)
<alternative 1> : <statement 1>;
VLSI Signal Processing Lab.

<alternative 2> : <statement 2>;

default : <default statement>;
endcase

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 Platform Based Design Group

Case, casez, casex

always @(s, a, b, c, d) always @*
case (s) casex (state)
2'b00: out = a; /*
2'b01: out = b; during comparison : 3'b01z,
2'b10: out = c; 3'b01x, 3b'011 ... match case
2'b11: out = d; 3'b01x
endcase */
3'b01x: fsm = 0 ;
always @* 3'b0xx: fsm = 1 ;
casez (state) default: fsm = 1 ;
VLSI Signal Processing Lab.

// 3'b11z, 3'b1zz,...match endcase

3'b1??
3'b1??: fsm = 0;
3'b01?: fsm = 1;
default: fsm = 1;
endcase
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 Platform Based Design Group

What happens if the

case statement is not complete?
VLSI Signal Processing Lab.

If sel = 3, mux will output

the previous value.
What have we created?

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 Platform Based Design Group

Incomplete Specification:
Added unwanted latch

Unintentional latch
VLSI Signal Processing Lab.

Similar for if-else

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 Platform Based Design Group

Always Avoid Incomplete Specification

1’bx (i.e. ‘x’) 視作 undefined

VLSI Signal Processing Lab.

TIPS: If you don’t care about the assignment in a case (for instance you know that it will never come up) then assign
the value “x” to the variable; E.g.: default: out = 1‘bx; The x is treated as a “don’t care” for synthesis and will simplify
the logic
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 Platform Based Design Group

Imcompleted case / if-else => unintentional

latch
module mux4( input a, b, c, d module mux4( input a, b, c, d
input [1:0] sel, input [1:0] sel,
output out ); output out );
reg out; reg out; a
always @( * ) always @( * ) b
begin begin
if ( sel == 2’d0 ) case ( sel ) 4-to-1
out
out = a; 2’d0 : out = a; c d multiple
else if ( sel == 2’d1 ) 2’d1 : out = b; xer
out = b; 2’d2 : out = c;
else if ( sel == 2’d2 ) 2’d3 : out = d;
out = c; //default : out = 1’bx;
else if ( sel == 2’d3 ) endcase
VLSI Signal Processing Lab.

out = d; end
//else endmodule sel[0] sel[1]
// out = 1’bx;
end
endmodule

Nested if-else case

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 Platform Based Design Group

A COMPLETED EXAMPLE
VLSI Signal Processing Lab.

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 Platform Based Design Group

Example 把 sequential logic 和 combinational logic 分開

Sequential logic => 各種的 DFF ，沒有 logic equation

module design(
// input
input [7:0] data_in, // combinational circuit
// system always_comb
input clk_p, beign
input rst_n, value_w = data_in + 7’d1;
// output end
output logic [7:0] data_out // sequential circuit
); always_ff@(posedge clk_p, negedge rst_n)
logic [7:0] value_w; begin
if(~rst_n)begin
data_out <= 7’d0;
VLSI Signal Processing Lab.

Module
Combinational Sequential end else begin
IN logic logic data_out <= value_w;
Reg.
Reg. end
OUT
Reg.
end
endmodule

86
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 Platform Based Design Group

Simple testbench
`timescale 1ns/1ps //time resolution
// dumpping waveform
`include “design.v” initial begin
`include “pattern.v” $fsdbDumpfile(“waveform.fsdb”);
$fsdbDumpvars; Save waveforms of all variables
module testbench; end
// inter connection wire endmodule
wire clk_p;
wire rst_n;
wire [7:0] data_in;
wire [7:0] data_out;
// connection, test pattern
testbench.v
pattern U_pattern(
.clk_p(clk_p),
.rst_n(rst_n), Test pattern generation
.data_in(data_in),
and response check pattern.v design.v
VLSI Signal Processing Lab.

.data_out(data_out));
//my design
design U_design(
.clk_p(clk_p),
.rst_n(rst_n),
.data_in(data_in), DUT
.data_out(data_out));

87
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 Platform Based Design Group

Simple testbench (SystemVerilog Version)

`timescale 1ns/1ps //time resolution Defines the time units and simulation precision (smallest increment)
`include “design.v” `timescale <reference_time_unit> / <time_precision>
`include “pattern.v”
• reference_time_unit: simulation time unit
module testbench;
// inter connection wire
• time_precision: unit for rounding 四捨五入的單位
wire clk_p; The precision unit must be less than or equal to the time unit
wire rst_n;
wire [7:0] data_in;
wire [7:0] data_out;
// connect test pattern
`ifdef RTL
pattern U_pattern(
.*); `timescale 1ns/100ps
//my test `endif
design U_design( //finer resolution for gate level
VLSI Signal Processing Lab.

.*));
// dumpping waveform
`ifdef GATE
initial begin `timescale 1ns/10ps
$fsdbDumpfile(“waveform.fsdb”); `endif
$fsdbDumpvars;
end
endmodule //global parameters for all modules
`define CLK_PERIOD 30.0
88
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 Platform Based Design Group

Simple test pattern

module pattern(
clk_p,
rst_n, initial begin
data_in, // reset
data_out rst_n = 1’b1;
); wait(clk_p!==1’bx);
// parameter setting @(negedge clk_p);
parameter cycle = 10; rst_n = 1’b0;
parameter Th = 2; @(negedge clk_p);
// I/O declaration rst_n = 1’b1;
output clk_p; // stimulus generation
output rst_n; @(posedge clk_p);
output [7:0] data_in; #(Th)
input [7:0] data_out; data_in = 8’d8; // 1st cycle
reg clk_p; @(posedge clk_p);
reg rst_n; #(Th)
VLSI Signal Processing Lab.

reg [7:0] data_in; data_in = 8’d2; // 2nd cycle

// clock ……
always begin $finish;
#(cycle/2.0) clk_p = 1’b1; end
Finish simulation
#(cycle/2.0) clk_p = 1’b0; endmodule
end

89
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 Platform Based Design Group

FOR LOOP IN VERILOG DESIGN

VLSI Signal Processing Lab.

(ONLY WITHIN PROCEDURAL BLOCKS)

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 Platform Based Design Group

loop
• The for loops are supported, with two constraints:
– The loop index range must be globally static, and the loop body must not contain
a wait statement.
– Latches are also synthesized whenever a for loop statement does not assign a
variable for all possible executions of the for loop and when a variable assigned
inside the for loop is not assigned a value before entering the enclosing for loop.
• The while loops are supported, but the loop body must contain at least
one wait statement.
VLSI Signal Processing Lab.

• Combinational while loops are supported if the iterative bound is statically determinable. The
loop statements with no iteration scheme (infinite loops) are supported, but the loop body
must contain at least one wait statement.
• Repeat is not supported in Synopsys Design Compiler

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 Platform Based Design Group

• Provide a shorter way to express a series of statements.

• Loop index variables must be integer type.
• Step, start & end value must be constant.
• In synthesis, for loops loops are “unrolled”, and then synthesized.
always@( a or b )begin
for( i=0; i<4; i=i+1 )c[i] = a[i] & b[i];
end
VLSI Signal Processing Lab.

always@( a or b ) begin
c[0] = a[0] & b[0];
c[1] = a[1] & b[1];
c[2] = a[2] & b[2];
c[3] = a[3] & b[3];
end
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 Platform Based Design Group

HDL Compiler allows four syntax forms for afor loop

A Simple for Loop

Nested for Loop

VLSI Signal Processing Lab.

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 Platform Based Design Group

FOR Loop in Hardware

• Equivalent to repeat multiple hardware units

int matrix[9]; always@(posedge clk)begin

for(idx=0;idx<9;idx++){ matrix[0] <= 0;
matrix[idx] = 0; matrix[1] <= 0;
}//C code matrix[2] <= 0;
matrix[3] <= 0;
reg[31:0]matrix[8:0]; matrix[4] <= 0;
always@(posedge clk)begin matrix[5] <= 0;
if(reset) matrix[6] <= 0;
VLSI Signal Processing Lab.

for(idx=0; idx <9; idx = idx +1)begin matrix[7] <= 0;

matrix[idx] <= 0; matrix[8] <= 0;
end end
end //Verilog code
Reset a matrix to zero

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 Platform Based Design Group

Add 1 to 10 with for loop

• A wrong example
– Iteration in a Verilog “for” loop is not what you think as in C
– Equivalent to expand the for loop

always@(posedge clk)begin
reg [7:0]temp;
temp <= temp+0;
always@(posedge clk)begin
temp <= temp+1;
for(idx=0;idx<10;idx=idx+1)begin
temp <= temp+2;
temp <= temp+idx;
VLSI Signal Processing Lab.

temp <= temp+3;

end
.
end
.
.
在 verilog 使用 for loop 時，他會把你的 for 做展開， temp <= temp+9;
end

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 Platform Based Design Group

Add 1 to 10 with for loop

reg[3:0]counter, temp;
• Use counter instead
assign counter_nxt = (counter == 10) ?
counter : counter + 1;
• Note. always@(posedge clk)begin
if(reset)
– When you use for loop counter <= 0;
else
– Try to expand it to see if it matches counter <= counter_nxt;
what you think or not end

assign temp_nxt = temp + counter;

VLSI Signal Processing Lab.

always@(posedge clk)begin
if(reset)
temp <= 0;
要用 for loop 請先展開看看合不合 else if(counter<10)
temp <= temp_nxt;
end

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 Platform Based Design Group

• Converting A Software-Style For

Loop to VHDL/Verilog
// Example Software Code:
For (int i=0; i<10; i++)
data[i] = data[i] + 1;

//equivalent code in Verilog:

always @(posedge clock)
begin
if (index < 10)
VLSI Signal Processing Lab.

begin
data[index] <= data[index] + 1;
index <= index + 1;
end
end

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 Platform Based Design Group
module for_loop_synthesis_tb (); //
module for_loop_synthesis (i_Clock); Testbench
input i_Clock; reg r_Clock = 1'b0;
integer ii=0; // Instantiate the Unit Under Test (UUT)
reg [3:0] r_Shift_With_For = 4'h1; for_loop_synthesis UUT
reg [3:0] r_Shift_Regular = 4'h1; (.i_Clock(r_Clock));
always
// Performs a shift left using a for loop #10 r_Clock = !r_Clock;
always @(posedge i_Clock) endmodule
begin
for(ii=0; ii<3; ii=ii+1)
r_Shift_With_For[ii+1] <= r_Shift_With_For[ii];
end

// Performs a shift left using regular statements

always @(posedge i_Clock)
begin
VLSI Signal Processing Lab.

r_Shift_Regular[1] <= r_Shift_Regular[0];

r_Shift_Regular[2] <= r_Shift_Regular[1];
r_Shift_Regular[3] <= r_Shift_Regular[2];
end
endmodule

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 Platform Based Design Group

Bit Reversal
• Given a 100-bit input vector [99:0], reverse its bit ordering
VLSI Signal Processing Lab.

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 Platform Based Design Group

population count
• A "population count" circuit counts the number of '1's in an input vector.
Build a population count circuit for a 255-bit input vector
VLSI Signal Processing Lab.

Not synthesizable, combinational feedback loop

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 Platform Based Design Group

Improper Loop Use (1/2)

input [‘N-1:0] a; input [‘N-1:0] a;
output [‘N-1:0] b; output [‘N-1:0] b;
integer i;
reg [‘N-1:0] b; assign b = ~a;

always @ (a) begin

for (i=0; i<=‘N-1; i=i+1)
b[i] = ~a[i];
end
VLSI Signal Processing Lab.

BAD Good
bit visit bus visit
loop overhead parallel evaluation

copyright © 2004 101

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 Platform Based Design Group

Improper Loop Use (2/2)

Bus Reversal

input [15:0] a; input [15:0] a;

output [15:0] b; output [15:0] b;
integer i;
reg [15:0] b; assign b = { a[0], a[1],
a[2], a[3], a[4], a[5],
always @ (a) begin a[6], a[7], a[8], a[9],
for (i=0; i<=15; i=i+1) a[10], a[11], a[12],
b[15 - i] = a[i]; a[13], a[14], a[15] };
end
VLSI Signal Processing Lab.

BAD Good
loop overhead concatenation

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For Loop
• It simulates slow
– from 10X to > 1000X slower than non-for loop versions
• It synthesizes slow
• Memory clear
– legitimate for loop use in chip design

• Avoid using the for loop whenever possible

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PARAMETERIZED DESIGN
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Generate Example (1/2)

generate
genvar i;

for(i = 0; i <= 7; i = i + 1)
begin: u
adder8 add(sum[(i*8)+:8], co[i+1],
a[(i*8)+:8], b[(i*8)+:8], ci[i]);
end
endgenerate

u[0].add, u[1].add, …, u[7].add are generated

VLSI Signal Processing Lab.

Verilog-2001

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Generate Example (2/2)

module multiplier (a, b, product);
parameter a_width = 8, b_width = 8;
localparam product_width = a_width + b_width;
input [a_width-1:0] a;
input [b_width-1:0] b;
output [product_width-1:0] product;

generate
if ((a_width < 8) || (b_width < 8))
CLA_multiplier #(a_width, b_width) u1 (a, b, product);
else
WALLACE_multiplier #(a_width, b_width) u1 (a, b, product);
endgenerate
VLSI Signal Processing Lab.

endmodule

Verilog-2001
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Ripple Adder Generator

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Generate Loop
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Generate
• Use for loops to generate any number of instances of:
– modules, primitives, procedures, continuous assignments, tasks, functions,
variables, nets
• Use if–else and case decisions to control what instances are
generated
– provides greater control than the VHDL generate
• New reserved words added:
– generate, endgenerate, genvar
VLSI Signal Processing Lab.

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Exercise
• https://hdlbits.01xz.net/wiki/Vector100r
VLSI Signal Processing Lab.

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