Assembly Language Programming

Intel x86 Architecture

Week 2

Dr. Victor Mageto

Intended Learning Outcomes

1. History of Intel microprocessors.

2. Instruction Set Architecture and Design.
3. Registers in x86 family
4. Memory and Addressing Modes

2
Intel microprocessor history
Intel Corporation
• Stylized as intel, is an American multinational corporation and
technology company established in 1968.
• HQ Santa Clara, California.
• Largest semiconductor chip manufacturer by revenue
• Developer of the x86 series of microprocessors found in most PCs.
• Supplies microprocessors for computer system manufacturers such
as Acer, Lenovo, HP, and Dell.
• Intel products includes
• Motherboard chipsets
• Network interface controllers
• Integrated circuits
• Flash memory graphics chips
• Embedded processors
• Devices related to communications and computing.

4
Early Intel microprocessors
• Intel 8080 (1972)
– 64K addressable RAM
– 8-bit registers
– CP/M operating system (Control Program for Microcontrollers)
– 5,6,8,10 MHz
– 29K transistors
• Intel 8086/8088 (1978)
– IBM-PC used 8088 Transistor
– 1 MB addressable RAM
– 16-bit registers
– 16-bit data bus (8-bit for 8088)
– separate floating-point unit (8087)
– used in low-cost microcontrollers now
5
The IBM-AT (International Business machines Advanced Technology)

• Intel 80286 (1982)

– 16 MB addressable RAM
– Protected memory
– several times faster than 8086
– introduced IDE bus architecture
– 80287 floating point unit
– Up to 20MHz
– 134K transistors

6
Intel IA-32 Family
• Intel386 (1985)
– 4 GB addressable RAM
– 32-bit registers
– paging (virtual memory)
– Up to 33MHz
• Intel486 (1989)
– instruction pipelining
– Integrated FPU
– 8K cache
• Pentium (1993)
– Superscalar (two parallel pipelines)

7
Intel P6 Family
• Pentium Pro (1995)
– advanced optimization techniques in microcode
– More pipeline stages
– On-board L2 cache
• Pentium II (1997)
– MMX (multimedia) instruction set
– Up to 450MHz
• Pentium III (1999)
– SIMD (streaming extensions) instructions (SSE)
– Up to 1+GHz
• Pentium 4 (2000)
– NetBurst micro-architecture, tuned for multimedia
– 3.8+GHz
• Pentium D (2005, Dual core)
8
IA32 Processors
• Totally Dominate Computer Market
• Evolutionary Design
– Starting in 1978 with 8086
– Added more features as time goes on
– Still support old features, although obsolete
• Complex Instruction Set Computer (CISC)
– Many different instructions with many different
formats
• But, only small subset encountered with Linux programs
– Hard to match performance of Reduced Instruction
Set Computers (RISC)
– But, Intel has done just that!
IA-32 Instruction Set Architecture
& Design
IA-32 architecture
• Lots of architecture improvements, pipelining,
superscalar, branch prediction, hyperthreading
and multi-core.
• From programmer’s point of view, IA-32 has not
changed substantially except the introduction
of a set of high-performance instructions

11
Modes of operation
• Protected mode
• It allows system software to use features such as virtual memory, paging
and safe multi-tasking designed to increase an operating system's control
over application software.
• Native mode (Windows, Linux), full features, separate memory

• Virtual-8086 mode
• hybrid of Protected
• each program has its own 8086 computer

• Real-address mode
– native MS-DOS
• System management mode
– power management, system security, diagnostics

12
Addressable memory
• Protected mode
– 4 GB
– 32-bit address
• Real-address and Virtual-8086 modes
– 1 MB space
– 20-bit address

13
General-purpose registers
32-bit General-Purpose Registers

EAX EBP
EBX ESP
ECX ESI
EDX EDI

16-bit Segment Registers

EFLAGS CS ES
SS FS
EIP
DS GS

14
Accessing parts of registers
• Use 8-bit name, 16-bit name, or 32-bit name
• Applies to EAX, EBX, ECX, and EDX
8 8

AH AL 8 bits + 8 bits

AX 16 bits

EAX 32 bits

15
Index and base registers
• Some registers have only a 16-bit name for
their lower half (no 8-bit aliases). The 16-bit
registers are usually used only in real-address
mode.

16
Some specialized register uses (1 of 2)

• General-Purpose
– EAX – accumulator (automatically used by division
and multiplication)
– ECX – loop counter
– ESP – stack pointer (should never be used for
arithmetic or data transfer)
– ESI, EDI – index registers (used for high-speed
memory transfer instructions)
– EBP – extended frame pointer (stack)

17
Some specialized register uses (2 of 2)

• Segment
– CS – code segment
– DS – data segment
– SS – stack segment
– ES, FS, GS - additional segments
• EIP – instruction pointer
• EFLAGS
– status and control flags
– each flag is a single binary bit (set or clear)
• Some other system registers such as IDTR,
GDTR, LDTR etc.
18
Status flags
• Carry
– unsigned arithmetic out of range
• Overflow
– signed arithmetic out of range
• Sign
– result is negative
• Zero
– result is zero
• Auxiliary Carry
– carry from bit 3 to bit 4
• Parity
– sum of 1 bits is an even number

19
Floating-point, MMX, XMM registers
• Eight 80-bit floating-point data 80-bit Data Registers
48-bit Pointer Registers
ST(0)
registers ST(1)
FPU Instruction Pointer

– ST(0), ST(1), . . . , ST(7) ST(2) FPU Data Pointer

ST(3)
– arranged in a stack ST(4) 16-bit Control Registers
ST(5) Tag Register
– used for all floating-point ST(6) Control Register
arithmetic ST(7) Status Register

• Eight 64-bit MMX registers Opcode Register

• Eight 128-bit XMM registers for
single-instruction multiple-data
(SIMD) operations SIMD, MIMD

20
Programmer’s model

21
Programmer’s model

MMX: Play multimedia applications

XMM: perform calculations on data

MXCSR: Multimedia Extensions Control and Status Register 22

IA-32 Memory Management &
Addressing Mode
Real-address mode
• 1 MB RAM maximum addressable (20-bit address)
• Application programs can access any area of
memory
• Single tasking
• Supported by MS-DOS operating system

24
Segmented memory
Segmented memory addressing absolute (linear) address is
a combination of a 16-bit segment value added to a 16-bit
offset
F0000
E0000 8000:FFFF
D0000
C0000
linear addresses

B0000
A0000
90000
one segment
80000
(64K)
70000
60000
8000:0250
50000
0250
40000
30000 8000:0000
20000
10000
seg ofs
00000
25
Calculating linear addresses
• Given a segment address, multiply it by 16 (add
a hexadecimal zero), and add it to the offset
• Example: convert 08F1:0100 to a linear address

Adjusted Segment value: 0 8 F 1 0

Add the offset: 0 1 0 0
Linear address: 0 9 0 1 0

• A typical program has three segments: code,

data and stack. Segment registers CS, DS and SS
are used to store them separately.
26
Example

What linear address corresponds to the segment/offset

address 028F:0030?

028F0 + 0030 = 02920

Always use hexadecimal notation for addresses.

27
Protected mode (1 of 2)
• 4 GB addressable RAM (32-bit address)
– (00000000 to FFFFFFFFh)
• Each program assigned a memory partition
which is protected from other programs
• Designed for multitasking
• Supported by Linux & MS-Windows

28
Protected mode (2 of 2)
• Segment descriptor tables
• Program structure
– code, data, and stack areas
– CS, DS, SS segment descriptors
– global descriptor table (GDT)
• MASM Programs use the Microsoft flat memory
model

29
Flat segmentation model
• All segments are mapped to the entire 32-bit physical
address space, at least two, one for data and one for
code
• global descriptor table (GDT)

30
Multi-segment model
• Each program has a local descriptor table (LDT)
– holds descriptor for each segment used by the program
RAM

Local Descriptor Table

26000
base limit access
00026000 0010
00008000 000A
00003000 0002 8000
multiplied by
1000h 3000
31
Translating Addresses
• The IA-32 processor uses a one- or two-step
process to convert a variable's logical address
into a unique memory location.
• The first step combines a segment value with a
variable’s offset to create a linear address.
• The second optional step, called page
translation, converts a linear address to a
physical address.
Converting Logical to Linear Address
The segment Logical address

Selector Offset
selector points to a
segment descriptor, Descriptor table

which contains the

base address of a
memory segment.
Segment Descriptor +
The 32-bit offset
from the logical
address is added to
the segment’s base
address, generating GDTR/LDTR

Linear address
a 32-bit linear (contains base address of
address. descriptor table)
Indexing into a Descriptor Table
Each segment descriptor indexes into the program's local
descriptor table (LDT). Each table entry is mapped to a
linear address:
Linear address space

(unused)

Logical addresses
Local Descriptor Table DRAM
SS ESP
0018 0000003A

DS offset (index)
0010 000001B6 18 001A0000
10 0002A000

08 0001A000
IP 00003000
00
0008 00002CD3

LDTR register
Paging (1 of 2)
• Virtual memory uses disk as part of the
memory, thus allowing sum of all programs can
be larger than physical memory
• Only part of a program must be kept in
memory, while the remaining parts are kept on
disk.
• The memory used by the program is divided
into small units called pages (4096-byte).
• As the program runs, the processor selectively
unloads inactive pages from memory and loads
other pages that are immediately required.
Paging (2 of 2)
• OS maintains page directory and page tables
• Page translation: CPU converts the linear
address into a physical address
• Page fault: occurs when a needed page is not
in memory, and the CPU interrupts the
program
• Virtual memory manager (VMM) – OS utility
that manages the loading and unloading of
pages
• OS copies the page into memory, program
resumes execution
Page Translation
Linear Address
A linear address is 10 10 12

divided into a page Directory Table Offset

directory field, page Page Frame

table field, and page

Page Directory Page Table
frame offset. The
Physical Address
CPU uses all three to
calculate the Page-Table Entry

physical address. Directory Entry

CR3
32