Design and Implementation of Reversible logic Circuit in

Sub-threshold Regime for Ultra Low Power Application

A PROJECT
Submitted in Fulfillment for the degree of Master of Technology in
  MICROELECTRONICS AND VLSI TECHNOLOGY
  OF
Maulana Abul Kalam Azad University of Technology, West Bengal (MAKAUT,WB)
Submitted by
SUBARNA MONDAL
(Roll no: - 30014618002)

Under the guidance of

Dr. DEBASHIS DE
 
DEPARTMENT OF MICROELECTRONICS AND VLSI TECHNOLOGY
 WHY LOW POWER???
Low power system are smaller and cheaper to manufacture.

Power consumption is vital issue.

In nanometre technology power has become the

most important issue because of
1. Increasing transistor count
2. high speed of operation
3. greater leakage current
Low power circuit to be used to reduce cost of
packing and cooling.

Moreover, reliability is also related with the power dissipation of the ICs. High
power systems often run hot, and high temperature tends to exacerbate several silicon
failure mechanisms. If the temperature increases by 10 degree centigrade then the
reliability of the ICs will reduce by 50%.
 INTRODUCTION
Designing low-power circuits has been a most demanding area in VLSI technology. And power
dissipation has been considered as one of the significant issue in the VLSI design .

Landuer stated that in the irreversible logic

computation, each bit information lost generates
KTln2 joule of energy.

Even C.H. Bennett in 1973 also showed that KTln2

energy dissipation would not occur if computation
were carried out in reversible manner and also stated
that dissipated energy directly correlated to the
number of lost bits

The reversible circuit are those circuits that do not lose information and the reversible computation
can be performed only when the system consist of reversible gates.
 INTRODUCTION
Reversible computation does not require erasing any bit of information.
Consequently, it does not dissipate any energy for computation.

In the reversible logic , reversible

gates allow inputs to be uniquely
identified from the observed output.

Reversible logic is likely to be in

demand in high speed power
awareness circuit , low power CMOS
design, optical computing ,
nanotechnology and quantum
computing.
 OBJECTIVE

 To reduce the power consumption without sacrificing the

performance of reversible logic in transistor level with 22nm
CMOS technology(junction-less transistor) using T-spice
simulator.
 MOTIVATION

The primary motivation for adopting the reversible logic lies in fact that it can
provide a logic methodology for designing ultra low power circuit beyond KTln2
limit for emerging technology in which the energy dissipation due to information
destruction will be a significant factor of overall heat dissipation .

And further adopting the junction less transistor for implementing the reversible
logic as Junction less transistor (JLT) have emerged as one of the most promising
candidate to extend the CMOS technology beyond the scaling limit of conventional
CMOS technology due to their better short-channel effects (SCEs) and compatible
process flow with the existing CMOS technologies.
What is Junction-less transistor??
 Junction-less transistor continued...

(a) (b)

Schematic view of Junctionless devices (JLT) (a) N - Type

and(b) P- Type
Junction-less transistor continued...

(a) (b)

Schematic view of N–Type JLT (a) OFF-state along with the conduction band
diagram and (b) ON-state
Difference between JT and JLT
JUNCTION TRANSISTOR JUNCTIONLESS TRANSISTOR

1. High electric field. 1. Less electric field(no decrease in mobility).

2.Major carrier make itself barrier to carrier 2.No barrier, so high current drive.
scattering.

3.Complex and expensive fabrication. 3. No annealing , implantation, easy fabrication.

4.Short channel effects. 4. No short channel effect.

 Sources of power dissipation
Classification of power dissipation:
 Dynamic power
Switching power.
Short circuit power

Static power
Diode leakage current
Sub threshold leakage current
Gate oxide leakage current
 Reversible Logic
The logical reversibility means there should be same number of
output lines as the number of input lines i.e. The number of input
lines and output line must be same or there should be one to one
mapping between the input and output.

The gate must be run forward and backward i.e. the input can
also be recovered or retrieved from the output.

When the device obeys these two conditions then the second
law of thermodynamics guarantees that it dissipates no heat.

For logical reversibility in the digital logics there are two

conditions as follows.
1. Fan-Out is not permitted
2. Feedback is not permitted
 Feynman Gate
Feynman gate is a 2*2 one-through reversible
Fig 2 shows The proposed transistor
gate shown in Fig. 1. One through gate means that
implementation is completely reversible, that is, the
one input variable is also the output.
proposed circuit can also work for reverse operation.

Figure 1. Feynman gate

we can calculate the forward calculation

P=A;
Fig:2. Reversible Transistor Implementation of the Feynman
If A=0 then Q=B Else Q=B’
 as well as the reverse calculation
A=P;
If P=0 then B=Q Else B=Q’
Simulated Result
 Feynman Gate Continued....
Truth Table

A_P B P Q
(INPUT) (INPUT) (OUTPUT) (OUTPUT)(A XOR B)

0 0 0 0

0 1 0 1

1 0 1 1

1 1 1 0
 Fredkin Gate
Fredkin gate is a (3*3) conservative reversible
Fig 4 shows the proposed transistor
gate as shown in Fig.3. It is called 3*3 gate as it
implementation of the Fredkin Gate which
has three inputs and three out- puts.
requires only 4 transistors. In the proposed
implementation, the output P is directly taken
from input A as it is simply hardwired

Fig 3: fredkin gate

 Forward calculation
P=A
If A=0 then Q=B and R=C,
Else Q=C and R=B
Fig 4: transistor implementation of fredkin gate
 Backward calculation
A=P
If P=0 then B=Q and C=R
Else C=Q and B=R
 
Simulated Result
 Fredkin Gate Continued....
A_P B C Q R
(INPUT) (INPUT) (INPUT) (OUTPUT) (OUTPUT)
(Q=A’B+AC) (R=AB+A’C)
0 0 0 0 0

0 0 1 1 0

0 1 0 0 1

0 1 1 1 1

1 0 0 0 0

1 0 1 1 0

1 1 0 0 1

1 1 1 1 1
 Toffoli Gate
Tofolli Gate (TG) is a 3*3 two-through Figure 6 shows the proposed transistor
reversible gate as shown in Fig. 5 implementation of Toffoli Gate. In the proposed
implementation, the outputs P and Q are
directly generated from inputs A and B
respectively by hardwiring.
 

fig 5: toffoli gate

 
 Forward calculation
P=A ; Q=B;
If A AND B =0 then R=C Else R=C’

 Fig 6: transistor implementation of toffoli gate

Backward calculation
A=P ; B=Q;
If P AND Q =0 then C=R Else C=R’
 
Simulated Result
 Toffoli Gate Continued....
A_P B C P Q R
(INPUT) (INPUT) (INPUT) OUTPUT (OUTPUT) (OUTPUT)
(SAME AS ‘A’) (SAME AS ‘B’) R=A.B+C

0 0 0 0 0 0

0 0 1 0 0 1

0 1 0 0 1 0

0 1 1 0 1 1

1 0 0 1 0 0

1 0 1 1 0 1

1 1 0 1 1 0

1 1 1 1 1 1
 Reversible Sequential Circuit
 The sequential logic differs from combinational logic in
that the output of the logic device is dependent not only on the
present inputs to the device, but also on the past inputs.

The reversible circuit can be constructed by replacing flip-flop and gates

of traditional design by their reversible counter part.

The transistor implementation of four latches are shown i.e.

1. D-latch
2. T-latch
3. RS Latch
4. JK Latch

 The number of garbage outputs (GO):

This refers to the number of unused outputs present in a reversible
circuit. One cannot avoid the garbage outputs as these are very essential
to achieve reversibility.
 Reversible D- Latch
The characteristic equation of the D latch can be written as Q+=D.E+E’Q. The characteristic
equation of the D latch can be mapped onto the Fredkin gate (F).

fig 7(a) conventional D latch fig 7(b): proposed logic to implement d latch

Number of gate Garbage output

2 2
Simulated Result
 Reversible D- Latch continued..
C D R(Q) Q1(Q’)
(CLOCK) (INPUT) (OUTPUT) (OUTPUT)
(INPUT)
1 0 0 1

1 0 0 1

1 1 1 0

1 1 1 0
 Reversible T- Latch
The characteristic equation of the T latch can be written as Q +=(T Q).E+E’Q. But the
same result can also be obtained from Q+= (T.E) Q. This equation can be directly
mapped to Toffoli gate. The fan-out can be avoided and complementary output can be
generated by using Toffoli gate with Fredkin Gate.

figure 8(a): conventional T latch Figure 8(b). Proposed T- Latch

Number of gate Garbage output

2 2
Simulated Result
 Reversible T- Latch continued…
C T Q1(Q) R(Q’)
(CLOCK) (INPUT) (OUTPUT) (OUTPUT)
(INPUT)
1 0 1 0

1 0 1 0

1 1 0 1

1 1 0 1
 Reversible JK- Latch
 The characteristic equation of the JK latch can be written as Q+=(JQ’+K’Q).E+E’Q. The equation
JQ’+K’Q can be mapped to Q+=D.E+E’Q which can be easily mapped onto the Fredkin Gate.

Fig 9(a) conventional JK Latch

Fig 9(b): proposed transistor implementation of JK latch

Number of gate Garbage output

4 3
Simulated Result
 Reversible JK- Latch continued…
C J K R2(Q) R1(Q’)
(CLOCK) (INPUT) (INPUT) (OUTPUT) (OUTPUT)
(INPUT)

1 1 0 1 0

1 0 0 1 0

1 0 1 0 1

1 1 0 1 0

1 1 1 1 1

1 0 1 0 1

1 1 0 1 0

1 1 1 1 1
 Reversible RS- Latch
In two designs of RS latch were proposed one using the NOR logic (Fig. 10.b) and the other by using NAND
logic (Fig. 10.c). The reversible RS latch in is designed by using the Toffoli gate and by passing the
complementary values of the inputs.

fig 10(a): conventional RS latch fig 10 (b): reversible RS latch design NOR based fig 10(c): reversible RS latch design NAND based

Number of gates Garbage output

2 2
Simulated Result
 Reversible RS- Latch continued…
C R S R1(Q) R2(Q’)
(CLOCK) (INPUT) (INPUT) (OUTPUT) (OUTPUT)
(INPUT)

1 0 1 0 1

1 1 1 0 1

1 1 0 1 1

1 1 1 1 0

1 0 0 1 0

1 0 1 0 1

1 1 1 0 1

1 1 0 1 0
 Conclusion and Future scope
Reversible logic has shown a good promise for low power design. A good number of
design method for transistor implementation reversible sequential circuit and basic
reversible gate have been shown. However only limited work have been reported on
reversible sequential logic and the logics are feasible to implement in silicon technology.
further advancement of the proposed work is to use the latch towards the design of
complex sequential circuit lik flip flop, counter, storage register etc.
THANK YOU