Multiplexer And
Demultiplexer
Multiplexer
Multiplexer is a combinational circuit that has maximum of 2n data inputs, ‘n’
selection lines and single output line. One of these data inputs will be
connected to the output based on the values of selection lines.
Since there are ‘n’ selection lines, there will be 2n possible combinations of
zeros and ones. So, each combination will select only one data input.
Multiplexer is also called as Mux.
4x1 Multiplexer
4x1 Multiplexer has four data inputs I3, I2, I1 & I0, two selection lines s1 &
s0 and one output Y. The block diagram of 4x1 Multiplexer is shown in the
following figure.
Block Diagram
Truth Table
One of these 4 inputs will be connected to the output
based on the combination of inputs present at these two
selection lines. Truth table of 4x1 Multiplexer is shown
below.
Selection Lines Output
S1 S0 Y
0 0 I0
0 1 I1
1 0 I2
1 1 I3
From Truth table, we can directly write the Boolean function for output, Y as
Y=S1′S0′I0 + S1′S0I1 +S1S0′I2+S1S0I3
Implementation of Higher-order Multiplexers.
Now, let us implement the following two higher-order Multiplexers using
lower-order Multiplexers.
8x1 Multiplexer
16x1 Multiplexer
8x1 Multiplexer
In this section, let us implement 8x1 Multiplexer using 4x1 Multiplexers and
2x1 Multiplexer. We know that 4x1 Multiplexer has 4 data inputs, 2 selection
lines and one output. Whereas, 8x1 Multiplexer has 8 data inputs, 3 selection
lines and one output.
So, we require two 4x1 Multiplexers in first stage in order to get the 8 data
inputs. Since, each 4x1 Multiplexer produces one output, we require a 2x1
Multiplexer in second stage by considering the outputs of first stage as inputs
and to produce the final output.
Let the 8x1 Multiplexer has eight data inputs I7 to I0, three selection lines s2,
s1 & s0 and one output Y. The Truth table of 8x1 Multiplexer is shown below.
Truth Table
Selection Inputs Output
S2 S1 S0 Y
0 0 0 I0
0 0 1 I1
0 1 0 I2
0 1 1 I3
1 0 0 I4
1 0 1 I5
1 1 0 I6
1 1 1 I7
8X1 Multiplexer Logic Diagram
Demultiplexer
De-Multiplexer is a combinational circuit that performs the reverse operation
of Multiplexer. It has single input, ‘n’ selection lines and maximum of
2n outputs. The input will be connected to one of these outputs based on the
values of selection lines.
Since there are ‘n’ selection lines, there will be 2n possible combinations of
zeros and ones. So, each combination can select only one output. De-
Multiplexer is also called as De-Mux.
1x4 De-Multiplexer
1x4 De-Multiplexer has one input I, two selection lines, s1 & s0 and four
outputs Y3, Y2, Y1 &Y0. The block diagram of 1x4 De-Multiplexer is shown in
the following figure.
Block Diagram
The single input ‘I’ will be connected to one of the four
outputs, Y3 to Y0 based on the values of selection lines s1 &
s0. The Truth table of 1x4 De-Multiplexer is shown below.
Selection Inputs Outputs
S1 S0 Y3 Y2 Y1 Y0
0 0 0 0 0 I
0 1 0 0 I 0
1 0 0 I 0 0
1 1 I 0 0 0
Boolian Expression
Y3=s1s0 I
Y2=s1s0′I
Y1=s1′S0i
Y0=s1′s0′I
Logic Diagram
Implementation of Higher-order De-
Multiplexers
Now, let us implement the following two higher-
order De-Multiplexers using lower-order De-
Multiplexers.
1x8 De-Multiplexer
1x16 De-Multiplexer
1x8 De-Multiplexer
In this section, let us implement 1x8 De-Multiplexer using 1x4 De-Multiplexers
and 1x2 De-Multiplexer. We know that 1x4 De-Multiplexer has single input,
two selection lines and four outputs. Whereas, 1x8 De-Multiplexer has single
input, three selection lines and eight outputs.
So, we require two 1x4 De-Multiplexers in second stage in order to get the
final eight outputs. Since, the number of inputs in second stage is two, we
require 1x2 DeMultiplexer in first stage so that the outputs of first stage will
be the inputs of second stage. Input of this 1x2 De-Multiplexer will be the
overall input of 1x8 De-Multiplexer.
Let the 1x8 De-Multiplexer has one input I, three selection lines s 2, s1 & s0 and
outputs Y7 to Y0. The Truth table of 1x8 De-Multiplexer is shown below.
Truth Table
Selection Inputs Outputs
s2 s1 s0 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0
0 0 0 0 0 0 0 0 0 0 I
0 0 1 0 0 0 0 0 0 I 0
0 1 0 0 0 0 0 0 I 0 0
0 1 1 0 0 0 0 I 0 0 0
1 0 0 0 0 0 I 0 0 0 0
1 0 1 0 0 I 0 0 0 0 0
1 1 0 0 I 0 0 0 0 0 0
1 1 1 I 0 0 0 0 0 0 0
Logic Diagram
Lab Assignment -3
Implement 4x1 and 8x1 MULTIPLEXERS using Logisim 2.7.1
Implement 1x4 and 1X8 DEMULTIPLEXERS using Logisim 2.7.1
