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RISC Vs CISC

The document discusses the tradeoffs between RISC (reduced instruction set computing) and CISC (complex instruction set computing) architectures. CISC architectures have more complex instructions which can improve performance but also increase design complexity. RISC architectures have simpler instructions which allow for lower complexity designs that can achieve higher clock speeds. However, RISC requires more advanced compilers. Hybrid architectures and instruction sets that incorporate some complex instructions may provide the best balance between the approaches.

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Shaveta Banda
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135 views10 pages

RISC Vs CISC

The document discusses the tradeoffs between RISC (reduced instruction set computing) and CISC (complex instruction set computing) architectures. CISC architectures have more complex instructions which can improve performance but also increase design complexity. RISC architectures have simpler instructions which allow for lower complexity designs that can achieve higher clock speeds. However, RISC requires more advanced compilers. Hybrid architectures and instruction sets that incorporate some complex instructions may provide the best balance between the approaches.

Uploaded by

Shaveta Banda
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPT, PDF, TXT or read online on Scribd
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RISC vs.

CISC
Towards CISC
Wired logic  microcode control
 Temptingly easy extensibility
Performance tuning
 HW implementation of some high-level functions
Marketing
 Add successful instructions of competitors
 “New feature” hype
 Compatibility: only extensions are possible
CISC Problems
Performance tuning unsuccessful
 Rarely used high-level instructions
 Sometimes slower than equivalent sequence
High complexity
 Pipelining bottlenecks  lower clock rates
 Interrupt handling can complicate even more
Marketing
 Prolonged design time and frequent microcode
errors hurt competitiveness
RISC Features
Low complexity
 Generally results in overall speedup
 Less error-prone implementation by hardwired
logic or simple microcodes
VLSI implementation advantages
 Less transistors
 Extra space: more registers, cache
Marketing
 Reduced design time, less errors, and more
options increase competitiveness
RISC Compiler Issues
The compilers themselves
 Computationally more complex
 More portable

The compiler writer


 Less instructions  probably easier job
 Simpler instructions  probably less bugs
 Can reuse optimization techniques
RISC vs. CISC misconceptions

Arguments favoring RISC: simple design,


short design time, speed, price…

Study of RISC should include


hardware/software tradeoffs, factors
influencing computer performance and
industry-side evaluation.
RISC vs. CISC misconceptions

Incorrect implication from the two


acronyms: RISC and CISC.
 They are not bifurcations between which
designers have to choose

Carelessly leaving out the ‘participation’


of Operating System
RISC vs. CISC misconceptions

Reduced design time?


 academic <-> industrial

Performance claims of RISC proponent


do not decouple design features like
MRSs.
 MRSs can have a remarkable effect on program
execution
Conclusion – RISC vs. CISC?
CISC
 Effectively realizes one particular High Level
Language Computer System in HW - recurring
HW development costs when change needed

RISC
 Allows effective realization of any High Level
Language Computer System in SW - recurring
SW development costs when change needed
Conclusion – Optimum?
Hybrid solutions
 RISC core & CISC interface
 Still has specific performance tuning

Optimal ISA
 Between RISC & CISC
 Few, carefully chosen, useful complex instructions
 Still has complexity handling problems

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