WICHIP:

Technical Aspects

1
Engineering ideas

Agenda

• Team Overview
• HW Based Design Flow and Tools
• Demonstration
• Design Examples

WICHIP Confidential 2
Engineering ideas

Services & Products

• Services • Products
– Fields of IP design – Consumer Electronics
• Wireless communications
• Digital Camera
• Multimedia
• Securities • Mobile Phone
• HW/SW Codesign for Embedded System • PDA
– ARM based • Set-top Box
– PPC based
• DVR
– Target device
• FPGA based
– Security Equipments
• Custom made DSP • PETD
• IP Camera
– IP verification
• RTL level verification • RFID Card Reader
• Static timing verification
• Board level verification
– Verification methodologies
• Random, deterministic and corner cases vectors verification
• Formal verification
– System design
• System architecture
• Board design
• PCB layout

WICHIP Confidential 3
Engineering ideas

Human Resource

• Technical staffs:
– 20 R&D engineers
• Ph.D. (3), M.Sc. (3), Eng. (14)
• PM (5)

WICHIP Confidential 4
Engineering ideas

Agenda

• Team Overview
• HW Based Design Flow and Tools
• HW Based Verification Methodologies
• Design Examples

WICHIP Confidential 5
Engineering ideas

Design Flow: Front-End

Procedure TOOL

Specification,
C/C++, SystemC
algorithm analysis,
architecture
analysis

RTL Modeling
Modelsim
d RTL Simulation
n
e
-t
n
o
r
F Xilinx ISE,
Synthesis Synplicity, or DC
compiler

Post Synthesis
Static Timing
Analysis and DRC
Modelsim

Post Synthesis
Simulation

WICHIP Confidential 6
Engineering ideas

Design Flow: Back-End

Procedure TOOL

Place and Route Astro, Synopsys

LVS and DRC Astro, Synopsys

d
n
e
-k Post Layout
c Static Timing Lint tools: Vera
a Analysis and DRC
B

Post P&R
simulation Modelsim

WICHIP Confidential 7
Engineering ideas

Design Flow: Back-End (Cont’d)

Procedure TOOL

Physical Library
Apollo, Cadence
Replace

DB Merge Opus, Cadence

d
n
e
-
k
c
a
B Pattern Generation Opus, Cadence

LVS and DRC Calibre, Cadence

Fab in

WICHIP Confidential 8
Engineering ideas

Agenda

• Team Overview
• HW Based Design Flow and Tools
• HW Based Verification Methodologies
• Design Examples

WICHIP Confidential 9
Engineering ideas

Verification Methodologies
Procedure – Verification methodologies
• Random vector
High Level
Verification • Deterministic vector
• Corner case vector
RTL Level
Verification
• Formal verification
STA Level – Language
Verification
• VHDL
HW Emulation • HDL Verilog
• System Verilog
Board Level
• Matlab-HDL Co-verification
Verification

WICHIP Confidential 10
Engineering ideas

Agenda

• Team Overview
• HW Based Design Flow and Tools
• HW Based Verification Methodologies
• Design Examples
– 802.11a PHY Transceiver

WICHIP Confidential 11
Engineering ideas

802.11a PHY Transceiver: Features

 Operating at frequency band of 5 GHz
 52 OFDM subcarriers
 Variety modulation methods (BPSK, QPSK, 16-QAM, 64-QAM)
 Advantages: Good performance for multipath environment (indoor)
High data transfer rates,
Less interference
 Applications: WLAN

WICHIP Confidential 12
Engineering ideas

Spec & Block Design

802.11a Transmitter

plcp_tx_data
pulse_shape_re

plcp_data_vld
conv pilot guardtim e data pulse
scram bler interleaver m apper ifft pulse_shape_im
encoder insertion insertion selection shaping
plcp sig_vld

pulse_shape_vld
plcp_tail_vld

clk

pream ble
rst_n tx_control
generator

BLOCK 1 BLOCK 2

Transmitter top block design

WICHIP Confidential 13
Engineering ideas

Timing Budget Analysis

 Block Delays
inte rrup t sign al

plc p_tx

72 4 c loc k SIGNAL start

s c ra mble r
1 c loc k

c onv_e nc ode r

24 3 c loc k

inte rle a ve r
5 1 c lo c k / 99 c loc k / 19 5 c lo c k 2 41 c loc k

ma ppe r
5 1 c lo c k

pilot_ins e rtion
c loc k
14 2 c loc k

ifft
49 c loc k

gua rdtime _ins e rtion

3 c loc k

data _s e le c tio n

pre a mble _s tart

Total delay: 726 clks (~16us)

WICHIP Confidential 14
Engineering ideas

RTL Level Simulation & Verification

 Transmitter Top Block

Input data from PLCP Transmission data over the air

WICHIP Confidential 15
Engineering ideas

Gate Level Synthesis

 Transmitter Top Block Synthesis

Mapping to part: xc2v6000bf957-6,

Global buffer usage summary: BUFGs + BUFGPs: 1 of 8 (12%)
Mapping Summary: Total LUTs: 8149 (12%)
Mapper successful!
Process took 279.406 seconds realtime, 279.406 seconds cputime

WICHIP Confidential 16
Engineering ideas

STA Verification

WICHIP Confidential 17
Engineering ideas

Spec & Block Design

802.11a Receiver

g uardtime
syn c fft p ilo t_extract rx_buffer equalizer d emapper dein terleaver viterb i descrambler
remove

plcp_rx

rx_contro l

BLOCK 1 BLOCK 2

Receiver top block design

WICHIP Confidential 18
Engineering ideas

Timing Budget Analysis

 Timing Analysis
s ync o ut vld

s ync

242 c lo c k SIGNAL s tart

g uard time
re mo ve r
142 c lo c k
fft

65 c lo c k
pilo t_e xtrac t
2 c lo c k

rx_buffe r
51 c lo c k

de mappe r
1 c lo c k

de inte rle ave r

110 c lo c k
vite rbi

1 c lo c k
de s c ram

48 c lo c k

plc p_rx

662 c lo c k

Total delay: 662 clks

WICHIP Confidential 19
Engineering ideas

RTL Level Simulation & Verification

 Receiver Top Block

WICHIP Confidential 20
BPSK QPSK 16QAM
Engineering ideas

Gate Level Synthesis

 Receiver Top Block Synthesis

Mapping to part: xc2v6000bf957-6

Global buffer usage summary: BUFGs + BUFGPs: 2 of 8 (25%)
Mapping Summary: Total LUTs: 13488 (19%)
Mapper successful!
Process took 664.656 seconds realtime, 664.656 seconds cputime

WICHIP Confidential 21
Engineering ideas

STA Verification

WICHIP Confidential 22
Engineering ideas

Agenda

• Team Overview
• HW Based Design Flow and Tools
• HW Based Verification Methodologies
• Design Examples
– H.264 Codec

WICHIP Confidential 23
Engineering ideas

H.264 Decoder - Block Diagram

Inter-
Prediction
NAL Deblocking Post
Parser _
Intra- Filter Processing
Prediction

Scale &
Entropy
Inverse
Decoder
Transform

WICHIP Confidential 24
Engineering ideas

H.264 Decoder - Platform Based Design

DB Filter
(RTL)
PPC405 DMA
Bus
Wrapper

PLB

Bus Bus Bus

Wrapper Wrapper Wrapper Bridge to
Peripheral
Parser Prediction Residual
Bus
(RTL) (RTL ) (RTL )

OPB

DVI,USB, System
RS232, LAN, ACE,
JTAG,... CF Cards

WICHIP Confidential 25
Engineering ideas

RTL Level Simulation and Verification

WICHIP Confidential 26
Engineering ideas

STA Simulation and Verification

WICHIP Confidential 27
Engineering ideas

System architecture for board level verification

test . 264

CF PPC DMA DDR SDRAM

OPB BUS Bus Bridge PLB BUS

H. 264 Decoder
VGA FRAME BRAM
BUFFER

PARSING PROCESS
(PARSER + ENTROPY DEBLOCKING -FILTER PREDICTION
MONITOR DECODER )

WICHIP Confidential 28
Engineering ideas

Verification Flow

Design Environment
Reference
Decoder
Reference
=
Encoder
H264
Decoder

WICHIP Confidential 29
Engineering ideas

Test Vectors

• Standard pattern
– QCIF Foreman 300 frames

• Other patterns:
– Akyio : slow movement
– Coast Guard : fast movement
– Others

WICHIP Confidential 30
Engineering ideas

H.264 Decoder - Implementation

Target Device - Xilinx Virtex 4 FX60

Profile Baseline, Main

Resolution Up to HDTV

Frames per second 30

Entropy Coding CAVLC, CABAC

Latency 3200

Maximum Frequency 1400 MHz

Size 19000 LUTs

WICHIP Confidential 31
Engineering ideas

H.264 Decoder Video Player

Red[ 7: 0]
WiFi DA C A nalog Red
Dat a B uf fer
I /F
Green [ 7:0]
CTRL B us DA C A nalog Green
B lue [ 7:0]
USB DA C A nalog B lue
Dat a B uf fer
I /F
HSYNC
CTRL B us VSYNC
Triple DAC - VGA
Interface VGA Connect or

Micro SD
Dat a B uf fer
I /F
CTRL B us
WICHIP H .264
CF
DECODER Y [ 7: 0] HDMI Interface
HDMI Connector
Dat a B uf fer Chip Set
I /F Cr[7: 0]

CTRL B us Cb[ 7: 0]

HDTV Encoder HDMI Connector ,

Com ponent Video Out put ,
Chip Set VGA
HSYNC ,VSYNC

WICHIP Confidential 32
Engineering ideas

H.264 Encoder - Block Diagram

NAL
Bitstr eam
NAL Packager

Motion
Estimation

Reorder +
Entropy Encode
Motion
Compensation

Selector T/Q

Intra prediction

Input External Deblocking

_ T-1/Q- 1
Video Memory Filter

WICHIP Confidential 33
Engineering ideas

H.264 Encoder - Platform Based Design

CAVLC/CABAC
(RTL )
PPC405 DMA
Bus
Wrapper

PLB

Bus Bus Bus

Wrapper Wrapper Wrapper Bridge to
Peripheral
Decoder ME TQ
Bus
(RTL) (RTL) (RTL)

OPB

DVI,USB,
System ACE,
RS232, LAN,
CF Cards
JTAG,...

WICHIP Confidential 34
Engineering ideas

H.264 Encoder - Implementation

Target Device - Xilinx Virtex 4 FX100

Profile Baseline, Main

Resolution Up to HDTV

Output Bitrate 14 Mbps

Entropy Coding CAVLC, CABAC

Latency 4859

Maximum Frequency 70 MHz

Size 49000 LUTs

WICHIP Confidential 35
Engineering ideas

H.264 Encoder System

CTRL B us
RJ-45
Connect or
Etherner
ENCODED DA TA B US
Y [ 7: 0] Chip Set
Cr[ 7: 0]
CMOS IMA GE SENSOR
Cb [7: 0]
PIX [ 9: 0]
WICHIP WICHIP H .264
PIX _CLK Image Processor HSYNC
VSYNC
ENCODER

PIX _CLK `

WiFi
ENCODED DA TA B US
Chip Set

WICHIP Confidential 36
Engineering ideas

THANK YOU

WICHIP Confidential 37