WICHIP:

Technical Aspects
Dr. Vu-Duc Ngo

1
Engineering ideas

Agenda

• HW Based Design Flow and Tools

• HW Based Verification Methodologies
• Design Examples

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Engineering ideas

Design Flow: Front-End

Procedure TOOL

Specification,
C/C++, SystemC
algorithm analysis,
architecture
analysis

RTL Modeling
Modelsim
RTL Simulation
Front-end

Xilinx ISE,
Synthesis Synplicity, or DC
compiler

Post Synthesis
Static Timing
Analysis and DRC
Modelsim

Post Synthesis
Simulation

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Engineering ideas

Design Flow: Back-End

Procedure TOOL

Place and Route Astro, Synopsys

LVS and DRC Astro, Synopsys

Post Layout
Back-end

Static Timing Lint tools: Vera

Analysis and DRC

Post P&R
Modelsim
simulation

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Engineering ideas

Design Flow: Back-End (Cont’d)

Procedure TOOL

Physical Library
Apollo, Cadence
Replace

DB Merge Opus, Cadence

Back-end

Pattern Generation Opus, Cadence

LVS and DRC Calibre, Cadence

Fab in

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Engineering ideas

Agenda

• Team Overview
• HW Based Design Flow and Tools
• HW Based Verification Methodologies
• Design Examples

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Engineering ideas

Verification Methodologies
Procedure – Verification methodologies
• Random vector
High Level
Verification • Deterministic vector
• Corner case vector
RTL Level
Verification
• Formal verification
STA Level – Language
Verification
• VHDL
HW Emulation • HDL Verilog
• System Verilog
Board Level
• Matlab-HDL Co-verification
Verification

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Engineering ideas

Agenda

• Team Overview
• HW Based Design Flow and Tools
• HW Based Verification Methodologies
• Design Examples
– 802.11a PHY Transceiver

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Engineering ideas

802.11a PHY Transceiver: Features

 Operating at frequency band of 5 GHz
 52 OFDM subcarriers
 Variety modulation methods (BPSK, QPSK, 16-QAM, 64-QAM)
 Advantages: Good performance for multipath environment (indoor)
High data transfer rates,
Less interference
 Applications: WLAN

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Engineering ideas

Spec & Block Design

802.11a Transmitter

plcp_tx_data
pulse_shape_re

plcp_data_vld
conv pilot guardtime data pulse
scrambler interleaver mapper ifft pulse_shape_im
encoder insertion insertion selection shaping
plcp sig_vld

pulse_shape_vld
plcp_tail_vld

clk

preamble
rst_n tx_control
generator

BLOCK 1 BLOCK 2

Transmitter top block design

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Engineering ideas

Timing Budget Analysis

 Block Delays
interrupt signal

plcp_tx

724 clock SIGNAL start

scrambler
1 clock

conv_encoder

243 clock

interleaver
51 clock / 99 clock / 195 clock 241 clock

mapper
51 clock

pilot_insertion
clock
142 clock

ifft
49 clock

guardtime_insertion
3 clock

data_selection

preamble_start

Total delay: 726 clks (~16us)

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RTL Level Simulation & Verification

 Transmitter Top Block

Input data from PLCP Transmission data over the air

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Gate Level Synthesis

 Transmitter Top Block Synthesis

Mapping to part: xc2v6000bf957-6,

Global buffer usage summary: BUFGs + BUFGPs: 1 of 8 (12%)
Mapping Summary: Total LUTs: 8149 (12%)
Mapper successful!
Process took 279.406 seconds realtime, 279.406 seconds cputime

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Engineering ideas

STA Verification

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Engineering ideas

Spec & Block Design

802.11a Receiver

guardtime
sync fft pilot_extract rx_buffer equalizer demapper deinterleaver viterbi descrambler
remove

plcp_rx

rx_control

BLOCK 1 BLOCK 2

Receiver top block design

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Engineering ideas

Timing Budget Analysis

 Timing Analysis
sync out vld

sync

242 clock SIGNAL start

guard time
remover
142 clock
fft

65 clock
pilot_extract
2 clock

rx_buffer
51 clock

demapper
1 clock
deinterleaver

110 clock
viterbi

1 clock
descram

48 clock
plcp_rx

662 clock

Total delay: 662 clks

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Engineering ideas

RTL Level Simulation & Verification

 Receiver Top Block

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BPSK QPSK 16QAM
Engineering ideas

Gate Level Synthesis

 Receiver Top Block Synthesis

Mapping to part: xc2v6000bf957-6

Global buffer usage summary: BUFGs + BUFGPs: 2 of 8 (25%)
Mapping Summary: Total LUTs: 13488 (19%)
Mapper successful!
Process took 664.656 seconds realtime, 664.656 seconds cputime

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Engineering ideas

STA Verification

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Engineering ideas

Agenda

• Team Overview
• HW Based Design Flow and Tools
• HW Based Verification Methodologies
• Design Examples
– H.264 Codec

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Engineering ideas

H.264 Decoder - Block Diagram

Inter-
Prediction
NAL Deblocking Post
Parser Σ
Intra- Filter Processing
Prediction

Scale &
Entropy
Inverse
Decoder
Transform

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Engineering ideas

H.264 Decoder - Platform Based Design

DB Filter
(RTL)
PPC405 DMA
Bus
Wrapper

PLB

Bus Bus Bus

Wrapper Wrapper Wrapper Bridge to
Peripheral
Parser Prediction Residual
Bus
(RTL) (RTL) (RTL)

OPB

DVI,USB, System
RS232, LAN, ACE,
JTAG,... CF Cards

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RTL Level Simulation and Verification

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STA Simulation and Verification

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System architecture for board level verification

test.264

CF PPC DMA DDR SDRAM

OPB BUS Bus Bridge PLB BUS

H.264 Decoder
VGA FRAME BRAM
BUFFER

PARSING PROCESS
(PARSER + ENTROPY DEBLOCKING-FILTER PREDICTION
MONITOR DECODER )

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Engineering ideas

Verification Flow

Design Environment
Reference
Decoder
Reference
=
Encoder
H264
Decoder

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Test Vectors

• Standard pattern
– QCIF Foreman 300 frames

• Other patterns:
– Akyio : slow movement
– Coast Guard : fast movement
– Others

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H.264 Decoder - Implementation

Target Device - Xilinx Virtex 4 FX60

Profile Baseline, Main

Resolution Up to HDTV

Frames per second 30

Entropy Coding CAVLC, CABAC

Latency 3200

Maximum Frequency 1400 MHz

Size 19000 LUTs

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Engineering ideas

H.264 Decoder Video Player

Red[7:0]
WiFi DAC Analog Red
Data Buffer
I/F
Green[7:0]
CTRL Bus DAC Analog Green
Blue[7:0]
USB DAC Analog Blue
Data Buffer
I/F
HSYNC
CTRL Bus VSYNC
Triple DAC- VGA
Interface VGA Connector

Micro SD
Data Buffer
I/F
CTRL Bus
WICHIP H.264
CF
DECODER Y[7:0] HDMI Interface
HDMI Connector
Data Buffer Cr[7:0] Chip Set
I/F
CTRL Bus Cb[7:0]

HDMI Connector,
HDTV Encoder
Component Video Output,
Chip Set VGA
HSYNC,VSYNC

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Engineering ideas

H.264 Encoder - Block Diagram

NAL
Bitstream
NAL Packager

Motion
Estimation

Reorder +
Entropy Encode
Motion
Compensation

Selector T/Q

Intra prediction

Input External Deblocking

Σ T-1/Q-1
Video Memory Filter

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Engineering ideas

H.264 Encoder - Platform Based Design

CAVLC/CABAC
(RTL)
PPC405 DMA
Bus
Wrapper

PLB

Bus Bus Bus

Wrapper Wrapper Wrapper Bridge to
Peripheral
Decoder ME TQ
Bus
(RTL) (RTL) (RTL)

OPB

DVI,USB,
System ACE,
RS232, LAN,
CF Cards
JTAG,...

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Engineering ideas

H.264 Encoder - Implementation

Target Device - Xilinx Virtex 4 FX100

Profile Baseline, Main

Resolution Up to HDTV

Output Bitrate 14 Mbps

Entropy Coding CAVLC, CABAC

Latency 4859

Maximum Frequency 70 MHz

Size 49000 LUTs

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Engineering ideas

H.264 Encoder System

`
CTRL Bus
RJ-45
Connector
Etherner
ENCODED DATA BUS
Y[7:0] Chip Set
Cr[7:0]
CMOS IMAGE SENSOR
Cb[7:0]
PIX[9:0]
WICHIP WICHIP H.264
PIX_CLK Image Processor HSYNC
ENCODER
VSYNC

PIX_CLK`

WiFi
ENCODED DATA BUS
Chip Set

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Engineering ideas

THANK YOU

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