Instruction Timing and

Execution in 8085
 8085 based system
• To make a complete system, the microprocessor
needs to be interfaced with the memories and
input and output devices.
• The memories required are of two types – RAM
and ROM.
• ROM is necessary to store some amount of fixed
programs.
• These programs are executed when the system is
powered on and are essential for the system.
8085 based system Contd..
• RAM is required in any system to store temporary
programs and data.
• A particular memory location is selected from the
memory by properly issuing the address for that
memory location and issuing the control signals
discussed in the previous section.
8085 based system contd..
• The microprocessor is the master in any
microcomputer system and the microprocessor
issues the required control signals to the
peripherals.
• Each location in a memory is given a number,
called an address. The maximum number of
locations that can be addressed will depend on the
number of bits in the address.
• In general, 2^n is the number of memory locations
addressed where n is the number of bits in the
address.
 MICROPROCESSOR
INSTRUCTIONS
• Every microprocessor has its own instruction set.
• Based on the design of the ALU and the decoding unit, the
microprocessor manufacturers generally list out the
instruction set for the every microprocessor.
• The instruction set consists of both the assembly language
mnemonics and the corresponding machine code.
 Format of Assembly
language programs contd..

Memory Machine Label Mnemonics comments

address code / opcode with operands
8000 3E START MVI A, 5FH load data in the
: accumulator
8001 5F

8002 Address of the next

memory location
 INSTRUCTION EXECUTION AND
TIMING DIAGRAM WITH MACHINE
CYCLES AND T STATES
• The 8085 microprocessor is designed to fetch the
instruction pointed by the program counter and then
decode and execute the instruction within the processor.
• If necessary, further operand fetch will take place before
completing the execution.
• Each instruction has two parts:
The operation code, known as opcode and another part -
operand.
 TIMING DIAGRAM

• The opcode is a command such as ADD, and the operand is

an object to be operated on, for ex. a byte or the contents
of a register.
• To complete the execution, 8085 needs to perform various
operations such as opcode fetch, Memory Read / Write or
I/O Read / Write.
 Definitions
• 1. Instruction Cycle
Defined as the time taken by the processor to complete,
execution of an instruction (i.e. time required to execute one
instruction). Instruction cycle consists of 1 to 5 machine cycles.
• 2. Machine Cycle:
The time required to complete one operation of accessing
memory or an I/O device. The machine cycle consists of 3 to 6 T-
states.
• 3. T state
The time corresponding to one clock period. The T state forms
the basic unit to calculate the execution of instructions and
programs in a processor.
 Different Machine Cycles
• The 8085 microprocessor has 5 (Five) basic machine cycles.
They are
a) Opcode fetch cycle (4T)
b) Memory read cycle (3 T)
c) Memory write cycle (3 T)
d) I/O read cycle (3 T)
e) I/O write cycle (3 T)
 Machine Cycles - Description
• Each instruction of the 8085 processor consists of one to
five machine cycles.
• An instruction execution will have compulsorily, the
opcode fetch cycle.
• Then depending upon the instruction, an instruction cycle
will have one or two or more other cycles in the list.
• When the 8085 processor executes an instruction, it will
need to access external memory and I/O devices, in other
words need many machine cycles in a specific order.
Clock Signal Shape
 Timing Diagram

• The timing diagram of an instruction are obtained by

drawing the binary levels on the various signals of 8085.
• It is drawn with respect to the clock of the microprocessor.
• It explains the execution of the instruction with the basic
machine cycles of that instruction, one by one in the order
of execution.
• Representation of Various Control signals generated
during Execution of an Instruction.
• Following Buses and Control Signals must be shown in a
Timing Diagram:
• Clock
• Higher Order Address Bus.
• Lower Address/Data bus
• ALE
• RD~
• WR~
• IO/M~
• S0,S1
Opcode fetch machine cycle
 Opcode fetch machine cycle

• At T1, the high order 8 address bits are placed on the

address lines A8 – A15 and the low order bits are placed on
AD7–AD0.
• The ALE signal goes high to indicate that AD0 – AD7 are
carrying an address and now that needs to be latched.
• At exactly the same time, the IO/M~ signal goes low to
indicate a memory access operation.
 Opcode fetch machine cycle
• At the beginning of the T2 cycle, the low order 8 address
bits are removed from AD7– AD0 and latched and the
controller sends the Read (RD~) signal to the memory.
• The RD~ signal remains low (active) for two clock periods to
allow for slow devices.
• During T2, memory places the data (i.e. opcode) from the
memory location on the lines AD7– AD0.
 Opcode fetch machine cycle
• During T3 the RD~ signal is Disabled (goes high).
• That makes the AD7– AD0 lines go to high impedance (or
tri- stated) mode.
• The opcode is placed into instruction register, and then
sent to decoder.
• During T4, the opcode is decoded by the processor and
necessary action or control is initiated for the execution of
the instruction fetched.
 MPU Communication and Bus Timing

Figure :Execution of MOV C, A instruction form memory to MPU

(machine code is 4FH = 0100 1111)20
 MPU Communication and Bus Timing
MOV C, A (1 byte instruction)

• The Fetch Execute Sequence :

1. The μp places a 16 bit memory address from PC (program counter)
to address bus.
– Figure : at T1
– The high order address, 20H, is placed at A15 – A8.
– the low order address, 05H, is placed at AD7 - AD0 and ALE is active high.
– Simultaneously the IO/M~ is in active low condition to show it is a
memory operation.
2. At T2 the active low control signal, RD~, is activated so as to
activate read operation; At the same time S0 and S1 become 1 and
1 respectively, it is to indicate that the MPU is in fetch mode
operation.
 Continue…

3. T3: The active low RD~ signal enabled the byte instruction,
4FH, to be placed on AD7 – AD0 and transferred to the
MPU. While RD~ high, the data bus will be in high
impedance mode. 4FH will then be placed in the
instruction register and then sent to decoder circuit.

4. T4: The machine code, 4FH, will then be decoded in

instruction decoder. The content of accumulator (A) will
then copied into C register at state T4.
8085 timing diagram for Opcode fetch cycle for MOV C, A .

8085 timing diagram for Opcode fetch cycle for MOV C, A .

Memory Read Machine Cycle
 Memory Read Machine Cycle
• The memory read machine cycle is exactly the same as the
opcode fetch except:
a) It has only 3 T-states
b) The S0 signal is set to 0.
c) The memory read machine cycle is executed by the
processor to read a data byte from memory.
d) The processor takes 3T states to execute this cycle.
e) The instructions which have more than one byte word size
will use the machine cycle after the opcode fetch machine
cycle.
 Execution of MVI B,43
(2 byte instruction)

• Instruction:
• 2000H MVI B, 43H

• Corresponding Coding:
• (Machine code is 06, and data is 43)
• Memory Location M/C code
• 2000H 06H
• 2001H 43H
MVI B, 43
• Timing diagram for STA 526AH.
(3 byte instruction)

Assume that Accumulator has the data C7H.

• This instruction is going to store content of A (i.e. C7) in
the memory location 526A.
• The opcode of the STA instruction is said to be 32H

• Address mnemonic opcode

• 41FFH STA 526A 32H
• 4200H 6AH
• 4201H 52H
• Timing diagram for STA 526AH.

• STA means Store Accumulator -The contents of the accumulator is stored

in the specified address(526AH).
• The opcode of the STA instruction is said to be 32H. It is fetched from the
memory 41FFH.
• Then read the lower order memory address which is (6AH). - Memory
Read Machine Cycle,
• Read the higher order memory address (52H).- Memory Read Machine
Cycle,
• The combination of both the addresses are considered and the content
from accumulator is written in 526AH. - Memory Write Machine Cycle,
• This will be the memory address for the instruction and let the content of
accumulator is C7H. So, C7H from accumulator is now stored in 526A.
STA 526A
Memory Write Machine Cycle
 Memory Write Machine Cycle

• The memory write machine cycle is executed by the

processor to write a data byte in a memory location.
• The processor takes 3T states to execute this machine cycle.
• Now, the active low WR~ signal is made to low indicating a
write operation to the memory chips.
 The Stack
• The stack is an area of memory identified by the
programmer for temporary storage of information.
• The stack is a LIFO structure.
• Last In First Out.
• The stack normally grows backwards into memory.
• In other words, the programmer Memory

defines the bottom of the stack

and the stack grows up into
reducing address range. The Stack
grows
backwards
into memory Bottom
of the
Stack

46
 The Stack
• Given that the stack grows backwards into memory, it is
customary to place the bottom of the stack at the end of
memory to keep it as far away from user programs as
possible.
• In the 8085, the stack is defined by setting the SP (Stack
Pointer) register.

LXI SP, FFFFH

• This sets the Stack Pointer to location FFFFH (end of

memory for the 8085).

47
Saving Information on the Stack

• Information is saved on the stack by PUSHing it on.

• It is retrieved from the stack by POPing it off.

• The 8085 provides two instructions: PUSH and POP

for storing information on the stack and retrieving it
back.
• Both PUSH and POP work with register pairs
ONLY.
48
 The PUSH Instruction
• PUSH B
• Decrement SP
• Copy the contents of register B to the memory location
pointed to by SP
• Decrement SP
• Copy the contents of register C to the memory location
pointed to by SP
B C
12 F3
FFFB
FFFC
FFFD F3
FFFE 12
FFFF SP

49
 The POP Instruction
• POP D
• Copy the contents of the memory location pointed to by the
SP to register E
• Increment SP
• Copy the contents of the memory location pointed to by the
SP to register D
• Increment SP
D E
12 F3
FFFB
FFFC
FFFD F3 SP
FFFE 12
FFFF

50
 Operation of the Stack
• During pushing, the stack operates in a “decrement then
store” style.
• The stack pointer is decremented first, then the
information is placed on the stack.

• During poping, the stack operates in a “use then

increment” style.
• The information is retrieved from the top of the the
stack and then the pointer is incremented.

• The SP pointer always points to “the top of the stack”.

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 LIFO
• The order of PUSHs and POPs must be opposite of each other in order to
retrieve information back into its original location.

PUSH B
PUSH D
...
POP D
POP B

• Reversing the order of the POP instructions will result in the exchange of
the contents of BC and DE.

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 Subroutines
• A subroutine is a group of instructions that will be used
repeatedly in different locations of the program.
• Rather than repeat the same instructions several
times, they can be grouped into a subroutine that is
called from the different locations.

• In Assembly language, a subroutine can exist anywhere

in the code.
• However, it is customary to place subroutines
separately from the main program.

54
 Subroutines
• The 8085 has two instructions for dealing with
subroutines.
• The CALL instruction is used to redirect program
execution to the subroutine.
• The RET instruction is used to return the
execution to the calling routine.

55
 The CALL Instruction
• CALL 4000H
• Push the address of the instruction immediately
following the CALL onto the stack
• Load the program counter with the 16-bit address
supplied with the CALL instruction.

2000 CALL 4000

2003
PC 2003
FFFB
FFFC
FFFD 03
FFFE 20
FFFF SP

56
 The CALL Instruction

• MP Reads the subroutine address from the next two

memory locations and stores the higher order 8bits of
the address in the W register and stores the lower order
8bits of the address in the Z register,
• – Pushes the address of the instruction immediately
following the CALL onto the stack [Return address],
• – Loads the program counter with the 16-bit address
supplied with the CALL instruction from WZ register.
 The RET Instruction
• RET
• Retrieve the return address from the top of the stack,
• Load the program counter with the return address.

PC 2003
FFFB
4014 ... FFFC
4015 RET FFFD 03 SP
FFFE 20
FFFF

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