Digital Logic Design

Lecture 1:
Digital Logic Families
By
Dr.S.Nagarajan
Logic Family
 A group of compatible ICs with the same logic
levels and supply voltages for performing various
logic functions, fabricated using a specific circuit
configuration is referred to a logic family.

 Bipolar Logic Families

 Unipolar Logic Families

2
BIPOLAR LOGIC FAMILIES
Components
 Resistors
 Diodes
 Transistors

Types
 Saturated
 Non-Saturated
BIPOLAR LOGIC FAMILIES
• RTL : Resistor Transistor Logic.
• DCTL : Direct Coupled Transistor Logic.
• DTL : Diode Transistor Logic
• HTL : High threshold Logic.
• TTL : Transistor Transistor Logic.
• I2L : Integrated Injection Logic.
• ECL : Emitter coupled logic.
UNIPOLAR LOGIC FAMILIES
 PMOS
 NMOS
 CMOS
CLASSIFICATION OF DIGITAL ICs
• SMALL SCALE INTEGRATION (SSI)
– Less than 12 equivalent individual gates
– No. of components up to 99
• MEDIUM SCALE INTEGRATION (MSI)
– Equivalent individual gates: 12-99
– No. of components: 100-999
• LARGE SCALE INTEGRATION (LSI)
– Equivalent individual gates: 100-999
– No. of components: 1000-9999
• VERY LARGE SCALE INTEGRATION (VLSI)
– Equivalent individual gates: above 1000
– No. of components: above 10000
 CHARACTERISTICS OF DIGITAL ICs
• SPEED OF OPERATION
• POWER DISSIPATION
• FIGURE OF MERIT
• FAN OUT
• CURRENT AND VOLTAGE PARAMETERS
• NOISE IMMUNITY
• OPERATING TEMPERATURE RANGE
• POWER SUPPLY REQUIREMENTS
• FLEXIBILITIES AVAILABLE
SPEED OF OPERATION
Specified in terms of Propagation delay
SPEED OF OPERATION
The delay times are measured between the
50% voltage levels of input and output
waveforms.

High State to Low

Low state to High
POWER DISSIPATION
• Each gate is connected to a power supply VCC. It
draws a certain amount of current during its
operation. Since each gate can be in a High, Transition
or Low state, there are three different currents drawn
from power supply.
– ICCH: Current drawn during HIGH state.
– ICCT: Current drawn during HIGH to LOW, LOW to HIGH
transition.
– ICCL: Current drawn during LOW state.
• For TTL, ICCT the transition current is negligible, in comparison
to ICCH and ICCL. If we assume that ICCH and ICCL are equal
then,
Average Power Dissipation = Vcc * (ICCH + ICCL)/2
• Specified in milliwatts
FIGURE OF MERIT
• Product of speed and power
• Figure of merit (pJ)=
Propagation delay (ns) x power (mW)
• Low value is desirable
FAN-OUT
• This is the number of similar gates which can
be driven by a gate.
• High fan-out is advantageous as it reduces
the need for additional drivers to drive more
gates.
VOLTAGE PARAMETERS
• V : High level output Voltage
OH

The minimum output voltage in HIGH state (logic '1').

• 2.4 V for TTL and 4.9 V for CMOS.
• VOL : Low level output Voltage
The maximum output voltage in LOW state (logic '0').
• 0.4 V for TTL and 0.1 V for CMOS.
• VIH : High level Input Voltage
The minimum input voltage guaranteed to be
recognized as logic 1.
• 2 V for TTL and 3.5 V for CMOS.
• VIL : Low level Input Voltage
• The maximum input voltage guaranteed to be
recognised as logic 0.
• 0.8 V for TTL and 1.5 V for CMOS.
CURRENT PARAMETERS
• IOH : High Level Output Current
The maximum current which the gate can sink in 1
level.
• IOL : Low Level Output Current
The maximum current which the gate can sink in 0
level.
• IIH : High Level Input Current
The minimum current which must be supplied by a
driving source corresponding to 1 level voltage.
• IIL : Low Level Input Current
The minimum current which must be supplied by a
driving source corresponding to 0 level voltage.
CURRENT PARAMETERS
• ICC (1): High Level Supply Current
The supply current when the output of the gate is at
logic 1.
• ICC (0): Low Level Supply Current
The supply current when the output of the gate is at
logic 0.
NOISE IMMUNITY
• The unwanted signals are referred to as noise
• This may cause the voltage at the input to a logic
circuit to drop below VIH or rise above VIL.
• may produce undesired operation
• The circuit’s ability to tolerate noise signals is
referred to as the noise immunity.
• The quantitative measure of noise immunity is noise
margin.
• Noise margin is the maximum noise added to an
input signal of a digital circuit that does not cause an
undesirable change in the circuit output.
NOISE MARGIN
OPERATING TEMPERATURE
• Consumer And Industrial Applications:
0 To 70 C
• Military Applications;
-55 To 125 C
FLEXIBILITIES AVAILABLE
• The breadth of the series
Type of different logic functions available in the
series
• Popularity of the series: Cost
• Wired Logic capability:
The output can be connected together to perform
additional logic without ant extra hardware
• Availability of complement output
Eliminates the need for additional inverters
• Type of output: passive pullup , Active pullup
Digital Logic Design
Lecture 2:
Digital Logic Families
By
Dr.S.Nagarajan
RESISTOR-TRANSISTOR LOGIC
• Consists of resistors and transistors
• Simple
• Basic RTL gate is NOR gate
• Obsolete now
2-Input RTL NOR gate driving N
similar gates
Loading Considerations
• Low 0 Level output  0.2 V (=VCE,Sat)
• High 1 level output voltage depends on the
number of gates connected to the output.
• Under no load, HIGH level output voltage will
be slightly less than VCC.
• When N similar gates are being driven….
Equivalent Circuit
Loading Considerations
• Base current for each load resistor =
 
 3 .6  0 . 8  1 2 .8
IB   . 
450 N 640N  450
 640  
 N 
• Collector current for the load transistor under
saturation =
3 .6  0.2
IC,sat   5.31 mA
640
Loading Considerations
• The value of N must satisfy the following
relation:
hFE .IB  IC,sat

• For N=5 IB= 0.767 mA.

• Hence hFE must be greater than 7.
NOISE MARGIN
• Low level output voltage = 0.2 V
• Cut-in Voltage of Transistor = 0.5 V
• Hence Logic 0 noise margin = 0.5 -0.2 = 0.3 V
NOISE MARGIN
• Logic 1 noise margin depends upon the number of
gates being driven.
• For N=5,
 90   640 
VO   . 3.6    . 0.8   1.14 V
 640  90   640  90 
• For hFE=10, the total base current required for load
transistors to be driven into saturation = 5.  5.31  mA
 10 

• Corresponding VO = 1.04 V
• Hence 1 Level Noise Margin = 1.14-1.04 =0.1 V
PROPAGATION DELAY TIME
• Affected by number of gates it drives.
• When the output of the gate is LOW, all the load
transistors are cut-off and base emitter junction of
each transistor appears to a capacitor.
• Time constant (Low to High)=
 450 
 640   NC   640N  450  C
 N 
• The resistance in the collector circuit pulls up the
voltage from LOW to HIGH and hence is known as
PULL-UP resistor.
WIRED LOGIC
• Fan-in can be increased if the outputs of the
gates are connected together, which is
referred to as wired-AND or Implied-AND.
Y  Y1 . Y2
Y  A B.CD
Y  A BCD
DIRECT-COUPLED TRANSISTOR LOGIC (DCTL)
• DCTL is from RTL if the base resistors RB are
omitted and inputs are directly coupled to the
transistors
• NOR logic
• Logic 1 voltage is 0.8 V (=VBE,sat)
• Logic 0 voltage is 0.2 V (=VCE,sat)
• Separation between logic 1 and logic 0 (LOGIC
SWING) is very small
• Hence noise margin is very poor
DIRECT-COUPLED TRANSISTOR LOGIC (DCTL)
• Not popular
• Main disadvantage : Current hogging
• Because of non-identical input characteristics of
transistors – Hence saturation voltages of load
transistors may be different.
• Current hogging: When the transistor with less base-
emitter voltage corresponding to saturation enters
into saturation will not allow other transistors to
enter saturation and will take whole of the current
supplied by the driver gate.
DIODE TRANSISTOR LOGIC (DTL)
• More complex than RTL
• Greater Fan-out
• Improved noise margin
Disadvantage:
• Slower speed

• Completely replaced by TTL

• Basic gate is NAND gate
3-IINPUT DTL NAND GATE