Microprocessors – IV

Interruptions
Yashar Hajiyev
Microprocessor Structural Organization
(architecture)
Interruptions
 Interruptions
The interrupt sequence in Intel 8080 may be illustrated as follows:

If INTE is equal to 0,  the entire interrupt handling system is disabled →

→ no interrupts will be accepted.
Interruptions
Interruptions
 Interruptions
Interrupts
The basic 8085 provides four interrupt lines
which are hardware vectored to dedicated locations. 

If this is not adequate then the following mechanism can be used....

An interrupt signal is acknowledged by the 8085 and external interrupting
logic can then send an instruction op-code
(usually RESET or CALL plus a vector address - but to implement a fast event
counter it could be to INC a dedicated Register ).
 Interrupt flip-flop Instructions
1-byte Instructions which operate directly upon Interrupt Enable
flip-flop INTE  ─
Interrupt flip-flop Instructions
 Interrupt flip-flop Instructions
Whenever INTE is equal to 0 entire interrupt handling system is disabled,
and no interrupts will be accepted.

When CPU recognizes an interrupt request from external device →

following actions occur:
(1) Current Instruction to be completed;
(2) Interrupt enable bit → INTE is reset from = 1 → to = O;
(3) Interrupting device supplies, via hardware, one instruction 
 normally an RST instruction → which CPU executes.

That instruction not appear anywhere in memory, and programmer

has no control over it.

Because it is function of interrupting device's controller design.

The program counter (PC) isn’t incremented before this instruction.
 Interrupt Instructions
Interrupting of current program will occur through next steps:
(1) Processor stops executing of current/main program;
(2) To store in memory (stack zone) the information needs to continue/resume
main program from interrupted point;
(3) To escape from current/main program to special program that serves
for interruption;
(4) After completing special program the Processor return to run the
main (interrupted) program;
Requests for interrupt are moistly asynchrony (rarely synchrony) regarding
executed program. Requests might be initiated by 
malfunctioning of computer internal / external units, input/output operations,
program instructions etc..
For coordination of succession of current/main program and interrupt
program the executing Operating system does 
i. temporarily terminate current program, and select interrupt request to be served;
ii. storing of status of current program;
iii. to identify and initiate special program to serve and handle concrete interrupt request;
iv. to run and complete relevant service program for concrete interrupt request;
v. recovering of status of main program and to start to run it;
 Interruptions
How to select right interrupting request among few of them
All interrupt requests provided with priority → (0,1,…n) that was
kept in register of interruptions.
0 → is the highest priority.
Two types of priority → relative and absolute.
When the priority of current/main program is lower than priority of
interrupting program  2 cases 
1) absolute priority  current program is terminated when high
priority of interruption is selected;
2) relative priority  current program not to be interrupted up to end;
Special procedure enable to select the right/active request (highest priority)
among n available requests.
The right/active procedure was selected ▬ gives the address of first instruction
belonging to that interrupt servicing program.
 Interruptions
Allocation of interruptions servicing programs over the memory addresses
1) Allocation over fixed memory addresses space.
Sequences of different interrupt serviced program doesn’t changed.
Fast method, but applicable for small system with few interruptions.

2) To enter to interrupting program by means of PSW (program status word).

In some fixed memory field→ to be formed two massives 
old PSWs massive and new PSWs massive.
Every pair of PSWs is correspond to request on interruption.

After performing active request → the PSW of interrupted/main program

to be downloaded to → old PSWs massive; to concrete address.
The PSW of interrupting program downloaded from → new PSWs massive.
Address is written in memory from new PSW.
 Interruptions
Allocation of interruptions servicing programs over the memory addresses
3) Vector interruption → for every accepted interruption request→
the address of vector interruption to be formed.
All addresses of vector interruptions to be in fixed memory field.
Using the address of indicated in vector → the address of first instruction
of interrupting program to be found.
As vector of interruptions might be used 
► address of first instruction of interrupting program;
Fast method, but applicable for small system with few interruptions.
►command of unconditional jumping to program ;

Interrupt vector  is the location from where the program proceeds with
execution of interrupt servicing program;
Interrupt Request
Interrupt request
 INTERRUPT SYSTEM

When interrupt request arrives, microcontroller executes the current instruction and
then stops the regular program execution. As a result, the current program memory
address is automatically pushed onto the stack and the default address
(predefined by the manufacturer) is written to the program counter.

The location from where the program proceeds with execution is called
 interrupt vector.
For the PIC16F887 microcontroller, this address is 0004h. As seen in figure below,
the location containing the interrupt vector is passed over during regular program
execution.

A part of program to be executed when an interrupt request arrives is called an

 interrupt routine.
Its 1st instruction is located at interrupt vector.

Interrupt vector  contains address of interrupt service procedure.

 INTERRUPT SYSTEM

I
The location from where the program proceeds with execution is called
 interrupt vector.

Its 1st instruction is located at interrupt vector.

How long will it take to execute this subroutine and what it will be like
depends on the skills of the programmer as well as on interrupt source itself.

Some of the microcontrollers have more interrupt vectors

(every interrupt request has its vector), but in this case there is only one.
Consequently, the first part of the interrupt routine consists in interrupt source
detection.

Finally, when the interrupt source is recognized and the interrupt routine
is executed, the microcontroller reaches the RETFIE instruction,
pops the address from the stack and proceeds with program execution from where it
left off.
Interrupt flip-flop Instructions
Interrupt Instructions
 Interrupt flip-flop Instructions
Interrupting device supplies instruction (normally RST (reset) instruction),

1-byte call to one of 8 eight-byte subroutines → located in
first 64 words of memory.

For instance,  RST 0h instruction →subroutine processes 

CPU will be called into execution via an eight-byte instruction
sequence at memory locations OOOOH to 0007H;

A digital input device may supply instruction  RST 1h → subroutine

that processes the digital input signals
will be called via a sequence of instructions occupying
memory locations 0008H to OOOFH.

Any of these 8-byte subroutines may to process the interrupt, if necessary.

Any device may supply an RST instruction (may supply any 8080
instruction).
Interrupt flip-flop Instructions
 Interrupt flip-flop Instructions
♦ Interrupt Vector → is a location near the bottom of memory associated
with
each I/O device class (floppy disks, hard disks, timers, terminals).
It contains address of interrupt service procedure.

All interrupts starts → by saving registers, often in process table entry

for current process → it can be restarted later.
Then information pushed earlier onto stack by interrupt, is removed and
the stack pointer is set to point to a temporary stack used by the process
handler

Each I/O device class (e.g., floppy disks, hard disks, timers,
terminals) associated with location (near bottom of memory)
of interrupt vector.

Interrupt vector  contains address of interrupt service procedure.

 Interrupt flip-flop Instructions
most significant 8 bits of ←the address into the C register,
and loads the least significant 8 bits of the address into the B register
General
RST INSTRUCTION

This section describes the RST (restart) instruction, which is a special purpose
subroutine jump. This instruction occupies one byte.

Programming for tile 8085

The interrupts have the following priority:

TRAP highest
RST 7.5
RST 6.5
RST 5.5
INTR lowest

Thus, an RST5.5 interrupt can Interrupt the service routine for an RST7.5
interrupt.
♦ Interrupt Vector → is a location near the bottom of memory associated with
each I/O device class (floppy disks, hard disks, timers, terminals).

It contains address of interrupt service procedure.

All interrupts starts → by saving registers, often in process table entry for current
process – it can be restarted later.
Then information pushed earlier onto stack by interrupt, is removed and the stack
pointer is set to point to a temporary stack used by the process handler

Each I/O device class (e.g., floppy disks, hard disks, timers, terminals) associated
with location (near bottom of memory) of interrupt vector.

Interrupt vector  contains address of interrupt service procedure.

Every hardware detects own interrupt conditions.
Then it triggers appropriate interrupt in CPU.
Interrupt vector table  maps each interrupt to
memory address of its Interrupt Service Routine (ISR).

CPU first goes to this table to find

address of ISR and then jumps to actual ISR code.

CPUs contain several different interrupts to handle

different external events uniquely
Implementation of Processes
Implementation of Processes

Skeleton of what the lowest level of the operating system

does when an interrupt occurred
 Implementation of Processes

Discrete hardware detects interrupt

conditions and then triggers the
appropriate interrupt in the CPU.
Interrupt vector table maps each
interrupt to memory address of its
Interrupt Service Routine (ISR).
The CPU first goes to this table to find
address of ISR and then jumps to actual
ISR code.
CPUs contain different interrupts to
handle different external events uniquely
16 – BIT REGISTERS OF 8085 MICROPROCESSOR:
Stack pointer (SP) and Program counter (PC).
 4 Instruction types 
Data processing → instructions for computational capabilities for processing numeric data →
performed in MP registers;
Data instructions → to transfer programs and data into memory and the results to user;
Control instructions → to test the value of data word or status of computation storage
→ instructions for moving data between memory and registers;
I/O;

7 Groups of Instruction commands 

► Moving data → between main memory and registers;
► Executing arithmetical and logical operations ;
► Regulation of conducting current programs;
► Relation with sub-programs ;
► Shift data in registers, clean up of registers, formatting of additional
codes;
► I/O instructions;
► Special instructions;

4 types of operands  Addresses; Numbers ( Integer or fixed point; floating point; Decimal );
Floating point;
Instruction Format
Instruction Format  three-bytes instructions
 Sample programs1
Write an assembly program to add Write an assembly program to
two numbers Program multiply a number by 8 program

► MVI D, 8Bh move data to D-reg ► MVI A, 30H move data to A-reg
► MVI C, 6Fh move data to C-reg ► RRC shift of (A) content to right with carry
► RRC shift of (A) content to right with carry
► MOV A, C move data from C-reg to A-reg
► RRC shift of (A) content to right with carry
► ADD D sum up (A) with (D)
► OUT PORT1
► OUT PORT1 content of (A) to Port 1 ► HLT
► HLT stop MP

.
 Sample programs2
Write an assembly program to find greatest between
two numbers.
Program
► MVI B, 30h move data to B-reg;
► MVI C, 40h move data to C-reg;
► MOV A, B move data from B-reg to A-reg;
► CMP C compare content of A-reg with C-req;
► JZ EQU jump if equal (A)=(C) ;
► JC GRT jump if carry;
► OUT PORT1 move content of A-reg to Port 1;
► HLT stop microprocessor;

► EQU: MVI A, 01h move O1H to A-reg;

► OUT PORT1 move content of A-reg to Port 1;
► HLT stop microprocessor;
► GRT: MOV A, C move data from C-reg to A-reg;
► OUT PORT1 move content of A-reg to Port 1;
► HLT stop microprocessor;

.
 Registers

MP 8085/8080A  six general-purpose registers to store 8-bit data; 

B,C,D,E,H, and L.
They can be combined as register pairs - BC, DE, and HL - to perform 16-bit
operations.
The programmer can use these registers to store or copy data into registers by
using data copy instructions.
 Registers
Program Counter (PC)  16-bit register deals with sequencing the execution of
instructions. PC is memory pointer. Memory locations have 16-bit addresses,
MP uses this PC to sequence the execution of instructions.
Function of PC is to point to memory address from which the next byte is to be
fetched.
After fetching of byte (machine code) the PC is incremented by
one to point to next machine code location in memory.

Stack Pointer (SP) 16-bit register used as a memory pointer.

It points to memory location in R/W memory, called the stack.
The beginning of stack is defined by loading  16-bit address
in SP.
General Definition
General Definition
General Definition
General Definition
Interruptions
Externally initiated signal

INTR(i/p) - Interrupt request.

INTA bar (o/p) - It is used as acknowledge interrupt.
TRAP(i/p) - This is non maskable interrupt and has
highest priority.
HOLD(i/p) - It is used to hold the executing program.
HLDA(o/p) - Hold acknowledge.
READY(i/p) - This signal is used to delay the
microprocessor read or write cycle until a slow responding
peripheral is ready to accept or send data.
RESET IN bar - When the signal on this pin goes low,
the program counter is set to zero, the bus are tri-stated, &
MPU is reset.
RESET OUT - This signal indicate that MPU is being
reset. The signal can be used to reset other devices.
RST 7.5, RST 6.5, RST 5.5 (Request interrupt) - It is
used to transfer the program control to specific memory
location. They have higher priority than INTR interrupt.
 CPU
The actual work of the microprocessor is carried out in the Arithmetic Logic Unit.
Most of these operations are in fact performed by addition.
To perform subtraction, the CPU first finds the complement of the number to be
subtracted and then adds the two numbers.
Multiplication and division can be performed by carrying out multiple addition or
subtraction operations.
To compare two numbers, the CPU will subtract them and then check to see if there is a
remainder, and so on.
In order to carry out its operations, the processor has storage locations, called registers,
for numbers and instructions it is operating on. For example, to add two numbers, the
first number might be loaded into Register A, the second into Register B and the result
stored in Register C. To speed up the operations of the processor, the Prefetch unit
looks ahead in the program to find the next instructions and preloads them into registers,
to cut down on time wasted waiting for the next instruction.
The microprocessor connects to the external components of the computer via "buses":
sets of parallel conductors used to move data in the form of electrical pulses. There are
three types of buses: the data bus carries the binary-coded information and instructions;
the address bus carries binary-coded numbers which identify storage locations in main
memory, much like the postal code on a letter; the control bus carries timing signals,
read-write signals, interrupt requests and similar signals between the microprocessor
and external devices.
1All CPU designs include a register or set of registers, often known as
the program status word (PSW), that contain status information. The PSW
typically con­tains condition codes plus other stains information. Common fields
or flags include the following:
Sign: Contains the sign bit of the result of the last arithmetic operation.
Zero: Set when the result is 0.
Carry: Set if an operation resulted in a carry (addition) into or borrow (sub-
traction) out of a high-order hit. Used for multiword arithmetic operations.
Equal: Set if a logical compare result is equality.
Overflow: Used to indicate arithmetic overflow
Interrupt enable/disable: Used to enable or disable interrupts.
Supervisor: Indicates whether the CPU is executing in supervisor or user
mode. Certain privileged instructions can be executed only in supervisor mode,
and certain areas of memory can be accessed only in supervisor mode.
A number of other registers related to status and control might be found in a
particular CPU design. In addition to the PSW, there may be a pointer to a
block of memory containing additional status information (e.g., process control
blocks).
General Definition
 Interrupt-Driven Input/Output (I/O)

How it works  the I/O module receives READ command from MP .

I/O proceeds to read data from peripheral device. Once data are in module’s data register/buffer
→ the interrupt signal from I/O module is send through control line to MP. When request
signal comes from MP → I/O places data on data bus.

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Functioning of Interrupt-Driven Input/Output (I/O)

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 Configuration of system of Interrupt-Driven
Input/Output (I/O)

Two design issues for Interrupt driven I/O module  1.How does processor deterermine
which device issued interrupt;
2. If multiple Interruption signals → how decide which to proceed?

Decide identification  4 categories of technique 

Multiple interrupt lines  between MP and I/O; in practice each line several
attached I/O modules.
Software poll (time consuming)  determine which I/O module causes
interrupt 
MP raises TESTI/O command and places address code of device on address
bus. I/O contains addressable status register. Positive signal comes to MP
from active I/O. MP reads status signal and branches to device specific
service program;

Daisy chain (hardware poll, vectored)  When MP senses interrupt signal, it

sends signal through Interrupt acknowledge line is daisy chained through
all I/O modules.
Signal propagates through all I/O and gets to requested module. That module
responds by placing word (vector) (address codes) on data bus.
After MP sends address codes of active device → vectored interrupt

Bus arbitration (vectored). 56

57
 Intel 82C55 Programmable Peripheral Interface

24 I/O lines → are

divided into three 8-
bit groups (A,B,C)
are
working as outlet
and
inlet I/O ports.

4-bit groups (CA

and
CB) and they curry
control and status
signal for A and B
I/O ports

Left side is internal

Interface to INTELL
80386 (D0-D7) to
transfer data to/from
Control register is loaded by MP to control the mode of operations. I/O and transfer
Transfer take place when Chip Select is enabled with Read and Write control
signals. INFO to
control register.
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 Intel 82C55 Programmable Peripheral Interface

The control signals → for two

purposes → hand shaking and
interrupt signals

hand shaking → is timing

mechanisms → one control line
is
used to send DATA READY → to
indicate that data present on I/O
lines.
Other control line → is
Acknowledge
line to indicate → data have
been
read, and data line might be
cleared.

Another control line → is

Interrupt Request line and tied
back to the system bus.
Keyboard → 8 bits of input. Two of this bits Shift and Control have special
meaning to the keyboard-handling program executing in the processor.
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DDD represents a destination register. SSS represents a source
register. Both DDD and SSS are interpreted as follows:

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 Interrupt-Driven Input/Output (I/O)

RST -- Special Restart Instruction Used with Interrupts

The machine control instructions are as follows:

EI ▬Enable Interrupt System;
D1 ▬ Disable I nterrupt System;
A non-maskable TRAP interrupt for handling serious problems
such as power failures;
Three separately maskable interrupts that generate internal
RST instructions;
The SIM instruction
sets the interrupt mask and/or writes out a bit of serial data;
The interrupts have the following priority:

TRAP▬highest
RST7.5
RST6.5
RST5.5
INTR ▬ lowest

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 Interrupt-Driven Input/Output (I/O)

RST -- Special Restart Instruction Used with Interrupts

When more than one interrupt is pending, the processor

always recognizes the higher priority interrupt first.
These priorities apply only to the sequence in which interrupts
arc recognized. Program routines that service
interrupts have no special priority. Thus, an RST5.5 interrupt
can interrupt the service routine for an RST7.5
interrupt. If you want to protect a service routine from
interruption, either disable the interrupt system (DI
instruction), or mask out other potential interrupts (SIM
instruction).

RST instruction has the following format:

Opcode Operand
RST code

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Interrupt-Driven Input/Output (I/O)

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Interrupt-Driven Input/Output (I/O)

64
Interrupt-Driven Input/Output (I/O)

65
Interrupt-Driven Input/Output (I/O)

66
Interrupt-Driven Input/Output (I/O)

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Interrupt-Driven Input/Output (I/O)

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General Definition