Lecture

Lecture 55
Fault
Fault Simulation
Simulation
 Problem and motivation
 Fault simulation algorithms
 Serial
 Parallel
 Deductive
 Concurrent
 Random Fault Sampling
 Summary

Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 7 1

 Problem
Problem and
and Motivation
Motivation
 Fault simulation Problem: Given
 A circuit
 A sequence of test vectors
 A fault model
Determine
 Fault coverage - fraction (or percentage) of
modeled faults detected by test vectors
 Set of undetected faults
 Motivation
 Determine test quality and in turn product quality
 Find undetected fault targets to improve tests

Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 7 2

 Fault
Fault simulator
simulator in
in a
a VLSI
VLSI
Design
Design Process
Process
Verified design Verification
netlist input stimuli

Fault simulator Test vectors

Modeled Remove Test Delete

fault list tested faults compactor vectors

Fault Low Test

coverage generator Add vectors
?
Adequate
Stop
Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 7 3
 Ripple
Ripple carry
carry adder
adder
Apply: C0 Ai Bi
0 00000000 … 32%
0 01010101 … 57%
0 10101010 … 68%
0 11001100 … 78%
1 00110011 … 89%
1 01010101 … 100%
1 10101010 … 100%
1 11111111 … 100% C0 Ai Bi
1 01010101 … 40%
1 00110011 … 64%
0 11001100 … 86%
0 10101010 … 100%
0 01010101 … 100%
0 00000000 … 100%

Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 6 4

 Fault
Fault Simulation
Simulation Scenario
Scenario
 Circuit model: mixed-level
 Mostly logic with some switch-level for high-
impedance (Z) and bidirectional signals
 High-level models (memory, etc.) with pin faults
 Signal states: logic
 Two (0, 1) or three (0, 1, X) states for purely
Boolean logic circuits
 Four states (0, 1, X, Z) for sequential MOS circuits
 Timing:
 Zero-delay for combinational and synchronous
circuits
 Mostly unit-delay for circuits with feedback

Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 7 5

 Fault
Fault Simulation
Simulation Scenario
Scenario
(continued)
(continued)
 Faults:
 Mostly single stuck-at faults
 Sometimes stuck-open, transition, and path-delay
faults; analog circuit fault simulators are not yet in
common use
 Equivalence fault collapsing of single stuck-at
faults
 Fault-dropping -- a fault once detected is dropped
from consideration as more vectors are simulated;
fault-dropping may be suppressed for diagnosis
 Fault sampling -- a random sample of faults is
simulated when the circuit is large

Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 7 6

 Fault
Fault Simulation
Simulation
Algorithms
Algorithms
 Serial
 Parallel
 Deductive
 Concurrent
 Differential

Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 7 7

 Serial
Serial Algorithm
Algorithm
 Algorithm: Simulate fault-free circuit and save
responses. Repeat following steps for each
fault in the fault list:
 Modify netlist by injecting one fault
 Simulate modified netlist, vector by vector,
comparing responses with saved responses
 If response differs, report fault detection and
suspend simulation of remaining vectors
 Advantages:
 Easy to implement; needs only a true-value
simulator, less memory
 Most faults, including analog faults, can be
simulated

Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 7 8

 Serial
Serial Algorithm
Algorithm (Cont.)
(Cont.)
 Disadvantage: Much repeated computation;
CPU time prohibitive for VLSI circuits
 Alternative: Simulate many faults together

Test vectors Fault-free circuit Comparator f1 detected?

Circuit with fault f1

Comparator f2 detected?
Circuit with fault f2

Comparator fn detected?
Circuit with fault fn

Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 7 9

 Parallel
Parallel Fault
Fault Simulation
Simulation
 Compiled-code method; best with two-
states (0,1)
 Exploits inherent bit-parallelism of logic
operations on computer words
 Storage: one word per line for two-state
simulation
 Multi-pass simulation: Each pass simulates
w-1 new faults, where w is the machine
word length
 Speed up over serial method ~ w-1
 Not suitable for circuits with timing-critical
and non-Boolean logic

Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 7 10

Parallel
Parallel Fault
Fault Sim.
Sim. Example
Example
Bit 0: fault-free circuit
Bit 1: circuit with c s-a-0
Bit 2: circuit with f s-a-1

1 1 1
c s-a-0 detected
a 1 0 1
1 1 1 1 0 1
b e 1 0 1
c s-a-0
g
0 0 0

d f s-a-1 0 0 1

Fault injection can be done via netlist modification

Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 7 11

Deductive
Deductive Fault
Fault Simulation
Simulation
 One-pass simulation
 Each line k contains a list Lk of faults
detectable on k
 Following true-value simulation of each
vector, fault lists of all gate output lines
are updated using set-theoretic rules,
signal values, and gate input fault lists
 PO fault lists provide detection data
 Limitations:
 Set-theoretic rules difficult to derive for non-
Boolean gates
 Gate delays are difficult to use

Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 7 12

 Deductive
Deductive Fault
Fault Sim.
Sim.
Example
Example
Notation: Lk is fault list for line k

kn is s-a-n fault on line k

1 {a0} Le = La U Lc U {e0}
a
= {a0 , b0 , c0 , e0}
1 {b0 , c0} e 1
b
c 1
{b0} g
d f 0 U
Lg = (Le Lf ) U {g0}
{b0 , d0}
{b0 , d0 , f1}
= {a , c , e , g }
Faults0detected
0 0 by
0

the input vector

Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 7 13

Concurrent
Concurrent Fault
Fault Simulation
Simulation
 Event-driven simulation of fault-free circuit and
only those parts of the faulty circuit that differ in
signal states from the fault-free circuit.
 A list per gate containing copies of the gate
from all faulty circuits in which this gate differs.
List element contains fault ID, gate input and
output values and internal states, if any.
 All events of fault-free and all faulty circuits are
implicitly simulated.
 Faults can be simulated in any modeling style or
detail supported in true-value simulation (offers
most flexibility.)
 Faster than other methods, but uses most
memory.
Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 7 14
 Conc.
Conc. Fault
Fault Sim.
Sim. Example
Example
a0 b c e
0 1 0 1 0 1 0
0 0 0 0
1 0 0 1
1
a 1 1
1 1 Event: a -> 0
b 1 e 1
c 1
0
1 g
0
1 0
a0 0 b0 0 c0 0 e0
d f 0
0 1 0 0
0 1 0 0

1 1 1
0 1 1
b0 d0 f1
0
g0
1 1
d0
0 1 0 1 1 1 f1

Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 7 15

 Fault
Fault Sampling
Sampling
 A randomly selected subset (sample) of
faults is simulated.
 Measured coverage in the sample is used
to estimate fault coverage in the entire
circuit.
 Advantage: Saving in computing resources
(CPU time and memory.)
 Disadvantage: Limited data on undetected
faults.

Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 7 16

 Motivation
Motivation for
for Sampling
Sampling

 Complexity of fault simulation depends on:

 Number of gates
 Number of faults
 Number of vectors
 Complexity of fault simulation with fault
sampling depends on:
 Number of gates
 Number of vectors

Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 7 17

 Summary
Summary
 Fault simulator is an essential tool for test development.
 Concurrent fault simulation algorithm offers the best
choice.
 For restricted class of circuits (combinational and
synchronous sequential with only Boolean primitives),
differential algorithm can provide better speed and
memory efficiency (Section 5.5.6.)
 For large circuits, the accuracy of random fault sampling
only depends on the sample size (1,000 to 2,000 faults)
and not on the circuit size. The method has significant
advantages in reducing CPU time and memory needs of
the simulator.

Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 7 18