Chapter One

Introduction & Evolution of Microprocessor

 Microprocessor is the brain of Microcomputer

An integrated circuit that contains all the functions of a central processing unit of a
computer.

 It is a single chip which is capable of processing data

 It controls all components like memory, I/O and external.

 It executes sequence of instruction.

 It fetches, decodes and execute the instruction

 Its internal architecture is complex

01/16/2022 1
01/16/2022 2
01/16/2022 3
How does a Microprocessor work?

A processor basically consists of Arithmetical and Logical Unit (), Control Unit and Register
Array.

ALU:- As the name indicates ALU performs all arithmetic and logical operations on the data
received from input devices or memory.

Register array consists of a series of registers like accumulator (A), B, C, D etc.

which acts as temporary fast access memory locations for processing data.

As the name indicates, control unit controls the flow of instructions and data throughout the system.

So basically, a microprocessor takes input from input devices, process it as per instructions given in
the memory and produces output.
01/16/2022 4
Advantages of a Microprocessor

• Low Cost
Microprocessors are available at low cost due to integrated circuit technology. Which will reduce the cost of a
computer system.

• High Speed
Microprocessor chips can work at very high speed due to the technology involved in it. It is capable of executing
millions of instructions per second.

• Small Size
Due to very large scale and ultra-large-scale integration technology, a microprocessor is fabricated in a very less
footprint. This will reduce the size of the entire computer system.

• Versatile
Microprocessors are very versatile; the same chip can be used for a number of applications by simply changing
the program (instructions stored in the memory).
01/16/2022 5
 Cont…

• Low Power Consumption

Microprocessors are usually manufactured using metal oxide semiconductor technology, in which MOSFETs
(Metal Oxide Semiconductor Field Effect Transistors) are working in saturation and cut off modes. So, the
power consumption is very low compared to others.

• Less Heat Generation

Compared to vacuum tube devices, semiconductor devices won’t emit that much heat.

• Reliable
Microprocessors are very reliable; failure rate is very less as semiconductor technology is used.

• Portable
Devices or computer system made with microprocessors can be made portable due to the small size and low
power consumption.
01/16/2022 6
Common Terms used in a Microprocessor

• Bus

A bus is a set of conductors intended to transmit data, address or control information to

different elements in a microprocessor. Usually a microprocessor will have 3 types of buses:
Data Bus, Control Bus and Address Bus. An 8-bit processor will be using 8-bit wide bus.

• Instruction Set

Instruction set is the group of commands that a microprocessor can understand. So,
instruction set is an interface between hardware and software (program). An instruction
commands the processor to switch relevant transistors for doing some processing in data.
For e.g. ADD A, B; is used to add two numbers stored in the register A and B.
01/16/2022 7
 Cont…

• Word Length

Word Length is the number of bits in the internal data bus of a processor or it is the number of bits a
processor can process at a time. For e.g. An 8-bit processor will have an 8-bit data bus, 8-bit
registers and will do 8-bit processing at a time. For doing higher bits (32-bit, 16-bit) operations, it
will split that into a series of 8-bit operations.

• Cache Memory

Cache memory is a random-access memory that is integrated into the processor. So, the processor
can access data in the cache memory more quickly than from a regular RAM. It is also known as
CPU Memory. Cache memory is used to store data or instructions that are frequently referenced by
the software or program during the operation. So, it will increase the overall speed of the operation.
01/16/2022 8
 Cont…

• Clock Speed

Microprocessors uses a clock signal to control the rate at which

instructions are executed, synchronize other internal components and to
control the data transfer between them. So, clock speed refers to the
speed at which a microprocessor executes instructions. It is usually
measured in Hertz and are expressed in megahertz (MHz), gigahertz
(GHz) etc.
01/16/2022 9
 Special Purpose Processors

There are some processors which are designed to handle some specific functions.

• DSP – Digital Signal Processors:-designed for specific applications like temperature and
pleasure reading, audio, video etc..

• Coprocessors – processors used along with a main processor (8087 math-coprocessor used
with 8086)

• Input/output processors

• Transputer – Transistor Computer: Microprocessor with its own local memory

 Designed specifically for parallel computing.

 Much more flexible in its I/O capabilities/easy to connect to other machines.

01/16/2022 10
 Coprocessor continued ….
• It is a computer processor used to supplement the functions of the
primary processor (the CPU).

• Operations performed may include floating point arithmetic, graphics,

signal processing, string processing, cryptography or I/O interfacing
with peripheral devices.

01/16/2022 11
Functions of Coprocessor

A processor may not be a general-purpose processor in its own.

Processors cannot fetch instructions from memory, execute program flow control
instructions, do input/output operations, manage memory and so on.
The processor requires the host(main) processor to fetch the coprocessor instructions
and handle all other operations aside from the coprocessor functions.
In some architectures the coprocessor is a more general-purpose computer, but
carries out only a limited range of functions under the close control of a supervisory
processor.

01/16/2022 12
 Major Components of Micro Processor
Microprocessor typically consists of:

 Register: Temporary storage location for performing instruction or data.

 Arithmetic and Logic Unit(ALU): It performs all arithmetic and logical operations

 Timing and Control circuit: It keeps all other parts system(register, ALU, memory &
I/O) working together in right time sequence.

Microprocessor is connected with:

 Input device: It is used to give the input data to the microprocessor

 Out device: It is used to provide the result of calculation from the microprocessor

 01/16/2022
Memory: It is used to store data 13
Block Diagram of Microprocessor

01/16/2022 14
8086 Microprocessor Programmer’s View
1) Execution Unit: is responsible for decoding and executing all instructions.

•The EU extracts instructions from the top of the queue in the BIU, decodes
them, generates operands if necessary, passes them to the BIU and requests it
to perform the read or write byes cycles to memory or I/O and perform the
operation specified by the instruction on the operands.

01/16/2022 15
 Continued ..
Functions of execution Unit are:
 To tell bus interface unit where to fetch the instruction or data from

 To decode the instruction

 To execute the instruction

 Execution unit contains the control circuitry to perform various internal operations

Execution unit has the following function parts:

 General Purpose Registers(GPRs)

 Pointer & Index register

 ALU

 Flag register

 01/16/2022
Timing & Control unit 16
 Continued…
2) Bus Interface Unit: Functions of Bus Interface Unit are:

 Fetch the instruction or data from memory

 Write the data to the memory

 Write the data to ports

 Read the data from ports

01/16/2022 17
Conti…
Bus Interface Unit has 3 Functional Parts:

1. Instruction pointer
2. Segment Register
3. Instruction Queue
1. Instruction Pointer: It is a 16-bit register that keeps the address of memory location of coming
instruction to be executed.

2. Segment Register: The memory space 1MB of 8086 is segment into 4 blocks each block specified by
register with max size 64KB.

3. Instruction Queue: Bus Interface Unit performs its operation in parallel with execution unit. Bus
Interface Unit fetches instruction byte while execution is executing operation. The prefetched
instruction
01/16/2022 is saved in group of high speed register and is known as instruction queue. 18
3) General Purpose Registers

8086 microprocessor consists of 4 general purpose registers.

1. AX--------> Accumulator Register (16-bit registers)

 AH -------> High Accumulator Register (8-bit registers)

 AL -------> Low Accumulator Register (8-bit registers)

2. BX--------> Base Register (16 bit registers)

 BH -------> High Base Register (8-bit registers)

 BL -------> Low Base Register (8-bit registers)

01/16/2022 19
Cont…

3. CX--------> Code Register (16 bit registers)

 CH -------> High Code Register (8-bit registers)

 CL -------> Low Code Register (8-bit registers)

4. DX--------> Data Register (16 bit registers)

 DH -------> High Data Register (8-bit registers)

 DL -------> Low Data Register (8-bit registers)

01/16/2022 20
Pointer and Index registers

8086 microprocessor consists of 2 pointers and 2 index registers.

 SP--------> Stack pointer (16-bit registers)

 BP--------> Base pointer (16-bit registers)

 SI---------> Source index (16-bit registers)

 DI--------> Destination index (16-bit registers)

ALU (Arithmetic Logic Unit)

It is 16 bit and it performs Arithmetic and logical operation.

01/16/2022 21
• There are eight 16-bit general purpose registers on the 8086: ax, bx, cx, dx, si, di, bp, and
sp. While you can use many of these registers interchangeably in a computation, many
instructions work more efficiently or absolutely require a specific register from this group.

So much for general purpose

• The ax register (Accumulator) is where most arithmetic and logical computations take
place. Although you can do most arithmetic and logical operations in other registers, it is
often more efficient to use the ax register for such computations.

• The bx register (Base) has some special purposes as well. It is commonly used to hold
indirect addresses, much like the bx register on the x86 processors.
22
 Cont…
• The cx register (Count) as its name implies, counts things. You often use
it to count off the number of iterations in a loop or specify the number
of characters in a string.

• The dx register (Data) has two special purposes: it holds the overflow
from certain arithmetic operations, and it holds I/O addresses when
accessing data on the 80x86 I/O bus.

• The si and di registers (Source Index and Destination Index) have some
special purposes as well.
23
 Cont…

• You may use these registers as pointers (much like the bx register) to indirectly access
memory. You’ll also use these registers with the 8086 string instructions when
processing character strings.

• The bp register (Base Pointer) is similar to the bx register.

• You’ll generally use this register to access parameters and local variables in a
procedure.

• The sp register (Stack Pointer) has a very special purpose – it maintains the
program stack. Normally, you would not use this register for arithmetic computations.

• The proper operation of most programs depends upon the careful use of this register.
24
 Cont…
Besides the eight 16-bit registers, the 8086 CPUs also have eight 8-bit registers. Intel calls
these registers al, ah, bl, bh, cl, ch, dl, and dh. You’ve probably noticed a similarity between
these names and the names of some 16-bit registers (ax, bx, cx and dx, to be exact).

The eight-bit registers are not independent. al stands for “ax’s L.O. byte.” ah stand for “ax’s
H.O. byte.” The names of the other eight-bit registers mean the same thing with
respect to bx, cx and dx. The Figure shows the general-purpose register set.

25
 8086 Segment Registers
• The 8086 has four special segment registers: cs, ds, es, and ss. These stand for Code
Segment, Data Segment, Extra Segment, and Stack Segment, respectively. These
registers are all 16 bits wide. They deal with selecting blocks (segments) of main
memory. A segment register (e.g., cs) points at the beginning of a segment in memory.

• The code segment register points at the segment containing the currently executing
machine instructions. Note that, despite the 64K segment limitation, 8086 programs can
be longer than 64K. You simply need multiple code segments in memory. Since you can
change the value of the cs register, you can switch to a new code segment when you want to
execute the code located there.
26
 Cont…

• The data segment register, ds, generally points at global variables for the program.
Again, you’re limited to 65,536 bytes of data in the data segment; but you can always
change the value of the ds register to access additional data in other segments.

• The extra segment register, es, is exactly that – an extra segment register. 8086
programs often use this segment register to gain access to segments when it is
difficult or impossible to modify the other segment registers.

• The stack segments register points at the segment containing the 8086 stacks. The
stack is where the 8086 stores important machine state information, subroutine
return addresses, procedure parameters, and local variables.
27
 General Registers

32-bit Registers 16-bit Registers 8-bit Registers

EAX EBP AX BP AH AL

EBX ESI BX SI BH BL

ECX EDI CX DI CH CL

EDX ESP DX SP DH DL
Bits 16-31 Bits 8-15 Bits 0-7

01/16/2022 28
 4) Flags
8086 has 16-bit flags(9 flags & 7 unused flags)

Among 9 flags, we divided in to two categories:

 Status flags---> 6 status flags(carry(CF), auxiliary carry(AF), zero(ZF), sign(SF), parity(PF) & over
flow flags(OF) )

 Control flags--> 3 control flags(direction(DF), interrupt enable(IF) and trap flags(TF))

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

X X X X OF DF IF TF SF ZF X AC X PF X CF

Timing and Control Unit

The control unit of execution unit directs all internal operations and also responsible for generation
of control signal.
01/16/2022 29
Registers Summary
• AX - accumulator, and preferred for most operations.
• BX - base register, typically used to hold the address of a procedure or variable.
• CX - count register, typically used for looping.
• DX - data register, typically used for multiplication and division.
• CS – Code Segment, base location of program code
• DS – Data Segment, base location for variables
• SS – Stack Segment. Base location of the stack
• ES – Extra Segment. Additional base location for variables in memory.
• BP – Base Pointer, offset from SS register to locate variables on the stack
• SP – Stack Pointer, offset from SS register as to the location of the stack’s top
• SI – Source Index, used for copying strings, segment register varies
• DI – Destination Index, used for destination for copying strings
01/16/2022 30
 8086 Architecture

01/16/2022 31
 8086 Microprocessor (cont..)
• It is a 16 bit µp.
• 8086 has a 20 bit address bus can access upto 220 memory locations
( 1 MB) .
• It can support upto 64K I/O ports.
• It provides 14, 16-bit registers.
• It has multiplexed address and data bus AD0- AD15 and A16 – A19.
 8086 Microprocessor (cont..)
• It requires single phase clock with 33% duty cycle to provide
internal timing.
• 8086 is designed to operate in two modes, Minimum and
Maximum.
• It can prefetches upto 6 instruction bytes from memory and queues
them in order to speed up instruction execution.
• It requires +5V power supply.
• A 40 pin dual in line package.
 Architecture continued ….
It is an enhanced version of 8085 microprocessor designed by the Intel in 1976.

It is 16-bit microprocessor

Operation modes of 8086 microprocessor:

1. Minimum mode:

 It is a single processor system

 MN/MX is 1 to indicate minimum mode

 ALE for the latch is given by 8086 as it is the only processor in the circuit

 DEN and DT/R for the trans-receivers are given by 8086 itself

 Direct control signals M/IO,RD & WR are given by 8086

 The circuit is simpler

 Performance is lower
01/16/2022 34
 Conti…

2. Maximum mode:

 It is a multiprocessor system with 8086 like 8087(numeric) & 8089 (I/O)

 MN/MX is 0 to indicate maximum mode

 ALE for the latch is given by 8288 bus controller as there can be multiple processors in the
circuit

 DT/R for the trans-receivers are given by 8288 bus controller

 Instead of control signals, each processor generates status signals called s1,s2 & so

 The circuit is complex

 Performance is very high

01/16/2022 35
 Terms:-
40.  VCC (Voltage Common
Collector) is the higher voltage
41. GND:-Grounding 0 volt,[1,& 20]
0-15,16-19 AD,or A/S address & data bus
17. NMI:- non-maskable interrupt/hw
interrupt
18. INTR: Interrupt
19. CLK:- Clock
21. Reset 33. MN/MX:-min /max
22. Ready 34. BHE:-bus high
23. Test enable
24. INTA:- interrupt Acknowledgement
(QS)
25. QS:- Queue Status(ALE=address latch
enable)
26. DEN:- Data enable
27. DT/R:-data transit or receiver
28. M/IO:- memory or input output
29. WR:-Write
30. RQ/GT0:- Request/Grant
32.RD:- Read
01/16/2022 36
• Status signal : The four most significant address lines A19 through A16
are also multiplexed but in this case with status signals S6 through S3.
These status bits are output on the bus at the same time that data are
transferred over the other bus lines.
• Bit S4 and S3 together from a 2 bit binary code that identifies which
of the 8086 internal segment registers are used to generate the
physical address that was output on the address bus during the
current bus cycle.
• Code S4S3 = 00 identifies a register known as extra segment
register as the source of the segment address.
S4 S3 Segment Register
0 0 Extra
0 1 Stack
1 0 Code/none
1 1 Data
 
• Status line S5 reflects the status of another internal
characteristic of the 8086. It is the logic level of the internal
enable flag. The last status bit S6 is always at the logic 0
level.
• Control Signals : The control signals are provided to support
the 8086 memory I/O interfaces. They control functions such
as when the bus is to carry a valid address in which direction
data are to be transferred over the bus, when valid write data
are on the bus and when to put read data on the system bus.
• ALE is a pulse to logic 1 that signals external circuitry when a
valid address word is on the bus. This address must be latched in
external circuitry on the 1-to-0 edge of the pulse at ALE.
• Another control signal that is produced during the bus cycle is
BHE bank high enable. Logic 0 on this used as a memory enable
signal for the most significant byte half of the data bus D8 through
D1. These lines also serves a second function, which is as the S7
status line.
• Using the M/IO and DT/R lines, the 8086 signals which type of
bus cycle is in progress and in which direction data are to be
transferred over the bus.
Cont…

•On the other hand, logic 0 at DT/R signals that the bus is in the receive mode. This
corresponds to reading data from memory or input of data from an input port.

•The signal read RD and write WR indicates that a read bus cycle or a write bus
cycle is in progress. The 8086 switches WR to logic 0 to signal external device that
valid write or output data are on the bus.

• On the other hand, RD indicates that the 8086 is performing a read of data of the
bus. During read operations, one other control signal is also supplied. This is DEN
( data enable) and it signals external devices when they should put data on the bus.

01/16/2022 40
Cont…

• There is one other control signal that is involved with the memory and I/O
interface. This is the READY signal.

•READY signal is used to insert wait states into the bus cycle such that it is
extended by a number of clock periods. This signal is provided by an external
clock generator device and can be supplied by the memory or I/O sub-system to
signal the 8086 when they are ready to permit the data transfer to be completed.

•Interrupt signals: The key interrupt interface signals are interrupt request
(INTR) and interrupt acknowledge ( INTA).
01/16/2022 41
Cont…

•INTR is an input to the 8086 that can be used by an external device to

signal that it need to be serviced.

•Logic 1 at INTR represents an active interrupt request. When an interrupt

request has been recognized by the 8086, it indicates this fact to external
circuit with pulse to logic 0 at the INTA output.

• The TEST input is also related to the external interrupt interface.

Execution of a WAIT instruction causes the 8086 to check the logic level at
the TEST input.

01/16/2022 42
Cont…

•If the logic 1 is found, the MPU suspend operation and goes into the idle
state. The 8086 no longer executes instructions, instead it repeatedly checks the
logic level of the TEST input waiting for its transition back to logic 0.

•As TEST switches to 0, execution resume with the next instruction in the
program. This feature can be used to synchronize the operation of the 8086 to an
event in external hardware.

•There are two more inputs in the interrupt interface: the non-maskable
interrupt NMI and the reset interrupt RESET.
01/16/2022 43
Cont…

•On the 0-to-1 transition of NMI control is passed to a no maskable interrupt

service routine. The RESET input is used to provide a hardware reset for the
8086. Switching RESET to logic 0 initializes the internal register of the 8086
and initiates a reset service routine.

•DMA Interface signals: The direct memory access DMA interface of the 8086
minimum mode consist of the HOLD and HLDA signals.

01/16/2022 44
Cont…

• When an external device wants to take control of the system bus, it

signals to the 8086 by switching HOLD to the logic 1 level. At the
completion of the current bus cycle, the 8086 enters the hold state. In the
hold state, signal lines AD0 through AD15, A16/S3 through A19/S6,
BHE, M/IO, DT/R, RD, WR, DEN and INTR are all in the high Z state.
The 8086 signals external device that it is in this state by switching its
HLDA output to logic 1 level.

01/16/2022 45
01/16/2022 46
Cont…

• The function of pins 24 through 31 of 8086 varies depending upon

whether the µp is in max or min mode.

01/16/2022 47
01/16/2022 48
01/16/2022 49
01/16/2022 50
01/16/2022 51
01/16/2022 52
01/16/2022 53
01/16/2022 54
01/16/2022 55
01/16/2022 56
01/16/2022 57
01/16/2022 58
Cont…

Memory •Program, data and stack memories occupy the same memory space. As
the most of the processor instructions use 16-bit pointers the processor can
effectively address only 64 KB of memory.

•To access memory outside of 64 KB the CPU uses special segment registers to
specify where the code, stack and data 64 KB segments are positioned within 1 MB
of memory.

• Program memory - program can be located anywhere in memory. Jump and call
instructions can be used for short jumps within currently selected 64 KB code
segment,
01/16/2022
as well as for far jumps anywhere within 1 MB of memory. 59
Cont…

•Data memory - the processor can access data in any one out of 4 available
segments, which limits the size of accessible memory to 256 KB (if all four
segments point to different 64 KB blocks).

•Accessing data from the Data, Code, Stack or Extra segments can be usually
done by prefixing instructions with the DS:, CS:, SS: or ES: (some registers and
instructions by default may use the ES or SS segments instead of DS segment).

•Stack memory can be placed anywhere in memory. The stack can be located at
odd memory addresses.
01/16/2022 60
 Basic I/O Interface

• There are various communication devices like the keyboard, mouse, printer, etc. So,
we need to interface the keyboard and other devices with the microprocessor by using
latches and buffers. This type of interfacing is known as I/O interfacing.

• In addition to memory, a computer system must also provide interfaces with other
external devices, such as display unit, keyboard etc. All these external devices are
regarded as Input/output devices (usually we simply use the term I/O). In general,
memory can also be considered as some kinds of I/O from the CPU’s point of
view.
01/16/2022 61
Cont…

• The I/O (Input/Output) interface permits the microprocessor to communicate

with the outside world.

• In the 8086 microprocessor, I/O devices are connected via the address and
data buses and the mechanism is similar to the memory interface. Data
transfer takes place over the multiplexed address/data bus.

• The major difference between connection to a memory and connecting to I/O

devices is the signal level of M/IO. When accessing memory devices M/IO
is ‘1’. While M/IO is ‘0’ when accessing I/O devices.
01/16/2022 62
 5. Bus Interface
• It provides a full 16-bit bidirectional data bus and 20-bit address bus.

•The bus interface unit is responsible for performing all external bus operations.

• Specifically, it has the following functions:

•Instruction fetch, Instruction queuing, Operand fetch and storage, Address relocation and Bus control.

• The BIU uses a mechanism known as an instruction stream queue to implement a pipeline

architecture.

01/16/2022 63
 Cont..

• This queue permits prefetch of up to six bytes of instruction code.

Whenever the queue of the BIU is not full, it has room for at least two
more bytes and at the same time the EU is not requesting it to read or
write operands from memory, the BIU is free to look ahead in the
program by prefetching the next sequential instruction.

• These prefetching instructions are held in its FIFO queue. With its 16-bit
data bus, the BIU fetches two instruction bytes in a single memory cycle.

01/16/2022 64
Conti…

•After a byte is loaded at the input end of the queue, it automatically shifts up
through the FIFO to the empty location nearest the output.

•The EU accesses the queue from the output end.

• It reads one instruction byte after the other from the output of the queue.

• If the queue is full and the EU is not requesting access to operand in memory.

•These intervals of no bus activity, which may occur between bus cycles are
known as Idle state.

01/16/2022 65
Cont…
•If the BIU is already in the process of fetching an instruction when the EU
request it to read or write operands from memory or I/O, the BIU first
completes the instruction fetch bus cycle before initiating the operand read /
write cycle.

•The BIU also contains a dedicated adder which is used to generate the 20bit
physical address that is output on the address bus. This address is formed by
adding an appended 16-bit segment address and a 16-bit offset address.

01/16/2022 66
 Conti…

For example: The physical address of the next instruction to be fetched is formed by

combining the current contents of the code segment CS register and the current
contents of the instruction pointer IP register.

• The BIU is also responsible for generating bus control signals such as those for
memory read or write and I/O read or write.

• 8086's BIU produces the 20-bit physical memory address by combining a 16-bit
segment address with a 16-bit offset address.

• There are four 16-bit segment registers: the code segment (CS), the stack segment
(SS), the extra segment (ES), and the data segment (DS).
01/16/2022 67
 Cont…
• These segment registers hold the corresponding 16-bit segment addresses. A segment address is the upper 16-
bits of the starting address of that segment. The lower 4-bits of the starting address of a segment is always zero.

• The offset address is held by another 16-bit register.

• The physical 20-bit address is calculated by shifting the segment address 4-bit left and then adding that to the
offset address.

For Example:
Code segment Register CS holds the segment address which is 4569 H  Instruction pointer IP
holds the offset address which is 10A0 H 
The physical 20-bit address is calculated as follows.
Segment address :  45690 H 
Offset address       : + 10A0 H 
Physical address  :  = 46730 H
01/16/2022 68