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Virtual Memory-Unit 5

This document discusses memory organization and virtual memory concepts, including: 1. Virtual memory maps virtual addresses to physical addresses through page tables and allows main memory to act as a cache for secondary storage. 2. Key concepts include page replacement policies, page size tradeoffs, and page mapping through page tables and translation lookaside buffers (TLB). 3. Page tables store mappings of virtual to physical page numbers and include fields like valid bits, dirty bits, and protection bits. Hierarchical page tables are stored in virtual memory, requiring two memory accesses for translation.

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Manisha Rajput
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68 views

Virtual Memory-Unit 5

This document discusses memory organization and virtual memory concepts, including: 1. Virtual memory maps virtual addresses to physical addresses through page tables and allows main memory to act as a cache for secondary storage. 2. Key concepts include page replacement policies, page size tradeoffs, and page mapping through page tables and translation lookaside buffers (TLB). 3. Page tables store mappings of virtual to physical page numbers and include fields like valid bits, dirty bits, and protection bits. Hierarchical page tables are stored in virtual memory, requiring two memory accesses for translation.

Uploaded by

Manisha Rajput
Copyright
© © All Rights Reserved
Available Formats
Download as PPT, PDF, TXT or read online on Scribd
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Computer Organization

Unit 5
Memory Organization

— Virtual memory
Outline
• Introduction
• Virtual memory concepts
∗ Page replacement policies
∗ Write policy
∗ Page size tradeoff
∗ Page mapping
• Page table organization
∗ Page table entries
• Translation lookaside buffer
• Page table placement
∗ Searching hierarchical page tables
Introduction
• Cache memory enhances performance by providing faster
memory access speed.
• Virtual memory enhances performance by providing greater
memory capacity, without the expense of adding main
memory.
• Instead, a portion of a disk drive serves as an extension of
main memory.
• Virtual memory deals with the main memory size limitations
∗ Provides an illusion of having more memory than the
system’s RAM
∗ Virtual memory separates logical memory from
physical memory
» Logical memory: A process’s view of memory
» Physical memory: The processor’s view of memory
Introduction
• Virtual memory (VM) allows main memory (DRAM) to act
like a cache for secondary storage (magnetic disk).
• VM address translation a provides a mapping from the
virtual address of the processor to the physical address in
main memory or on disk.
• Virtual memory also provides
∗ Relocation
» Each program can have its own virtual address space
» Run-time details do not have any impact on code
generation
∗ Protection
» Programs are isolated from each other
» Protection can be easily implemented
Introduction
Implements a mapping
function
∗ Between virtual address
space and physical address
space
Introduction
Virtual address space is divided into fixed-size chunks
∗ These chunks are called virtual pages
∗ Virtual address is divided into
» Virtual page number
» Byte offset into a virtual page
Physical memory is also divided into similar-size
chunks
» These chunks are referred to as physical pages
» Physical address is divided into
– Physical page number
– Byte offset within a page
Virtual memory concepts
Page size is similar to cache line size
• Typical page size 4 KB
• Example
∗ 32-bit virtual address to 24-bit physical address
∗ If page size is 4 KB
» Page offset: 12 bits
» Virtual page number: 20 bits
» Physical page number: 12 bits
∗ Virtual memory maps 220 virtual pages to 212
physical pages
Virtual memory concepts
Virtual memory concepts
Virtual memory concepts

A virtual page can be


∗ In main memory
∗ On disk
• Page fault occurs if
the page is not in
memory
∗ Like a cache miss
• OS takes control and
transfers the page
∗ Demand paging
» Pages are transferred
on demand
Cache VS. VM comparisons
Parameter First-level cache Virtual memory

Block (page) 12-128 bytes 4096-65,536 bytes


size

Hit time 1-2 clock cycles 40-100 clock cycles

Miss penalty 8-100 clock cycles 700,000 – 6,000,000 clock cycles


(Access time) (6-60 clock cycles) (500,000 – 4,000,000 clock cycles)
(Transfer time) (2-40 clock cycles) (200,000 – 2,000,000 clock cycles)

Miss rate 0.5 – 10% 0.00001 – 0.001%

Data memory 0.016 – 1 MB 4MB – 4GB


size

It’s a lot like what happens in a cache


– But everything (except miss rate) is a LOT worse
Cache VS. VM comparisons
• Replacement policy:
—Replacement on cache misses primarily
controlled by hardware
—Replacement with VM (i.e. which page do I
replace?) usually controlled by OS
– Because of bigger miss penalty, want to make the
right choice
• Sizes:
—Size of processor address determines size of
VM
—Cache size independent of processor address
size
Page Replacement Policies

∗ Similar to cache replacement policies


∗ Implemented in software
» As opposed to cache’s hardware implementation
∗ Can use elaborate policies
» Due to slow lower-level memory (disk)
∗ Several policies
—Random
—FIFO: First-in-first-out
—LRU: Least-Recently-Used
—MRU: Most-Recently-Used
—OPT: (will-not-be-used-farthest-in-future)
Write policies
∗ For cache systems, we used
» Write-through
– Not good for VM due to disk writes
» Write-back
• Page size tradeoffs
∗ Factors favoring small page sizes
» Internal fragmentation
» Better match with working set
∗ Factors favoring large page sizes
» Smaller page sizes
» Disk access time
Page mapping
∗ Miss penalty is high
» Should minimize miss rate
∗ Can use fully associative mapping
» Could not use this for cache systems due to
hardware complexity
∗ Uses a translation table
» Called page table
∗ Several page table organizations are possible
Page table organization
Simple page table organization
∗ Each entry in a page table consists of
» A virtual page number (VPN)
» Corresponding physical page number (PPN)
∗ Unacceptable overhead
• Improvement
∗ Use virtual page number as index into the page
table
• Typical page table is implemented using two
data
structures
Page table organization
PTE
Page table entry
∗ Physical page number
» Gives location of the page in memory if it is in memory
∗ Disk page address
» Specifies location of the page on the disk
∗ Valid bit
» Indicates whether the page is in memory
– As in cache memory
∗ Dirty bit
» Indicates whether the page has been modified
– As in cache memory
Page table organization
Reference bit
» Used to implement pseudo-LRU
– OS periodically clears this bit
– Accessing the page turns it on
∗ Owner information
» Needed to implement proper access control
∗ Protection bits
» Indicates type of privilege
– Read-only, execute, read/write
» Example: PowerPC uses three protection bits
– Controls various types of access to user- and supervisormode
access requests
Page table organization
For large virtual address spaces
∗ Translation table must be in stored in virtual address
space
» Every address translation requires two memory
accesses:
– To get physical page number for the virtual page number
– To get the program’s memory location
• To reduce this overhead, most recently used PTEs
are kept in a cache
∗ This is called the translation lookaside buffer (TLB)
» Small in size
» 32 – 256 entries (typical)
TLB
Each TLB entry consists of
∗ A virtual page number
∗ Corresponding physical page number
∗ Control bits
» Valid bit
» Reference bit
»...
• Most systems keep separate TLBs for data and
instructions
∗ Examples: Pentium and PowerPC
Translation using TLB
Page Table Placement
Pentiums Page Table Placement

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