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WHY 8279???
WHAT WE KNOW,
8255 can be used in interfacing keyboards and displays.
The disadvantages of this method of interfacing keyboard and
display is that the processor has to refresh the display and check
the status of the keyboard periodically
using polling technique.
Thus a considerable amount of CPU time is wasted, reducing
the system operating speed.
Intel’s 8279 is a general purpose keyboard display
controller that simultaneously drives the display of a
system and interfaces a keyboard with the CPU, leaving it
free for its routine task.
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8279
Keyboard segment
Scans the keyboard,
detects key press
transmits to CPU the
characteristic s of key
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Connected to a 64 contact key matrix
Keyboard
●
●
Keyboard entries and debounced and
stored in FIFO
segment Interrupt signal is generated with each
●
entry
Display ●
●
16character scanned display
16x8 R/W memory ( RAM )
segment ●
Right entry or left entry
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BLOCK
DIA
8279
MPU
INTERFACE
KEYBOA
DISPLAY
RD
SCAN
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RE
C TU
IT E
C H OF
AR 7 9
82 A set of eight
output lines
for
A set of four
interfacing
scan lines
display
and eight
return lines
The keyboard for
display interfacing
controller chip keyboard
8279 provides IIE - SAP
●
The I/O control section controls the flow of data
I/O Control ●
to/from the 8279
The I/O section is enabled only if CS is low.
The pins A0, RD and WR select the command, status or
and Data
●
data read/write operations carried out by the CPU with
8279.
Buffers : ●
The data buffers interface the external bus of the
system with internal bus of 8279.
Control and ●
These registers store the keyboard and display modes
and other operating conditions programmed by CPU.
Timing ●
The registers are written with A0=1 and WR=0. The
Timing and control unit controls the basic timings for
Register and the operation of the circuit.
●
Scan counter divide down the operating frequency of
Timing 8279 to derive scan keyboard and scan display
frequencies.
Control :
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●
The scan counter has two modes to scan the
key matrix and refresh the display.
●
In the encoded mode, the counter provides
binary count that is to be externally decoded to
Scan ●
provide the scan lines for keyboard and display
Four externally decoded scan lines may drive
upto 16 displays.
Counter ●
In the decode scan mode, the counter
internally decodes the least significant 2 bits
and provides a decoded 1 out of 4 scan on SL0-
: ●
SL3
Four internally decoded scan lines may drive
upto 4 displays.
●
The keyboard and display both are in the same
mode at a time.
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●
This section scans for a key closure row wise. If a
Return Buffers and key closer is detected, the keyboard debounce unit
debounces the key entry (i.e. wait for 10 ms).
Keyboard De- ●
After the debounce period, if the key continues to
bounce and be detected, The code of key is directly transferred
Control: to the sensor RAM along with SHIFT and CONTROL
key status.
●
The display address register holds the address
Display Address of the word currently being written or read by
the CPU to or from the display RAM.
Registers and ●
The contents of the registers are
Display RAM : automatically updated by 8279 to accept the
next data entry by CPU.
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FIFO/S ●
In keyboard or strobed input mode, this block
ensor ●
acts as 8-byte first-in-firstout (FIFO) RAM.
Each key code of the pressed key is entered in
the order of the entry and in the mean time read
by the CPU, till the RAM become empty.
RAM ●
The status logic generates an interrupt after each
FIFO read operation till the FIFO is empty.
●
In scanned sensor matrix mode, this unit acts as
and ●
sensor RAM.
Each row of the sensor RAM is loaded with the
status of the corresponding row of sensors in the
Status ●
matrix.
If a sensor changes its state, the IRQ line goes
high to interrupt the CPU.
Logic: IIE - SAP
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●
Scanned keyboard mode
●
Scanned sensor matrix mode
●
Strobed input mode
INPUT ( keyboard) MODES
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N – key roll
over
2 key lock
out
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IS
T
HA
W
2 key
lock out
??
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IS
T
HA
W
N2–key
key
roll
lockover
out
??
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Scanned Keyboard Special Error Mode :
This mode is valid only under the N-Key rollover mode.
This mode is programmed using end interrupt / error
mode set command.
If during a single debounce period ( two keyboard scans )
two keys are found pressed , this is considered a
simultaneous depression and an error flag is set.
This flag, if set, prevents further writing in FIFO but
allows the generation of further interrupts to the CPU
for FIFO read.
The error flag can be read by reading
the FIFO status word. The error Flag is reset by sending
normal clear command with CF = 1.
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Scanned Sensor Matrix :
In this mode, a sensor array can be interfaced with 8279 using either
encoded or decoded scans. With encoded scan 8*8 sensor matrix or
with decoded scan 4*8 sensor matrix can be interfaced.
The sensor codes are stored in the CPU addressable sensor RAM.
In the sensor matrix mode, the debounce logic is inhibited. The 8-
byte FIFO RAM now acts as 8 * 8 bit memory matrix.
The status of the sensor switch matrix is fed directly to sensor RAM
matrix. Thus the sensor RAM bits contains the rowwise and column
wise status of the sensors in the sensor matrix.
The IRQ line goes high, if any change in sensor value is detected at
the end of a sensor matrix scan or the sensor RAM has a previous entry
to be read by the CPU.
The IRQ line is reset by the first data read operation, if AI = 0,
otherwise, by issuing the end interrupt command. AI is a bit in read
sensor RAM word.
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Strobed input:
In this mode, if the control lines goes low, the data on return lines, is stored in the
FIFO byte by byte.
Output (Display) Modes :
8279 provides two output
modes for selecting the
display options.
Display
Display Entry
Entry
(( right
right entry
entry or
or left
left entry
entry mode
mode ))
8279
8279 allows
allows options
options for
for data
data entry
entry
on
on the
the displays.
displays.
The
The display
display data
data is
is entered
entered for
for
display
display either
either from
from the
the right
right side
side or
or
from
from the
the left
left side.
side.
Display Scan :
In this mode 8279 provides 8
or 16 character multiplexed
displays those can be
organized as dual 4- bit or
single 8-bit display units.
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Left Entry Mode Right Entry Mode
( TYPE WRITER) ( CALCULATOR)
●
In the left entry mode, the data is entered from left
side of the display unit.
●
In this right entry mode, the first entry to
●
Address 0 of the display RAM contains the leftmost be displayed is entered on the rightmost
display characters and address 15 of the RAM contains display.
the right most display characters. ●
The next entry is also placed in the right
●
It is just like writing in our note books ie left to right.
●
In autoincrement mode, address is automatically
most display but after the previous display
updated with successive readsor writes. is shifted left by one display position.
●
The first entry is displayed on the leftmost display and ●
The leftmost characters is shifted out of that
the sixteenth entry on the rightmost display. display at the seventeenth entry and is lost,
●
The seventeenth entry is again displayed at the
i.e. it is pushed out of the display RAM.sss
leftmost display position.
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Command Words of 8279
All the command words or status words are written or
read with A0 = 1 and CS = 0 to or from 8279.
a) Keyboard Display Mode Set : The format of the command word to select different
modes of operation of 8279 is given below with its bit definitions.
D7 D6 D5 D4 D3 D2 D1 D0
0 0 0 D D K K K
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SENSOR MATRIX
SENSOR MATRIX
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B) Programmable clock :
The clock for operation of 8279 is obtained by dividing
the external clock input signal by a programmable
constant called prescaler.
PPPPP is a 5-bit binary constant.
The input frequency is divided by a decimal constant
ranging from 2 to 31, decided by the bits of an internal
prescaler, PPPPP.
D7 D6 D5 D4 D3 D2 D1 D0
0 0 1 P P P P P
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c) Read FIFO / Sensor RAM : The format of this command is given
below.
D7 D6 D5 D4 D3 D2 D1 D0
0 1 0 AI X A A A
AI – Auto Increment Flag
AAA – Address pointer to 8 bit FIFO RAM
X- Don’t care
This word is written to set up 8279 for reading FIFO/ sensor RAM.
In scanned keyboard mode, AI and AAA bits are of no use. The 8279
will automatically drive data bus for each subsequent read, in the
same sequence, in which the data was entered.
In sensor matrix mode, the bits AAA select one of the 8 rows of
RAM.
If AI flag is set, each successive read will be from the subsequent
RAM location.
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d) Read Display RAM :
This command enables a programmer to read the display RAM data.
D7 D6 D5 D4 D3 D2 D1 D0
0 1 1 AI A A A A
The CPU writes this command word to 8279 to prepare it for
display RAM read operation.
AI is auto increment flag and AAAA, the 4-bit address points to
the 16-byte display RAM that is to be read.
If AI=1, the address will be automatically, incremented after
each read or write to the Display RAM.
The same address counter is used for reading and writing.
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d) Write Display RAM :
This command enables a programmer to write the display RAM data.
D7 D6 D5 D4 D3 D2 D1 D0
1 0 0 AI A A A A
AI – Auto increment Flag.
AAAA – 4 bit address for 16-bit display RAM to be
written.
e) Display Write Inhibit/Blanking :
D7 D6 D5 D4 D3 D2 D1 D0
1 0 1 X IW IW BL BL
IW - inhibit write flag
BL - blank display bit flags
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The IW ( inhibit write flag ) bits are used to mask the individual
nibble.
The output lines are divided into two nibbles ( OUTA0 – OUTA3 )
and (OUTB0 – OUTB3 ), those can be masked by setting the
corresponding IW bit to 1.
Once a nibble is masked by setting the corresponding IW bit to
1, the entry to display RAM does not affect the nibble even
though it may change the unmasked nibble.
The blank display bit flags (BL) are used for blanking A and B
nibbles.
D0, D2 corresponds to OUTB0 – OUTB3
D1, D3 corresponds to OUTA0 - OUTA3 for blanking and
masking.
If the user wants to clear the display, blank (BL) bits are
available for each nibble as shown in format.
Both BL bits will have to be cleared for blanking both the
nibbles.
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g) Clear Display RAM :
D7 D6 D5 D4 D3 D2 D1 D0
1 1 0 CD2 CD1 CD0 CF CA
CD2 CD1 CD0
0X - All zeros ( x don’t care ) AB=00
ENABLES CLEAR DISPLAY 10 - A3-A0 =2 (0010) and B3-B0=00 (0000)
WHEN CD2=1 11 - All ones (AB =FF), i.e. clear RAM
• CD2 must be 1 for enabling the clear display command.
• If CD2 = 0, the clear display command is invoked by setting
CA(CLEAR ALL) =1 and maintaining CD1, CD0 bits exactly same as
above.
• If CF(CLEAR FIFO RAM STATUS) =1, FIFO status is cleared and IRQ
line is pulled down and the sensor RAM pointer is set to row 0.
•If CA=1, this combines the effect of CD and CF bits.
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h) End Interrupt / Error mode Set :
D7 D6 D5 D4 D3 D2 D1 D0
1 1 1 E X X X 1
E- Error mode
X- don’t care
For the sensor matrix mode, this command lowers the IRQ
line and enables further writing into the RAM.
Otherwise, if a change in sensor value is detected, IRQ
goes high that inhibits writing in the sensor RAM.
For N-Key roll over mode, if the E bit is programmed to be
‘1’, the 8279 operates in special Error mode
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I/O Interface
FIFO status register
•Code given in text for reading keyboard.
•Data returned from 8279 contains raw data that need to be translated to ASCII:
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