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Speeeeeeeeeed

This document discusses strategies for architecting speed in VHDL designs. It defines key terms like critical path, propagation delay, latency, and throughput. It explains that pipelining can improve design performance by breaking long sequences of logic into multiple clock cycles. Other strategies discussed include minimizing logic levels with multiplex decoding instead of priority decoding, using clock enables instead of gating clocks, balancing logic between registers, and choosing case statements or if statements based on the application. An example compares the clock frequencies possible with non-pipelined versus pipelined designs.

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hasan alsarraf
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54 views28 pages

Speeeeeeeeeed

This document discusses strategies for architecting speed in VHDL designs. It defines key terms like critical path, propagation delay, latency, and throughput. It explains that pipelining can improve design performance by breaking long sequences of logic into multiple clock cycles. Other strategies discussed include minimizing logic levels with multiplex decoding instead of priority decoding, using clock enables instead of gating clocks, balancing logic between registers, and choosing case statements or if statements based on the application. An example compares the clock frequencies possible with non-pipelined versus pipelined designs.

Uploaded by

hasan alsarraf
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PPT, PDF, TXT or read online on Scribd
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Architecting Speed

By
Hasan A.Abdulla

Supervised by
Dr.Basama M.Kamal
Overview
 Why Architecting Speed?
 Definitions
 Factors that lead to delay & Strategies
of speed
 Example.
Why Architecting Speed ?

Many factors effect on your design in vhdl for


time consideration , so we have to diagnosing
those factors and implementing them to get the
minimum delay in your process ,here we have
to talk about optimization methods to speed up
your program .
Definitions
important concepts related to the computation of
speed
performance.
throughput: The amount of data processed in a
single clock cycle (bits per second).
latency: The time elapsed between data input
and processed data output (clock cycles).
local data path : Delay of logic between storage
elements (nanoseconds).
Definitions
 Critical path : the path in the entire design with
the maximum propagation delay.
Definitions
set up time :the amount of time required for the input
data be stable before a clock edge.
Holding time : is the minimum amount of time required
for the input data to be stable after a clock edge.
Definitions
Definitions
Definitions
 Propagation Delay : is the amount of time
it takes for a signal to travel from a source
to a destination.
Factors that lead to delay &
Strategies of speed
 propagation delay fixing by Pipelining
 Pipelining: a process which enables parallel
execution of program instructions.
  can improve design performance by restructuring a
long data path with several levels of logic and
breaking it up over multiple clock cycles. This
method allows a faster clock cycle by relaxing the
clock-to-output and setup time requirements
between the registers.
Factors that lead to delay &
Strategies of speed

the clock speed is significantly improved by


reducing the delay of three logic levels to one
logic level and the associated routing delays
Factors that lead to delay &
Strategies of speed
 Clock Enable :
 Gating clocks is not encouraged in digital designs
because it can cause timing issues, such as
unexpected clock skews. By using the clock enable
you can achieve the same functionality without
worrying about timing issues,
 since only one signal is controlling the clock, and
only one clock is used in all related logic can be
implemented in one block to achieve better.
Factors that lead to delay &
Strategies of speed
Factors that lead to delay &
Strategies of speed
 Multiplex decoding vs. priority decoding
 multiplex decoding ( tree) is much faster than
priority ( cascading ) decoding. Or we there are 7
levels of logic from input signal, to output signal Q.
If each of the AND gates has a propagation delay
of I ns, output Q is only valid 7 ns. after input A is
valid .From Fig below the first, there are only 3
levels of logic from input signal A to output signal
Q. Therefore, output Q is valid 3 ns after input A is
valid.
Factors that lead to delay &
Strategies of speed

7 ns

3 ns
Factors that lead to delay &
Strategies of speed
 Resource Sharing
 resources when possible it might do this at the
expense of timing performance by creating longer
routes and adding to routing congestion.
Factors that lead to delay &
Strategies of speed
Minimizing logic delay – register balancing
During register balancing the logic between registers
is redistributed in order to minimize the worst-case
delay between any register pairs.
Factors that lead to delay &
Strategies of speed
Factors that lead to delay &
Strategies of speed
 Optimization speed vs. area
Factors that lead to delay &
Strategies of speed
 Coding style
Comparing If Statement and Case Statement
 The If statement generally produces priority-encoded logic.
 Case statement generally creates balanced logic
 Case statement for complex decoding and use the If statement
for speed critical paths.
Factors that lead to delay &
Strategies of speed
Factors that lead to delay &
Strategies of speed
Example
 Non pipeline & pipelined program
in this comparison we will see how pipelining design speed up
the frequency, the maximum clock frequency will increase with
pipelining .
Factors that lead to delay &
Strategies of speed

Non pipelined
Factors that lead to delay &
Strategies of speed

pipelined
Factors that lead to delay &
Strategies of speed

Non pipelined
Factors that lead to delay &
Strategies of speed

pipelined
Thank you

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